JP7305005B2 - 記憶装置 - Google Patents
記憶装置 Download PDFInfo
- Publication number
- JP7305005B2 JP7305005B2 JP2022084296A JP2022084296A JP7305005B2 JP 7305005 B2 JP7305005 B2 JP 7305005B2 JP 2022084296 A JP2022084296 A JP 2022084296A JP 2022084296 A JP2022084296 A JP 2022084296A JP 7305005 B2 JP7305005 B2 JP 7305005B2
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- JP
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- Prior art keywords
- transistor
- insulator
- electrically connected
- wiring
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
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Description
本実施の形態では、本発明の一形態であるOSトランジスタを用いた記憶装置について説明を行う。
図1は記憶装置の構成例を示すブロック図である。図1に示す記憶装置100は、セルアレイ110、周辺回路111、コントロール回路112、電位生成回路127、およびパワースイッチ(PSW)141、142を有する。
図2(A)はセル10の構成例を示すブロック図である。セル10は、メモリセルアレイ1a、メモリセルアレイ1b、メモリセルアレイ1c、メモリセルアレイ1d、および回路20を有する。
次に、図4および図5を用いて、セル10の動作について説明を行う。
図3に示すセル10は、ノードN1およびノードN2にVPREをプリチャージしてもよい。その場合の回路図を図6に示す。図6に示すセル10は、回路20に含まれるスイッチ3a乃至3dが省略され、代わりにスイッチ27およびスイッチ28が追加されている点で図3に示すセル10と異なる。
図8は図3に示すセル10の回路図を立体的に示したものである。図8において、配線CLは、容量素子C1の第2電極に電気的に接続され、GNDが与えられる。
本実施の形態では、上記実施の形態に示す記憶装置の変形例について説明する。
図11に、nチャネル型の単極性回路によって構成されたセル10の構成例を示す。図11に示す回路20は、図3に示すスイッチ4a乃至4dとしてnチャネル型のトランジスタ40a乃至40dを用いている。トランジスタ40aおよび40bのゲートには信号BE1が入力され、トランジスタ40cおよび40dのゲートには信号BE2が入力される。また、トランジスタ5a乃至5dとしてnチャネル型のトランジスタが用いられる。また、トランジスタ23のソースまたはドレインの一方、およびトランジスタ24のソースまたはドレインの一方は、電位VPREが与えられる配線と電気的に接続されている。
次に、図12に示すセル10の動作例について説明する。図13乃至図16は、図12に示すセル10の動作例を示すタイミングチャートである。なお、図13および図14は、メモリセルに記憶されたデータを読み出す際の動作を示し、図15および図16は、メモリセルにデータを書き込む際の動作を示す。
メモリセルに記憶されたデータを読み出す際の動作を、図13を用いて説明する。ここでは具体例として、メモリセル2a[0]に格納されたデータ“L”を読み出す場合の動作について詳述する。
次に、メモリセルにデータを書き込む際の動作を、図15を用いて説明する。ここでは具体例として、データ“H”が格納されたメモリセル2a[0]に、データ“L”を上書きする場合の動作について詳述する。
本実施の形態では、上記実施の形態で説明した記憶装置に供給される電源を制御する機能を有する電源制御部の構成例について、図17を用いて説明する。
以下では、実施の形態1に示すトランジスタM1に用いることが可能なOSトランジスタの構成例について、図18乃至図20を用いて説明する。
本実施の形態は、上記実施の形態に示す記憶装置が組み込まれた電子部品および電子機器の一例を示す。
まず、記憶装置100が組み込まれた電子部品の例を、図21(A)、(B)を用いて説明を行う。
次に、上記電子部品を有する電子機器の例について図22および図23を用いて説明を行う。
本実施の形態は、実施の形態1に示す記憶装置100が組み込まれたGPU(Graphics Processing Unit)について説明する。図24は、GPUの構成例を示す機能ブロック図である。
Claims (7)
- 第1トランジスタおよび第1容量素子を有する第1メモリセルと、
第2トランジスタおよび第2容量素子を有する第2メモリセルと、
第3トランジスタおよび第3容量素子を有する第3メモリセルと、
第4トランジスタおよび第4容量素子を有する第4メモリセルと、
第1乃至第4配線と、
第1乃至第4スイッチと、
センスアンプと、
第5トランジスタと、
第6トランジスタと、
第7トランジスタと、
第8トランジスタと、
第9トランジスタと、
第10トランジスタと、
第11トランジスタと、
第12トランジスタと、を有し、
前記第1トランジスタのソースまたはドレインの一方は、前記第1配線に電気的に接続され、
前記第1トランジスタのソースまたはドレインの他方は、前記第1容量素子に電気的に接続され、
前記第2トランジスタのソースまたはドレインの一方は、前記第2配線に電気的に接続され、
前記第2トランジスタのソースまたはドレインの他方は、前記第2容量素子に電気的に接続され、
前記第3トランジスタのソースまたはドレインの一方は、前記第3配線に電気的に接続され、
前記第3トランジスタのソースまたはドレインの他方は、前記第3容量素子に電気的に接続され、
前記第4トランジスタのソースまたはドレインの一方は、前記第4配線に電気的に接続され、
前記第4トランジスタのソースまたはドレインの他方は、前記第4容量素子に電気的に接続され、
前記センスアンプは第1ノードおよび第2ノードを有し、
前記第1配線は、前記第1スイッチを介して、前記第1ノードに電気的に接続され、
前記第2配線は、前記第2スイッチを介して、前記第2ノードに電気的に接続され、
前記第3配線は、前記第3スイッチを介して、前記第1ノードに電気的に接続され、
前記第4配線は、前記第4スイッチを介して、前記第2ノードに電気的に接続され、
前記第5トランジスタのソースまたはドレインの一方は、前記第1ノードと電気的に接続され、
前記第5トランジスタのソースまたはドレインの他方は、前記第6トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第5トランジスタのゲートは、前記第1配線と電気的に接続され、
前記第7トランジスタのソースまたはドレインの一方は、前記第2ノードと電気的に接続され、
前記第7トランジスタのソースまたはドレインの他方は、前記第8トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第7トランジスタのゲートは、前記第2配線と電気的に接続され、
前記第9トランジスタのソースまたはドレインの一方は、前記第1ノードと電気的に接続され、
前記第9トランジスタのソースまたはドレインの他方は、前記第10トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第9トランジスタのゲートは、前記第3配線と電気的に接続され、
前記第11トランジスタのソースまたはドレインの一方は、前記第2ノードと電気的に接続され、
前記第11トランジスタのソースまたはドレインの他方は、前記第12トランジスタのソースまたはドレインの一方と電気的に接続され、
前記第11トランジスタのゲートは、前記第4配線と電気的に接続され、
前記センスアンプは、前記第1ノードと前記第2ノードの電位差を増幅する記憶装置。 - 請求項1において、
前記第1乃至第4スイッチは、トランジスタを含む記憶装置。 - 請求項1において、
前記第1乃至第4スイッチは、nチャネル型のトランジスタによって構成され、
前記センスアンプは、nチャネル型のトランジスタを用いた単極性回路によって構成されている記憶装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1乃至第4トランジスタは、チャネル形成領域に酸化物半導体を含む記憶装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1乃至第4メモリセルは、前記センスアンプよりも上層に設けられる記憶装置。 - 請求項1乃至請求項5のいずれか一項において、
前記第1配線の電位を、前記第1メモリセルに保持されたデータに対応する電位とした後、前記第6トランジスタ、および前記第8トランジスタをオンにする機能を有する記憶装置。 - 請求項6において、
前記第1配線、および前記第2配線をプリチャージした後、前記第1配線の電位を、前記第1メモリセルに保持されたデータに対応する電位とする機能を有する記憶装置。
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TWI842855B (zh) | 2019-03-29 | 2024-05-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
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CN113748463A (zh) | 2019-05-23 | 2021-12-03 | 株式会社半导体能源研究所 | 半导体装置 |
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