JP7254956B2 - 三次元メモリデバイスおよびその製作方法 - Google Patents
三次元メモリデバイスおよびその製作方法 Download PDFInfo
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- JP7254956B2 JP7254956B2 JP2021554774A JP2021554774A JP7254956B2 JP 7254956 B2 JP7254956 B2 JP 7254956B2 JP 2021554774 A JP2021554774 A JP 2021554774A JP 2021554774 A JP2021554774 A JP 2021554774A JP 7254956 B2 JP7254956 B2 JP 7254956B2
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Description
101 第1の基板
110 周辺領域
114 アレイウェル構造
116 nウェル領域
118 pウェル領域
120 階段アレイ領域
201 交互誘電体スタック
205 交互誘電エッチング停止構造
206 導体層
210 交互導電体/誘電体スタック
212 導体層
214 第1の誘電層、酸化物層
218 第2の誘電層、窒化物層
220 アレイデバイス
230 NANDストリング
240 階段構造
250 絶縁層
300 周辺領域
310 鉛直貫通コンタクト
312 第1の鉛直コンタクト
314 第2の鉛直コンタクト
316 ワード線コンタクト
320 コンタクト層
323 相互接続コンタクト
325 誘電層
330 アレイ結合層
336 誘電層
338 結合構造
400 CMOSウェハ
401 第2の基板
410 周辺回路層、CMOSデバイス層
412 CMOSデバイス
420 コンタクト層
423 相互接続コンタクト
425 誘電層
430 CMOS結合層
436 誘電層
438 結合構造
540 底基板
600 交互誘電体スタック
610 貫通基板開口
730 隔離層
740 貫通基板コンタクト
810 保護層
820 アレイパッド
Claims (18)
- 三次元(3D)メモリデバイスを形成するための方法であって、
エッチング停止構造を第1のウェハ内に形成するステップと、
前記エッチング停止構造と接触する第1の貫通コンタクトを形成するステップと、
前記第1の貫通コンタクトを第2のウェハのCMOSデバイスに電気的に接続するために、前記第1のウェハを前記第2のウェハに接合するステップと、
前記第1のウェハの第1の基板および前記エッチング停止構造を貫通し、前記第1の貫通コンタクトを通じて前記CMOSデバイスと電気的に接触する貫通基板コンタクトを形成するステップと
を含み、
前記エッチング停止構造は、
第1の誘電層と、前記第1の誘電層と異なる第2の誘電層とを各々が備える少なくとも2つの誘電層対を備える、方法。 - 前記第1の基板内にアレイウェル構造を形成するステップと、
前記アレイウェル構造と接触する第2の貫通コンタクトを形成するステップと
をさらに含む、請求項1に記載の方法。 - 前記第1の基板上に交互誘電体スタックを形成するステップと、
前記エッチング停止構造と、階段構造とを同時に形成するために、前記交互誘電体スタックの一部分を除去するステップと
をさらに含む、請求項2に記載の方法。 - 前記交互誘電体スタックを交互導電体/誘電体スタックに変換するステップと、
前記交互導電体/誘電体スタックを鉛直に貫通する複数のNANDストリングを形成するステップと
をさらに含む、請求項3に記載の方法。 - 前記エッチング停止構造、前記アレイウェル構造、および前記交互導電体/誘電体スタックを覆う絶縁層を形成するステップと、
前記階段構造においてワード線と接触するワード線コンタクトを形成するステップと
をさらに含み、
前記第1の貫通コンタクト、前記第2の貫通コンタクト、および前記ワード線コンタクトは、同じコンタクト形成工程によって前記絶縁層内に同時に形成される、請求項4に記載の方法。 - 前記絶縁層上に、複数の第1の相互接続コンタクトを備える第1のコンタクト層を形成するステップと、
前記第1のコンタクト層上にアレイ結合層を形成するステップと
をさらに含む、請求項5に記載の方法。 - 周辺回路層を前記第2のウェハの第2の基板上に形成するステップと、
前記周辺回路層上に、複数の第2の相互接続コンタクトを備える第2のコンタクト層を形成するステップと、
前記少なくとも1つの第2のコンタクト層上にCMOS結合層を形成するステップと
をさらに含む、請求項6に記載の方法。 - 前記第1のウェハを前記第2のウェハに接合するステップは、
前記第1の貫通コンタクトが、少なくとも1つの第1の相互接続コンタクトおよび少なくとも1つの第2の相互接続コンタクトを通じて前記周辺回路層へと電気的に接続されるように、前記第1のウェハの前記アレイ結合層を前記第2のウェハの前記CMOS結合層に接合するステップと
を含む、請求項7に記載の方法。 - 前記貫通基板コンタクトを形成するステップは、
前記第1の基板を貫通する貫通基板開口を形成するステップと、
前記第1の基板を覆い、前記貫通基板開口を満たす隔離層を形成するステップと、
前記隔離層、前記貫通基板開口、および前記エッチング停止構造を貫通し、前記第1の貫通コンタクトの少なくとも一部分を露出させる鉛直貫通開口を形成するステップと、
前記貫通基板コンタクトが前記第1の貫通コンタクトと接触するように、前記貫通基板コンタクトを前記鉛直貫通開口内に形成するステップと
を含む、請求項8に記載の方法。 - 前記貫通基板開口を形成するステップは、
前記貫通基板開口を前記第1の基板内に形成するためにディーププラズマエッチングを使用するステップを含み、
前記ディーププラズマエッチングの間のプラズマの高エネルギー流が前記エッチング停止構造および前記アレイウェル構造によって阻止される、請求項9に記載の方法。 - 前記貫通基板コンタクトを形成するステップは、
前記貫通基板コンタクトと接触するアレイパッドを形成するステップと、
前記少なくとも1つのアレイパッドを露出させるためにパッド開口を形成するステップと
をさらに含む、請求項9に記載の方法。 - 第1のウェハであって、
第1の基板、
前記第1の基板上のエッチング停止構造、
前記エッチング停止構造上の絶縁層における第1の貫通コンタクト、ならびに、
前記第1の基板および前記エッチング停止構造を貫通し、前記第1の貫通コンタクトと接触する貫通基板コンタクト
を備える第1のウェハと、
前記第1の貫通コンタクトを介して前記貫通基板コンタクトに電気的に接続される周辺回路層を備える、前記第1のウェハに接合される第2のウェハと
を備え、
前記エッチング停止構造は、
第1の誘電層と、前記第1の誘電層と異なる第2の誘電層とを各々が備える少なくとも2つの誘電層対を備える、三次元(3D)メモリデバイス。 - 前記第1のウェハは、
前記第1の基板におけるアレイウェル構造と、
前記アレイウェル構造と接触する第2の貫通コンタクトと
をさらに備える、請求項12に記載の3Dメモリデバイス。 - 前記第1のウェハは、
前記第1の基板における交互導電体/誘電体スタックと、
前記交互導電体/誘電体スタックを鉛直に貫通する複数のNANDストリングと、
前記交互導電体/誘電体スタックの横側面における階段構造と
をさらに備える、請求項13に記載の3Dメモリデバイス。 - 前記第1のウェハは、
前記階段構造におけるワード線と接触するワード線コンタクト
をさらに備え、
前記第1の貫通コンタクト、前記第2の貫通コンタクト、および前記ワード線コンタクトは前記絶縁層を貫通する、請求項14に記載の3Dメモリデバイス。 - 前記第1のウェハは、
前記絶縁層を覆い、第1の相互接続コンタクトを備える第1のコンタクト層と、
前記第1のコンタクト層と前記第2のウェハとの間のアレイ結合層と
をさらに備える、請求項14に記載の3Dメモリデバイス。 - 前記第2のウェハは、
前記周辺回路層上の、第2の相互接続コンタクトを備える第2のコンタクト層と、
前記少なくとも1つの第2のコンタクト層と前記アレイ結合層との間のCMOS結合層と
を備える、請求項16に記載の3Dメモリデバイス。 - 前記第1のウェハは、
前記貫通基板コンタクトと接触するパッドをさらに備え、
前記パッドは、前記第1の貫通コンタクト、前記第1の相互接続コンタクト、および前記第2の相互接続コンタクトを通じて前記第2のウェハの前記周辺回路層に電気的に接続される、請求項17に記載の3Dメモリデバイス。
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