JP2022524205A - 三次元メモリデバイスおよびその製作方法 - Google Patents
三次元メモリデバイスおよびその製作方法 Download PDFInfo
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- JP2022524205A JP2022524205A JP2021554774A JP2021554774A JP2022524205A JP 2022524205 A JP2022524205 A JP 2022524205A JP 2021554774 A JP2021554774 A JP 2021554774A JP 2021554774 A JP2021554774 A JP 2021554774A JP 2022524205 A JP2022524205 A JP 2022524205A
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Abstract
Description
101 第1の基板
110 周辺領域
114 アレイウェル構造
116 nウェル領域
118 pウェル領域
120 階段アレイ領域
201 交互誘電体スタック
205 交互誘電エッチング停止構造
206 導体層
210 交互導電体/誘電体スタック
212 導体層
214 第1の誘電層、酸化物層
218 第2の誘電層、窒化物層
220 アレイデバイス
230 NANDストリング
240 階段構造
250 絶縁層
300 周辺領域
310 鉛直貫通コンタクト
312 第1の鉛直コンタクト
314 第2の鉛直コンタクト
316 ワード線コンタクト
320 コンタクト層
323 相互接続コンタクト
325 誘電層
330 アレイ結合層
336 誘電層
338 結合構造
400 CMOSウェハ
401 第2の基板
410 周辺回路層、CMOSデバイス層
412 CMOSデバイス
420 コンタクト層
423 相互接続コンタクト
425 誘電層
430 CMOS結合層
436 誘電層
438 結合構造
540 底基板
600 交互誘電体スタック
610 貫通基板開口
730 隔離層
740 貫通基板コンタクト
810 保護層
820 アレイパッド
Claims (20)
- 三次元(3D)メモリデバイスを形成するための方法であって、
周辺領域および階段アレイ領域を備えるアレイウェハを形成するステップであって、
前記周辺領域において第1の基板上に交互誘電エッチング停止構造を形成するステップ、
前記階段アレイ領域において前記第1の基板上にアレイデバイスを形成するステップ、および、
前記周辺領域において、前記交互誘電エッチング停止構造と接触する少なくとも1つの第1の鉛直貫通コンタクトを形成するステップ
を含む、ステップと、
CMOSウェハを形成するステップと、
前記アレイウェハと前記CMOSウェハとを接合するステップと、
前記第1の基板および前記交互誘電エッチング停止構造を貫通し、前記少なくとも1つの第1の鉛直貫通コンタクトと接触する少なくとも1つの貫通基板コンタクトを形成するステップと
を含む方法。 - 前記アレイウェハを形成するステップは、
前記周辺領域において前記第1の基板内にアレイウェル構造を形成するステップと、
前記アレイウェル構造と接触する少なくとも1つの第2の鉛直貫通コンタクトを形成するステップと
をさらに含む、請求項1に記載の方法。 - 前記アレイウェハを形成するステップは、
前記第1の基板上に交互誘電体スタックを形成するステップと、
前記周辺領域における前記交互誘電エッチング停止構造と、前記階段アレイ領域における前記交互誘電体スタックの少なくとも1つの横側面上における階段構造とを同時に形成するために、前記交互誘電体スタックの一部分を除去するステップと
をさらに含む、請求項2に記載の方法。 - 前記アレイデバイスを形成するステップは、
前記階段アレイ領域における前記交互誘電体スタックを交互導電体/誘電体スタックに変換するステップと、
前記交互導電体/誘電体スタックを鉛直に貫通する複数のNANDストリングを形成するステップと
を含む、請求項3に記載の方法。 - 前記アレイウェハを形成するステップは、
前記交互誘電エッチング停止構造、前記アレイウェル構造、および前記アレイデバイスを覆う絶縁層を形成するステップと、
前記階段アレイ領域において、前記階段構造におけるワード線と接触する少なくとも1つのワード線コンタクトを形成するステップと
をさらに含み、
前記少なくとも1つの第1の鉛直貫通コンタクト、前記少なくとも1つの第2の鉛直貫通コンタクト、および前記少なくとも1つのワード線コンタクトは、同じコンタクト形成工程によって前記絶縁層内に同時に形成される、請求項3に記載の方法。 - 前記アレイウェハを形成するステップは、
前記絶縁層上に、複数の第1の相互接続コンタクトを備える少なくとも1つの第1のコンタクト層を形成するステップと、
前記少なくとも1つの第1のコンタクト層上にアレイ結合層を形成するステップと
をさらに含む、請求項4に記載の方法。 - 前記CMOSウェハを形成するステップは、
周辺回路層を第2の基板上に形成するステップと、
前記周辺回路層上に、複数の第2の相互接続コンタクトを備える少なくとも1つの第2のコンタクト層を形成するステップと、
前記少なくとも1つの第2のコンタクト層上にCMOS結合層を形成するステップと
を含む、請求項6に記載の方法。 - 前記アレイウェハを前記CMOSウェハに接合するステップは、
前記CMOSウェハの方へ下に向けるために前記アレイウェハをひっくり返すステップと、
前記少なくとも1つの第1の鉛直貫通コンタクトが、少なくとも1つの第1の相互接続コンタクトおよび少なくとも1つの第2の相互接続コンタクトを通じて前記周辺回路層へと電気的に接続されるように、前記アレイウェハの前記アレイ結合層を前記CMOSウェハの前記CMOS結合層に接合するステップと
を含む、請求項7に記載の方法。 - 前記少なくとも1つの貫通基板コンタクトを形成するステップは、
前記第1の基板を貫通する少なくとも1つの貫通基板開口を形成するステップと、
前記第1の基板を覆い、前記少なくとも1つの貫通基板開口を満たす隔離層を形成するステップと、
前記隔離層、前記少なくとも1つの貫通基板開口、および前記交互誘電エッチング停止構造を貫通し、前記少なくとも1つの第1の鉛直貫通コンタクトの少なくとも一部分を露出させる少なくとも1つの鉛直貫通開口を形成するステップと、
前記少なくとも1つの貫通基板コンタクトが前記少なくとも1つの第1の鉛直コンタクトと接触するように、前記少なくとも1つの貫通基板コンタクトを前記少なくとも1つの鉛直貫通開口内に形成するステップと
を含む、請求項8に記載の方法。 - 少なくとも1つの貫通基板開口を形成するステップは、
前記少なくとも1つの貫通基板開口を前記第1の基板内に形成するためにディーププラズマエッチングを使用するステップを含み、
前記ディーププラズマエッチングの間のプラズマの高エネルギー流が前記交互誘電エッチング停止構造および前記アレイウェル構造によって阻止される、請求項9に記載の方法。 - 前記少なくとも1つの貫通基板コンタクトを形成するステップは、
前記少なくとも1つの貫通基板コンタクトと接触する少なくとも1つのアレイパッドを形成するステップと、
前記少なくとも1つのアレイパッドを露出させるために少なくとも1つのパッド開口を形成するステップと
をさらに含む、請求項10に記載の方法。 - 周辺領域および階段アレイ領域を備えるアレイウェハであって、
第1の基板、
前記周辺領域における前記第1の基板上の交互誘電エッチング停止構造、
前記階段アレイ領域における前記第1の基板上のアレイデバイス、
前記周辺領域における少なくとも1つの第1の鉛直貫通コンタクト、および、
前記第1の基板および前記交互誘電エッチング停止構造を貫通し、前記少なくとも1つの第1の鉛直貫通コンタクトと接触する少なくとも1つの貫通基板コンタクト
を備えるアレイウェハと、
前記少なくとも1つの第1の鉛直貫通コンタクトを通じて前記少なくとも1つの貫通基板コンタクトに電気的に接続される周辺回路層を備える、前記アレイウェハに接合されるCMOSウェハと
を備える三次元(3D)メモリデバイス。 - 前記アレイウェハは、
前記周辺領域における前記第1の基板においてのアレイウェル構造と、
前記アレイウェル構造と接触する少なくとも1つの第2の鉛直貫通コンタクトと
をさらに備える、請求項12に記載の3Dメモリデバイス。 - 前記交互誘電エッチング停止構造は、
第1の誘電層と、前記第1の誘電層と異なる第2の誘電層とを各々が備える少なくとも2つの誘電層対を備える、請求項13に記載の3Dメモリデバイス。 - 前記アレイデバイスは、
前記第1の基板における交互導電体/誘電体スタックと、
前記交互導電体/誘電体スタックを鉛直に貫通する複数のNANDストリングと、
前記交互導電体/誘電体スタックの少なくとも1つの横側面における階段構造と
を備える、請求項13に記載の3Dメモリデバイス。 - 前記アレイウェハは、
前記交互誘電エッチング停止構造、前記アレイウェル構造、および前記アレイデバイスを覆う絶縁層と、
前記階段アレイ領域において、前記階段構造におけるワード線と接触する少なくとも1つのワード線コンタクトと
をさらに備え、
前記少なくとも1つの第1の鉛直貫通コンタクト、前記少なくとも1つの第2の鉛直貫通コンタクト、および前記少なくとも1つのワード線コンタクトは前記絶縁層を貫通する、請求項15に記載の3Dメモリデバイス。 - 前記アレイウェハは、
前記絶縁層を覆う、複数の第1の相互接続コンタクトを備える少なくとも1つの第1のコンタクト層と、
前記少なくとも1つの第1のコンタクト層と前記CMOSウェハとの間のアレイ結合層と
をさらに備える、請求項16に記載の3Dメモリデバイス。 - 前記CMOSウェハは、
第2の基板上の周辺回路層と、
前記周辺回路層上の、複数の第2の相互接続コンタクトを備える少なくとも1つの第2のコンタクト層と、
前記少なくとも1つの第2のコンタクト層と前記アレイ結合層との間のCMOS結合層と
を備える、請求項17に記載の3Dメモリデバイス。 - 前記アレイウェハは、
前記第1の基板を覆う隔離層をさらに備え、
前記少なくとも1つの貫通基板コンタクトは、前記隔離層および前記交互誘電エッチング停止構造を貫通し、前記少なくとも1つの第1の鉛直コンタクトと接触する、請求項18に記載の3Dメモリデバイス。 - 前記アレイウェハは、
前記少なくとも1つの貫通基板コンタクトと接触する少なくとも1つのアレイパッドをさらに備え、
前記少なくとも1つのアレイパッドは、前記少なくとも1つの第1の鉛直貫通コンタクト、前記少なくとも1つの第1の相互接続コンタクト、および前記少なくとも1つの第2の相互接続コンタクトを通じて前記CMOSウェハの前記周辺回路層に電気的に接続される、請求項19に記載の3Dメモリデバイス。
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KR102649964B1 (ko) | 2024-03-21 |
US20210343742A1 (en) | 2021-11-04 |
EP3912189B1 (en) | 2023-08-02 |
TW202107688A (zh) | 2021-02-16 |
KR20210126675A (ko) | 2021-10-20 |
CN110574162A (zh) | 2019-12-13 |
EP3912189A4 (en) | 2022-08-31 |
US20210036006A1 (en) | 2021-02-04 |
TWI803732B (zh) | 2023-06-01 |
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