JP7238621B2 - 半導体装置、焼結シートの製造方法、半導体装置の製造方法 - Google Patents
半導体装置、焼結シートの製造方法、半導体装置の製造方法 Download PDFInfo
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- JP7238621B2 JP7238621B2 JP2019114680A JP2019114680A JP7238621B2 JP 7238621 B2 JP7238621 B2 JP 7238621B2 JP 2019114680 A JP2019114680 A JP 2019114680A JP 2019114680 A JP2019114680 A JP 2019114680A JP 7238621 B2 JP7238621 B2 JP 7238621B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
第1実施形態について説明する。本実施形態の半導体装置は、第1支持部材10、半導体チップ20、ターミナル30、第2支持部材40等を備えた構成されている。また、半導体装置は、下層焼結部材50、中層焼結部材60、上層焼結部材70を備えた構成とされている。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
20a 表面
60 中層焼結部材
60a 一面
61 凹部
Claims (6)
- 半導体チップ(20)と被接合部材(30、40)とが焼結部材(60)を介して接合された半導体装置であって、
表面(20a)側に凸部(21)を有する前記半導体チップと、
前記被接合部材と、
前記半導体チップの表面側と前記被接合部材との間に配置され、前記半導体チップと前記被接合部材とを接合する前記焼結部材と、を備え、
前記焼結部材は、前記半導体チップの表面側と対向する一面(60a)側に、前記半導体チップの凸部に対応する凹部(61)が形成されており、
前記焼結部材は、前記凹部の底面と前記被接合部材との間に位置する部分が、当該部分と異なる部分より、焼結密度が小さくなっている半導体装置。 - 前記半導体チップは、前記凸部が所定方向に沿って延設されており、
前記凸部の延設方向と交差する方向であり、前記半導体チップの面方向に沿った方向の長さを幅とすると、
前記凸部の幅に対する前記凹部の幅の割合は、300%以下とされている請求項1に記載の半導体装置。 - 前記焼結部材は、前記凹部を構成する壁面が前記凸部と離れている請求項1または2に記載の半導体装置。
- 前記焼結部材は、銀焼結体、または銅焼結体である請求項1ないし3のいずれか1つに記載の半導体装置。
- 表面(20a)側に凸部(21)を有する半導体チップ(20)の前記表面側と被接合部材(30、40)との間に配置される焼結部材(60)を構成する焼結シートの製造方法であって、
一面(200a)側に、前記凸部に対応する凹部形成用凸部(201)が形成された治具(200)を用意することと、
前記治具の一面に、焼結材料(610)を配置することと、
前記焼結材料に前記被接合部材を接触させ、加熱しながら前記被接合部材を加圧することにより、前記被接合部材に、前記凹部形成用凸部に対応する凹部が形成された前記焼結材料を転写することと、を行う焼結シートの製造方法。 - 半導体チップ(20)と被接合部材(30、40)とが焼結部材(52)を介して接合された半導体装置の製造方法であって、
表面(20a)側に凸部(21)を有する前記半導体チップを用意することと、
一面(200a)側に、前記凸部に対応する凹部形成用凸部(201)が形成された治具(200)を用意することと、
前記治具の一面に、焼結材料(610)を配置することと、
前記焼結材料に前記被接合部材を接触させ、加熱しながら前記被接合部材を加圧することにより、前記被接合部材に、前記凹部形成用凸部に対応する凹部が形成された前記焼結材料を転写して焼結シート(600)を配置することと、
前記半導体チップの表面側に、前記凸部と前記凹部とが対向するように、前記焼結シートを介して前記被接合部材を配置することと、
加熱しながら加圧することにより、前記焼結シートから前記焼結部材を構成して前記半導体チップと前記被接合部材とを接合することと、を行う半導体装置の製造方法。
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JP2018026417A (ja) | 2016-08-09 | 2018-02-15 | 三菱電機株式会社 | 電力用半導体装置 |
JP2018190936A (ja) | 2017-05-11 | 2018-11-29 | 富士電機株式会社 | 金属接合体、金属接合体の製造方法、半導体装置および半導体装置の製造方法 |
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JPH11121527A (ja) * | 1997-10-21 | 1999-04-30 | Pfu Ltd | ベアチップ実装方法およびセラミック基板の製造方法およびセラミック基板ならびに半導体装置 |
JP2001138041A (ja) | 1999-11-09 | 2001-05-22 | Mitsubishi Materials Corp | 焼結金属接合体の製造方法 |
US9589860B2 (en) * | 2014-10-07 | 2017-03-07 | Nxp Usa, Inc. | Electronic devices with semiconductor die coupled to a thermally conductive substrate |
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JP2014157926A (ja) | 2013-02-15 | 2014-08-28 | National Institute Of Advanced Industrial & Technology | 接合方法及び半導体モジュールの製造方法 |
JP2017005037A (ja) | 2015-06-08 | 2017-01-05 | 三菱電機株式会社 | 電力用半導体装置 |
JP2018026417A (ja) | 2016-08-09 | 2018-02-15 | 三菱電機株式会社 | 電力用半導体装置 |
JP2018190936A (ja) | 2017-05-11 | 2018-11-29 | 富士電機株式会社 | 金属接合体、金属接合体の製造方法、半導体装置および半導体装置の製造方法 |
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