201117338 六、發明說明： [0001] 【發明所屬之技術領域】 本發明涉及一種功率半導體I 別涉及一種用於功率半導體I 架及製作方法。 置的封裝結構 置封裝的混合 和製造，特 A金引線框 [先前技術】 [0002] 引線框架的主要功点疋為晶片提供機 為導電介質連接频電路外部電路傳^栽體’並作 與封裝材料-起，向外散發晶片卫作時^信號’以及 為積體電路中極為關鍵的零部祙，机: 的熱量’成 丨1干對於功率半導體萝 ，由於功耗高，引線《中的散熱片成為 ^ 片散熱能力的主要手段。 " 如中國專利公開號CN1738012A中， I路了 一種給晶片增 加散熱片的方法，該方法包括將排列成陣列的晶片輸入 到上片機中’通過上片機上的多_嘴料所述散熱片 陣列’並將所述散熱片陣列放置到所述晶^陣列上然 後將所述散熱片陣列切割分開，該方法可以對一個陣列 的晶片進行上片，大大提高了上片欵率，然而，該處理 方法比較繁m性差，減無料㈣速處理大規 模的晶片散熱問題。 在現有技術中引線框架普遍採用銅合金引線框架，其分 為兩種’一種為異型材銅合金引線框架，它是在引腳和 散熱片部分採用不同厚度的銅合金，一體成型，另一種 為同型材銅合金引線框架，它是在引腳和散熱片部分採 用相同厚度的銅合金，一禮成型。其中，對於異型材銅 合金引線框架的，由於製造手段和成本的限制，不容易 098137925 表單編號A0101 第4頁/共38頁 201117338 [0003] 得到很厚的異型材銅合金散熱片’而同型材銅合金引線 框，由於散熱片薄，其散熱性能差並且會增加塑封料的 耗用量。另外無論是異型材銅合金引線框架還是同型材 銅合金引線框架，其價格昂貴，製造成本高。 【發明内容】 本發明的目的是提供一種應用於功率半導體裝置的溫合 合金引線框架及製作方法，該混合合金引線框架具有高 的熱容比，其製造過程靈活、簡單，能夠節約工藝製作 材料，降低製作成本。 Ο 為了達到上述目的’本發明的技術方案是：—種功率半 導體裝置的混合合金引線框架陣列，其特點是，勺括. 多個散熱片、一個引腳陣列；' 所述的散熱片由第一種材料製成，其上部設有散執片定 位孔，下部中央部位設有散熱片焊接區; 所述的引腳陣列由與第一種材料不同的第二種材料製成 ’設置在上下兩個散熱片之間，該弓|腳陣列上下兩端分 別引出多個引腳端子組。 ο 上述-種功率半導體裝置的混合合金引線框架，其中， 所述的每個散熱片上還包括一個晶片載片Α。 上述-種功率半導體裝置的混合合金引線框架，其中， 所述的每個引腳端子組包含三則腳端子，每個引腳端 子組的中⑸丨腳端子上分別設有與散熱片焊接區對應的 弓丨腳焊接區。 098137925 上述-種功率半導财置的混合合金⑽框架，其中， 所述的每個引腳焊接區上延伸出一個晶片載片二。 上述-種功率半導體裝置的混合合幻丨線框^其中， 表單編號A0101 第5頁/共38頁 、 0983408055-0 201117338 所述的第一種材料為紹合金。 上述一種功率半導體裝置的混合合金引線框架，其中， 所述的散熱片的马·度為2ηιιπ。 上述一種功率半導體裝置的混合合金引線框架，其中， 所述的第二種材料為銅合金。 一種應用混合合金引線框架封裝功率半導體裝置的製作 方法，其特點是，包括以下步驟. 步驟1、製作引線框架組焊板，該引線框架組焊板的上部 和下部對應設置多組凹槽，每個凹槽内設置若干個散熱 片定位柱，在引線樞架參轉板的申部設置多個引腳定位 柱； ,_ 步驟2、製作散熱片，在散熱片的上部設置一個散熱片定 位孔，在散熱片的下部中央部位設置散熱片焊接區； 步驟3、製作引腳陣列’在引腳陣列上下兩端分別引出多 組三個一組的引腳端子組，其中，在引腳端子組的中間 引腳端子上分別設置與散義片焊揍复對應的引腳焊接區 ，兩個引腳端子組之間設置多個引腳定位孔； 步驟4、通過弓丨線框鉍組焊板的散熱片定位柱及散熱片定 位孔，將散熱片定位在引線框架組焊板的凹槽内； 步驟5、通過引線框架組焊板的引腳定位柱及引腳定位孔 ，將引腳定位在引線框架組焊板上的上下散熱片之間的 部位； 步驟6、將散熱片和引腳連接； 步驟7 '從引線框架組焊板上卸下連接在一起的散熱片和 引腳，清洗散熱片和引腳。 上述的製作方法，其中，步驟2還包括 098137925 表單編號A0101 第6頁/共38頁 〇沿 201117338 步驟2. 1、在散熱片上設置晶片載片台。 上述的製作方法，其中，步驟3還包括： 步驟3. 1、引腳焊接區上延伸出晶片載片台； 步驟3.2、將晶片固定在晶片載片臺上； 步驟3. 3、通過引線將晶片與引腳的引腳端子連接。 上述的製作方法，其中，步驟2. 1還包括將晶片固定在晶 片載片台。 上述的製作方法，其中，步驟3還包括： 步驟3. 1、在引腳端子上延伸跳線。 Ο 上述用於功率半導體裝置的混合合金引線框架的製作方 法，其中，步驟6還包括： 步驟6. 1、通過跳線將晶片與引腳端子連接。 上述的製作方法，其中，所述將晶片固定在晶片載片臺 上的方法為焊錫固定。 一種功率半導體裝置的封裝，其特點是，包括： 一個功率半導體晶片、一引線框架和一封裝體，所述的 引線框架包含一個散熱片、一個引腳組；201117338 VI. Description of the Invention: [0001] Technical Field The present invention relates to a power semiconductor I and to a power semiconductor I-frame and a method of fabricating the same. The package structure is packaged for mixing and manufacturing, and the special A gold lead frame [Prior Art] [0002] The main work point of the lead frame is that the chip is provided as a conductive medium connection frequency circuit external circuit transmission body and The packaging material - from the outward emission of the wafer security ^ signal 'and the extremely critical part of the integrated circuit, the machine: the heat 'to dry 1 for the power semiconductor, due to high power consumption, lead "zhong The heat sink becomes the main means of heat dissipation. " As disclosed in Chinese Patent Publication No. CN1738012A, a method of adding a heat sink to a wafer, the method comprising inputting a wafer arranged in an array into a film loading machine, 'through the multi-nozzle on the film loading machine A heat sink array 'and placing the heat sink array on the array of crystals and then cutting the heat sink array apart, the method can perform wafer loading on an array of wafers, thereby greatly improving the top sheet defect rate, however The processing method is relatively versatile, and the problem of heat dissipation of the large-scale wafer is reduced by the materialless (four) speed. In the prior art, the lead frame generally adopts a copper alloy lead frame, which is divided into two types: a profiled copper alloy lead frame, which is formed by using a copper alloy of different thicknesses in the lead and the heat sink portion, and the other is The same profile copper alloy lead frame, which is made of copper alloy of the same thickness in the pin and heat sink parts. Among them, for the profile copper alloy lead frame, due to manufacturing methods and cost constraints, it is not easy 098137925 Form No. A0101 Page 4 / Total 38 Page 201117338 [0003] Obtaining a very thick profile copper alloy heat sink 'with the same profile Copper alloy lead frames, due to the thin heat sink, have poor heat dissipation properties and increase the consumption of molding materials. In addition, whether it is a profiled copper alloy lead frame or a same profile copper alloy lead frame, it is expensive and has a high manufacturing cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a solder alloy lead frame and a manufacturing method thereof for use in a power semiconductor device. The mixed alloy lead frame has a high heat capacity ratio, and the manufacturing process is flexible and simple, and the process material can be saved. , reduce production costs. Ο In order to achieve the above object, the technical solution of the present invention is: a hybrid alloy lead frame array of a power semiconductor device, which is characterized by: a plurality of heat sinks, a pin array; A material is prepared, the upper part is provided with a positioning piece positioning hole, and the lower central part is provided with a heat sink welding zone; the pin array is made of a second material different from the first material; Between the two heat sinks, the upper and lower ends of the bow|foot array respectively lead to a plurality of pin terminal sets. o The hybrid alloy lead frame of the above-described power semiconductor device, wherein each of the heat sinks further comprises a wafer carrier. The hybrid alloy lead frame of the above-mentioned power semiconductor device, wherein each of the pin terminal groups includes three leg terminals, and the middle (5) pin terminals of each pin terminal group are respectively provided with a heat sink soldering region Corresponding bow and foot weld zone. 098137925 The above-mentioned hybrid semiconductor (10) frame of power semi-conducting, wherein a wafer carrier 2 extends from each of the lead pads. The above-mentioned type of power semiconductor device is a hybrid phantom frame, wherein the first material described in Form No. A0101, page 5 of 38, and 0983408055-0, 201117338 is a sinter alloy. A mixed alloy lead frame of the above power semiconductor device, wherein the heat sink has a horse's degree of 2 η. A mixed alloy lead frame of the above power semiconductor device, wherein the second material is a copper alloy. A manufacturing method for applying a mixed alloy lead frame package power semiconductor device, comprising the following steps: Step 1. manufacturing a lead frame group soldering plate, wherein the upper and lower portions of the lead frame group soldering plate are correspondingly provided with a plurality of sets of grooves, each A plurality of fin positioning posts are disposed in the recesses, and a plurality of pin positioning posts are disposed at a portion of the lead pivoting plate; _Step 2, a heat sink is formed, and a heat sink positioning hole is disposed at an upper portion of the heat sink a heat sink soldering area is disposed at a lower central portion of the heat sink; Step 3: fabricating a pin array' leads to a plurality of sets of three sets of pin terminal groups at the upper and lower ends of the pin array, wherein, in the pin terminal group The pin terminals of the intermediate pin terminals are respectively disposed corresponding to the dispersive chip solder joints, and a plurality of pin positioning holes are disposed between the two pin terminal groups; Step 4: by bending the wire frame and the group welding plate The heat sink positioning post and the heat sink positioning hole are positioned in the groove of the lead frame group soldering plate; Step 5, through the lead frame group soldering plate pin positioning column and the pin positioning hole, Position the area between the upper and lower heat sinks on the lead frame assembly board; Step 6. Connect the heat sink to the leads; Step 7 'Remove the heat sink and pins from the lead frame assembly. Clean the heat sink and pins. The above manufacturing method, wherein the step 2 further comprises: 098137925 Form No. A0101 Page 6 of 38 〇 2011 201117338 Step 2. 1. Set the wafer stage on the heat sink. In the above manufacturing method, the step 3 further includes: Step 3. 1. Extending the wafer carrier on the soldering area of the pin; Step 3.2: Fixing the wafer on the wafer carrier; Step 3. 3. Passing the lead The chip is connected to the pin terminals of the pins. The above manufacturing method, wherein the step 2.1 further comprises fixing the wafer to the wafer stage. In the above manufacturing method, the step 3 further includes: Step 3. 1. Extending the jumper on the pin terminal. Ο The above method for fabricating a mixed alloy lead frame for a power semiconductor device, wherein the step 6 further comprises: Step 6.1: connecting the wafer to the pin terminal through a jumper. In the above manufacturing method, the method of fixing the wafer on the wafer stage is solder fixing. A package of a power semiconductor device, comprising: a power semiconductor wafer, a lead frame and a package, the lead frame comprising a heat sink and a pin set;
G 所述的散熱片由第一種材料製成，所述的引腳組由與第 一種材料不同的第二種材料製成。 上述功率半導體裝置的封裝，其中，所述的第一種材料 為鋁合金，所述的第二種材料為銅合金。 上述功率半導體裝置的封裝，其中，所述的散熱片上還 包括一個晶片載片台，所述的晶片載片台由第一種材料 製成。 上述功率半導體裝置的封裝，其中，所述的散熱片上還 包括一個晶片載片台，所述的晶片載片台由第二種材料 098137925 表單編號A0101 第7頁/共38頁 0983408055-0 201117338 製成。 上述功率半導體裝置的封裝，其中，所述的散熱片設有 散熱片焊接區，所述的引腳端子組設有與散熱片焊接區 對應的引腳焊接區。 上述功率半導體裝置的封裝，其中，所述的封裝體一部 分至少延伸到散熱片的底面。 上述功率半導體裝置的封裝，其中，所述功率半導體晶 片包含頂面電極和底面電極，所述底面電極與至少一個 引腳端子連接，所述頂面電極與其他引腳端子連接。 本發明用於功率半導體裝置的混合合金引線框架及製作 方法由於採用上述技術方案，使之與現有技術相比，具 有以下優點和積極效果： 1、 本發明由於設有高熱容比的鋁合金散熱片，散熱性能 好。 2、 本發明由於鋁合金散熱片的製作工藝簡單，通過使用 厚的鋁合金散熱片以節省塑封料，從而降低引線框架封 裝成本。 3、 本發明由於散熱片採用鋁合金，引腳採用銅合金，二 者分開製作然後組裝構成混合合金引線框架，工藝製造 靈活，製造成本低。 【實施方式】 [0004] 098137925 實施例一，請參見附第ΙΑ、1B圖所示，分別為一種功率 半導體裝置的混合合金引線框架陣列分離元件組裝前的 正視圖及側視圖，包括：多個散熱片1、多個引腳2形成 的陣列；散熱片1的上部設有散熱片定位孔13、散熱片1 的下部中央部位設有散熱片焊接區12，每個散熱片1上還 表單編號A0101 第8頁/共38頁 098: 201117338 Ο 包括一個晶片載片台4，散熱片1的材料為鋁合金，由於 鋁合金材料具有高熱容比，散熱片的散熱性能佳，本實 施例中，散熱片1優選厚度為2mm ;引腳2陣列設置在上下 兩個散熱片1之間，引腳2陣列上下兩端分別相互錯位引 出多組三個一組的引腳端子組21，由連結帶（TIE BAR)23連結各引腳端子和整個引腳陣列。其中，引腳2陣 列上下兩端的每一組三個引腳端子21的中間引腳端子上 分別設有與散熱片焊接區12對應的引腳焊接區211，引腳 2陣列上下兩端的引腳焊接區211可分別與上下兩個散熱 片1的散熱片焊接區12連接，引腳端子組21之間設有多個 引腳定位孔22。引腳2的材料為銅合金。 上述用於功率半導體裝置的混合合金引線框架的製作方 法，包括以下步驟：The heat sink described in G is made of a first material made of a second material different from the first material. The package of the above power semiconductor device, wherein the first material is an aluminum alloy and the second material is a copper alloy. The package of the above power semiconductor device, wherein the heat sink further comprises a wafer carrier, the wafer carrier being made of the first material. The package of the above power semiconductor device, wherein the heat sink further comprises a wafer carrier, the wafer carrier is made of a second material 098137925, form number A0101, page 7 / 38 pages 0983408055-0 201117338 to make. The package of the above power semiconductor device, wherein the heat sink is provided with a heat sink soldering region, and the pin terminal group is provided with a pin soldering region corresponding to the heat sink soldering region. The package of the above power semiconductor device, wherein a portion of the package extends at least to a bottom surface of the heat sink. The package of the above power semiconductor device, wherein the power semiconductor wafer comprises a top surface electrode and a bottom surface electrode, the bottom surface electrode being connected to at least one pin terminal, and the top surface electrode being connected to other pin terminals. The mixed alloy lead frame and the manufacturing method for the power semiconductor device of the present invention have the following advantages and positive effects compared with the prior art by adopting the above technical solutions: 1. The present invention is provided with heat dissipation of an aluminum alloy having a high heat capacity ratio. The film has good heat dissipation performance. 2. The invention has a simple manufacturing process of the aluminum alloy heat sink, and reduces the cost of the lead frame packaging by using a thick aluminum alloy heat sink to save the molding material. 3. The invention adopts aluminum alloy for the heat sink and copper alloy for the lead, and the two are separately fabricated and assembled to form a mixed alloy lead frame, which is flexible in manufacturing process and low in manufacturing cost. [Embodiment] [0004] 098137925 Embodiment 1, please refer to Appendix ΙΑ, 1B, respectively, a front view and a side view of a hybrid alloy lead frame array separation element of a power semiconductor device, including: a plurality of The heat sink 1 and the plurality of pins 2 are formed in an array; the upper portion of the heat sink 1 is provided with a heat sink positioning hole 13, and the lower central portion of the heat sink 1 is provided with a heat sink soldering region 12, and each heat sink 1 is also provided with a form number. A0101 Page 8 of 38 098: 201117338 包括 Included is a wafer carrier 4, the material of the heat sink 1 is aluminum alloy, because the aluminum alloy material has a high heat capacity ratio, the heat dissipation performance of the heat sink is good, in this embodiment, The heat sink 1 preferably has a thickness of 2 mm; the array of pins 2 is disposed between the upper and lower heat sinks 1 , and the upper and lower ends of the array of pins 2 are respectively offset from each other to lead out a plurality of sets of pin terminal groups 21 of three groups, (TIE BAR) 23 links each pin terminal to the entire pin array. Wherein, the middle pin terminals of each of the three pin terminals 21 of each of the upper and lower ends of the pin 2 array are respectively provided with a pin pad 211 corresponding to the heat sink pad 12, and pins of the upper and lower ends of the pin 2 array The soldering regions 211 are respectively connected to the heat sink lands 12 of the upper and lower heat sinks 1 , and a plurality of pin positioning holes 22 are disposed between the pin terminal groups 21 . The material of the pin 2 is a copper alloy. The above method for fabricating a mixed alloy lead frame for a power semiconductor device includes the following steps:
G 步驟1、請參見附第2A及2B圖分別為引線框架組焊板3的 正視圖及侧視圖，製作引線框架組焊板3，該引線框架組 焊板3的上部和下部對應設置多組凹槽31，每個凹槽31内 設置若干散熱片定位柱311，在引線框架組焊板3的中部 設置多個引腳定位柱32; 步驟2、請參見附第ΙΑ、1B圖所示，製作散熱片1，在散 熱片1的上部設置一個定位孔13，在散熱片1的下部中央 部位設置散熱片焊接區12，在散熱片1上設置晶片載片台 4 ;每個散熱片1可單獨分開，也可根據引腳2陣列的節距 選擇用連結帶將多個散熱片連結在一起（未顯示）。 步驟3、請參見附第ΙΑ、1B圖所示，製作引腳2陣列，在 引腳陣列上下兩端分別引出多個各有三個引腳端子的引 098137925 腳端子組21，其中，每個引腳端子組21的中間引腳端子 表單編號A0101 第9頁/共38頁 0983408055-0 201117338 上分別設置與散熱片焊接區12對應的引腳焊接區211，兩 個引腳2之間設置多個引腳定位孔2 2 ; 步驟4、請參見附第3A及3B圖所示，將散熱片w定位孔 13穿過引線框架組焊板3的散熱片定位柱311，從而使散 熱片1疋位在引線框架組焊板3的凹槽内； 步驟5、請參見附第4A及4B圖所示，將引腳定位孔22穿過 引線框架組焊板3的引腳定位柱32，從而使引腳2陣列定 位在引線框架組焊板3上的上下散熱片1之間的部位，且 散熱片焊接區12和引腳焊接區211對應匹配； 步驟6、焊錫膏點塗在散熱片烊接區12為引腳焊接區211 上’將散熱片1和引腳2陣列連接，焊錫膏為船錫、錫銀 銅或錫鉍，焊接過程是在氮氣或氮氫混合氣體中進行。 優選地，焊接的溫度為280〜520攝氏度，焊接的時間為 5〜6 0秒； 最後從引線框架組焊板3上卸下連接在=一起的散熱片1和 引腳2並進行清洗，形成如附第5A及5B圖所示的混合合金 引線框架陣列。 可以應用標準的半導體晶片封裝程式，再經過晶片黏貼 ，金屬聯接和塑膠封模等步驟後，對整個封裝陣列進行 切割分離而形成如第5C、5D圖所示的獨立封裝的半導體 裝置。每一個獨立封裝的半導體裝置包含一功率半導體 晶片6 (如MOSFET )和一引線框架’該功率半導體晶片包 含頂面電極和底面電極，該引線框架包含由一種散熱性 能好的低成本材料（如鋁合金）製成的一散熱片和由一 種導電性能好的材料（如銅合金）製成的多個引腳。該 散熱片進一步包含一晶片載片台以承載該半導體晶片， 098137925 表單編號A0101 第10頁/共38頁 0983408055- 201117338 引腳連接區.連接所述多㈣腳當中的至 腳，該引腳連接區 固Μ 至少-個引腳上的 散熱片焊接區以便與所述 面電極與所、成5引腳知接區用淳踢對接使晶片的底 電極、i料Γ彡-個引腳端子連接。所述晶片的頂面 U金屬引線與其他引腳端子連接.第㈣ =的附圖標記U塑膠封裝體，該封裝體一部分至2 伸到散熱片的底^ u 夕延 露以更好散執。 底面可部分裸露或全部裸 Ο [0005]G Step 1. Please refer to the front view and side view of the lead frame group welding plate 3 in the drawings 2A and 2B, respectively, to fabricate the lead frame group welding plate 3, and the upper and lower portions of the lead frame group welding plate 3 are correspondingly arranged in groups a groove 31, a plurality of fin positioning posts 311 are disposed in each of the grooves 31, and a plurality of pin positioning posts 32 are disposed in the middle of the lead frame group soldering plate 3; Step 2, as shown in the attached figure, FIG. A heat sink 1 is formed, a positioning hole 13 is disposed in an upper portion of the heat sink 1, a heat sink soldering region 12 is disposed at a lower central portion of the heat sink 1, and a wafer carrier 4 is disposed on the heat sink 1. Each heat sink 1 can be Separately, it is also possible to connect a plurality of heat sinks together (not shown) by means of a link according to the pitch of the pin 2 array. Step 3, please refer to Appendix ΙΑ, 1B, to make a pin 2 array, and lead a plurality of 098137925-pin terminal groups 21 each having three pin terminals at the upper and lower ends of the pin array, wherein each lead The pin terminal block form number A0101 on page 9 of the pin terminal group 21 is set to the pin pad area 211 corresponding to the heat sink pad 12, and multiple pins are provided between the two pins 2 Pin positioning hole 2 2 ; Step 4, as shown in the attached drawings 3A and 3B, the heat sink w positioning hole 13 is passed through the heat sink positioning post 311 of the lead frame group soldering plate 3, so that the heat sink 1 is clamped In the recess of the lead frame group soldering plate 3; Step 5, as shown in the attached drawings 4A and 4B, the pin positioning hole 22 is passed through the pin positioning post 32 of the lead frame group soldering plate 3, thereby The array of the legs 2 is positioned between the upper and lower fins 1 on the lead frame group soldering plate 3, and the heat sink soldering region 12 and the pin soldering region 211 are matched; Step 6. The solder paste is applied to the heat sink bonding region. 12 is the pin soldering area 211 on the 'heat sink 1 and pin 2 array connection, solder paste for ship tin Copper, tin-bismuth or tin-silver, the welding process is performed in a nitrogen or nitrogen-hydrogen mixed gas. Preferably, the soldering temperature is 280 to 520 degrees Celsius, and the soldering time is 5 to 60 seconds; finally, the heat sink 1 and the pin 2 connected together = are removed from the lead frame group soldering plate 3 and cleaned to form A hybrid alloy lead frame array as shown in Figures 5A and 5B is attached. A standard semiconductor chip package program can be applied, and after the steps of wafer bonding, metal bonding, and plastic sealing, the entire package array is diced and separated to form a separately packaged semiconductor device as shown in FIGS. 5C and 5D. Each of the individually packaged semiconductor devices includes a power semiconductor wafer 6 (such as a MOSFET) and a lead frame. The power semiconductor wafer includes a top surface electrode and a bottom surface electrode. The lead frame includes a low cost material (such as aluminum) having good heat dissipation properties. A heat sink made of alloy and a plurality of pins made of a conductive material such as a copper alloy. The heat sink further comprises a wafer carrier to carry the semiconductor wafer, 098137925 Form No. A0101, page 10 / 38 pages 0983408055 - 201117338 pin connection area. Connect the foot to the foot (four), the pin is connected a heat sink soldering area on at least one of the pins to be connected to the surface electrode and the 5-pin contact area to connect the bottom electrode of the wafer to the pin terminal of the wafer . The top surface U metal lead of the wafer is connected to other pin terminals. The fourth (=) = reference U plastic package, the part of the package extends to the bottom of the heat sink to facilitate better dissipation . The bottom surface can be partially exposed or all bare. [0005]
’、、、由於該半導體裝置封裝的引線框架可採 同材料’分別製作散熱片和引腳，然後將二者聯接 =焊接）在1，—方面其散祕缺，另—方= 於散J獨立製作，並隸舍金卫藝製作簡單，可以得 到厚度大的散熱片，從而節省後期機過程中塑封料， 大大降低功率㈣體^雜的製作成本。 實施例°月參見附第6八及把圖所示，分別為-種功率 半導體裝置的混合合金引線框架序列分離元件組裝前的 正視圖及側視圖，包括：多個散熱片「和引腳2，陣列 ’散熱片1，的上部設有散熱片定位孔13 -、散熱片1 一 的下部中央部位設有散熱片焊接區12一，散熱片厂的材 料為鋁合金，散熱片i /的厚度為2111111;引腳2 >陣列設置 在上下兩個散熱片r之間，引腳厂陣列上下兩端分別 相互錯位引出多組三個一組的引腳端子組21，由連結帶 (TIE BAR)23連結各引腳端子和整個引腳陣列❶其中 ，所述的引腳2陣列上下兩端的每一組三個引腳端子21 的中間引腳端子上分別設有與散熱片焊接區12 -對應 的引腳焊接區21广’引腳2 -上下兩端的引腳焊接區211 098137925 表單編號A0101 第Π頁/共38頁 0983408055-0 201117338 /可分別與上下兩個散熱片1 >的散熱片焊接區12>連接 ，每個引腳焊接區211 〃上延伸出一個晶片載片台4 一， 引腳2 >之間設有多個引腳定位孔22 /。引腳2 /的材料 為銅合金。 上述用於功率半導體裝置的混合合金引線框架的製作方 法及裝置封裝方法，包括以下步驟： 步驟1、請參見附第7A及7B圖所示，製作引線框架組焊板 3/，該引線框架組焊板3 /的上部和下部對應設置多組 凹槽31 /，每個凹槽31 /内設置若干散熱片定位柱311 一 ，在引線框架組焊板3 /的中部設置多個引腳定位柱32 / 步驟2、請參見附第6A及6B圖所示，製作散熱片1 /，在 散熱片1 >的上部設置一個散熱片定位孔13 >，在散熱片 1/的下部中央部位設置散熱片焊接區12> ; 步驟3、請參見附第7A、7B、8A、8B、9A及9B圖所示， 製作引腳，在引腳上下兩端分別引出多個各有三 個引腳端子21 /的引腳端子組，其中，每個引腳端子組 21 /的中間引腳端子上分別設置與散熱片焊接區12 <對 應的引腳焊接區211 >，兩個引腳2 /之間設置多個引腳 定位孔22 步驟3還包括： 步驟3. 1、引腳焊接區211 /上延伸出晶片載片台4 一 ； 步驟3. 2、在氮氣或氮氫混合氣體中，用鉛錫、錫銀銅或 錫叙點塗在晶片載片台4 上’將晶片6 焊接固定在晶 片載片台4 /上，優選地，焊接的溫度為280~520攝氏度 ，焊接的時間為5〜6 0秒； 步驟3. 3、通過引線5 /將晶片6 >與引腳2 >的引腳端子 098137925 表單編號Α0101 第12頁/共38頁 0983408055-0 201117338 21 —連接。 步驟4、請參見附第10A及1 0B圖所示，散熱片定位孔13 /穿過引線框架組焊板3 /上的散熱月定位柱311 /，從 而將散熱片1 /定位在引線框架組焊板3 >的凹槽31 >内 :每個散熱片Γ可單獨分開，也可根據引腳陣列2’的 節距選擇用連結帶將多個散熱片連結在一起（未顯示） f 步驟5、請參見附第11A及11B圖所示，引腳定位孔22 ' 穿過引線框組焊板3 /上的引腳定位柱32 >，從而將引 腳2 /定位在引線框架組焊板3 /上的上下散熱片1 /之間 的部位且散熱片焊接區12’和引腳焊接區21Γ對應匹配 步驟6、焊錫膏點塗在散熱片焊接區12 >和引腳焊接區 211 >上，將散熱片1 /和引腳2 /連接使晶片6 >的底面 電極與引腳端子組21 >的中間引腳端子連接，優選地， 晶片載片台的下表面與散熱片1>的上表面能有緊密 接觸或由焊錫連接以增強散熱效果； 最後從引線框架組焊板3 /上卸下連接在一起的散熱片1 /和引腳2 /並進行清洗，得到如第12Α及12Β圖所示的包 含晶片連接的混合合金引線框架陣列。 再經過塑膠封模後，對整個封裝陣列進行切割分離而形 成如第12C、12D圖所示的獨立封裝的半導體裝置。每一 個獨立封裝的半導體裝置包含一功率半導體晶片（如 M0SFET)和一引線框架，該功率半導體晶片包含頂面電 極和底面電極，該引線框架包含由一種散熱性能好的底 成本材料（如鋁合金）製成的一散熱片和由一種導電性 098137925 表單編號A0101 第13頁/共38頁 0983408055-0 201117338 能好的材料（如銅合金） 一步包八 成的多個引腳。該散熱片進 一個 ?丨腳連接區以連接所述多個引腳當中的至少 與所述腳ί ^引腳連接區可是—個散熱片焊接區以便 j ^ 個引腳上的一弓I腳焊接區用焊錯對接。該 引線框架進— a 今曰 步匕含一曰曰片栽片台以承載該半導體晶片 栽片台與所述至少一個引腳相連且由引腳相同 材料製成，& 且其下表面與所述散熱片的上表面有緊密接 焊錄連接以增強散熱效果。所述晶片的頂面電極 通金屬弓I線與其他引腳端子連接，第12C圖、第12D圖 中、、圖払S己7為塑膠封裝體，該封裝體一部分至少延 Ο 伸到散熱ha+ 、〇的底面，散熱片的底面可部分裸露或全部裸 露以更好散熱。 由；S’半導體裝置封裝的引線框架採用不同材料分別 製作散熱片和引腳，然後將二者焊接在-起，-方面其 散熱性能权 ^ ’另一方面由於散熱片獨立製作，並且鋁合 金工藝製作簡單’可以得到厚度大的散熱片，從而節省 後期封襄過財塑㈣，大大降低功率半導體W封裝 的製作成本’在製作引腳2 一時，同時完成了晶片的 ◎ 安裝及晶片6 -與引腳2 >的連接，工藝製作過程方便。 [0006] 實施例三，請參見附第13A及13B圖，一種功率半導體裝 置的混合合金引線框架陣列分離元件組裝前的正視圖及 侧視圖，包括：多個散熱片1…、引腳2…陣列；散 熱片1 的上部設有散熱片定位孔13 散熱片1， 的下部中央部位設有散熱片焊接區12, >，每個散熱 片上還包括一個晶片載片台4 散熱片的材料 098137925 表單編號A0101 第14夷/共38頁 0983408055-0 201117338 採用鋁合金，優選地，散熱片1 β >的厚度為2mm ;引腳2 陣列設置在上下兩個散熱片1 之間，引腳陣列2 上下兩端分別相互錯位引出多組三個一組的引腳端 子組21 ——，由連結帶（TIE BAR)23 '—連結各引腳端 子和整個引腳陣列.其中，引腳2 > /陣列上下兩端的每 一組三個引腳端子21 的中間引腳端子上分別設有與 散熱片焊接區12 對應的引腳焊接區211 引腳2 陣列上下兩端的引腳焊接區211 / /可分別與上下兩 個散熱片1 的散熱片焊接區12 連接，引腳端子組 〇 21 之間設有多個引腳定位孔22 。引腳端子21 > /延伸出一段跳線212 引腳陣列2 的材料為銅 合金。 上述用於功率半導體裝置的混合合金引線框架的製作方 法及裝置封裝方法，包括以下步驟： 步驟1、如第14Α及14Β圖所示，製作引線框架組焊板3 一 一，引線框架組焊板3 的上部和下部銬應設置多組凹 槽31 每個凹槽31 内設置若干散熱片定位柱311 ^ 在引線框架組焊板3> —的中部設置多個引腳定位 柱32…； 步驟2、如第13Α及13Β圖所示，製作散熱片在散 熱片1 / /的上部設置一個散熱片定位孔13 / /，在散熱 片1 的下部中央部位設置散熱片焊接區12 每個 散熱片Γ可單獨分開，也可根據引腳2 陣列的節距 選擇用連結帶將多個散熱片連結在一起（未顯示）；步 驟2還包括： 步驟2. 1、在散熱片1 上設置晶片載片台4 用焊 098137925 表單編號Α0101 第15頁/共38頁 0983408055-0 201117338 錫膏將晶片,焊接在晶片載片台4 -。 步驟3、如第i3A及13B圖所示，製作引腳2…陣列，在 引腳2 -—陣列上下兩端分別引出多個各有三個引腳端子 21的引腳端子組，其中，每個引腳端子組21 ' 的中 間引腳端子上分別設置與散熱片焊接區12 //對應的引 腳焊接區211 ^ 一，兩個引腳組21 / >之間設置多個W腳 定位孔22 -';步驟3還包括： 步驟3. 1、在引腳2 陣列的引腳端子組21 上的另 兩個引腳延伸跳線212 ; 0 步驟4、如第15A及15B圖所示，散熱片定位孔13 / ’聲 ,::1. . ： 過引線框架組焊板3 -—的散熱片定位柱311 / /，從而 將散熱片>定位在引線框.架組焊板3的凹槽31 一内； 步驟5 '如第16A及16B圖所示，引腳定位孔22 / '穿過 引線框架組焊板—的引腳定位柱32，，，從而將弓丨腳 2 疋位在引線框架組焊板3>.'上的上下散熱片1 之間的部位； q 步驟6、在氣氣或氣氫混合氣體中，將錯錫、錫銀銅或錫 鉍點塗在散熱片焊接區12 ''和引腳焊接區211 上， 將散熱片1 —，和引腳陣列2連接使晶片6”的底面電 極與引腳端子組21 的中間引腳端子連接，優選地， 知接的溫度為280〜520攝氏度’焊接的時間為5~6〇秒； 步驟6還包括： 步驟6· 1、通過跳線212將晶片6 > —的上表面電極與 其他不與散熱片連接的引腳端子21> 連接。 最後從引線框架組焊板3 上卸下連接在一起的散熱片 098137925 表單編號Α0101 第16頁/共38頁 0983408055-0 201117338 1和引聊2…並進行清洗’得到如第17A及Ι7β圖所 不包含晶片連接的混合合金引線框架。再經過塑膠封楔 後，對整個封裝陣列進行切割分離而形成如第1；^、 圖所示的獨立封裝的半導體裝置。每-個獨立封裝的: 導體裝置包含-功率半導體晶片（如M〇SFET)和—弓I線 框架，該功率半導體晶片包含頂面電極和底面電極，| 引線框架包含由一種散熱性能好的底成本材料（如紹二 金）製成的一散熱片和由一種導電性能好的材料（如: 合金）製成的多個引腳。該散熱片進一步包含—a 、 曰曰片裁^ 片台以承載該半導體晶片，和一引腳連接區以連接所述 多個引腳當中的至少-個引腳，該引腳連接區可以是」 個散熱片焊接區以便與所述至少一個引腳上的一引腳垾 接區用焊錫對接，所述引線枢架進一步包:含由所述多^',,, because the lead frame of the semiconductor device package can be made of the same material 'to make the heat sink and the pin separately, and then the two are connected = soldered" in the first aspect, the secret is lacking, and the other side = the loose J Independently produced, and the production of Jin Weiyi is simple, you can get a thick heat sink, which saves the molding material in the process of the late machine, greatly reducing the production cost of power (4). EXAMPLES FIG. 6 is a front view and a side view of a mixed alloy lead frame serial separation element of a power semiconductor device, respectively, including a plurality of heat sinks "" and "pin 2" The upper part of the array 'heat sink 1 is provided with a fin positioning hole 13-, and the lower central part of the heat sink 1 is provided with a heat sink welding zone 12, the material of the heat sink factory is aluminum alloy, and the thickness of the heat sink i / 2111111; pin 2 > array is set between the upper and lower heat sinks r, the upper and lower ends of the pin factory array are mutually offset to lead out multiple sets of three sets of pin terminal sets 21, by the link belt (TIE BAR 23) connecting each pin terminal and the entire pin array ❶, wherein the pin 2 array is arranged at the upper and lower ends of each of the three pin terminals 21 at the intermediate pin terminals respectively provided with the heat sink soldering region 12 - Corresponding pin soldering area 21 wide 'pin 2 - upper and lower pin soldering area 211 098137925 Form No. A0101 Page / Total 38 pages 0983408055-0 201117338 / Can be separately cooled with the upper and lower heat sink 1 > Chip pad 12> connection, each pin A wafer stage 4 is extended on the connection area 211, and a plurality of pin positioning holes 22 are provided between the pins 2 > The material of the pin 2 / is a copper alloy. The above is used for the power semiconductor device. The manufacturing method of the mixed alloy lead frame and the device packaging method include the following steps: Step 1. Referring to the drawings 7A and 7B, the lead frame group welding plate 3/, the upper part of the lead frame group welding plate 3/, and The lower part is correspondingly provided with a plurality of sets of grooves 31 /, and each of the grooves 31 / is provided with a plurality of fin positioning posts 311, and a plurality of pin positioning posts 32 are arranged in the middle of the lead frame group welding plate 3 / Step 2 As shown in Figs. 6A and 6B, a heat sink 1 / is formed, a heat sink positioning hole 13 > is disposed on the upper portion of the heat sink 1 >, and a heat sink soldering portion 12 is disposed in a lower central portion of the heat sink 1 > Step 3. Please refer to the drawings 7A, 7B, 8A, 8B, 9A and 9B to make the pins. A plurality of pin terminal groups each having three pin terminals 21 / are respectively drawn at the upper and lower ends of the pin. Wherein, each pin terminal group 21 / intermediate pin terminal is respectively disposed and dissipated The soldering area 12 < corresponding pin soldering area 211 >, two pins 2 / between the plurality of pin positioning holes 22 step 3 further includes: Step 3. 1, the pin soldering area 211 / extended Wafer stage 4; Step 3. 2. In a nitrogen or nitrogen-hydrogen mixed gas, coated with lead tin, tin silver copper or tin on the wafer stage 4 'welding the wafer 6 to the wafer carrier Table 4 / upper, preferably, the soldering temperature is 280 ~ 520 degrees Celsius, the soldering time is 5 ~ 60 seconds; Step 3. 3, through the lead 5 / put the wafer 6 > with the pin 2 > Terminal 098137925 Form No. 1010101 Page 12 of 38 0983408055-0 201117338 21 — Connection. Step 4, as shown in Figures 10A and 10B, the heat sink positioning hole 13 / through the heat dissipation month positioning column 311 / on the lead frame group soldering plate 3 /, thereby positioning the heat sink 1 / in the lead frame group The groove 31 > inside the soldering plate 3 >: each heat sink Γ can be separately separated, or a plurality of heat sinks can be connected together according to the pitch of the pin array 2 ′ (not shown) f Step 5, as shown in Figures 11A and 11B, the pin locating holes 22' pass through the lead frame of the lead frame group 3/on the pin positioning post 32 >, thereby positioning the pin 2 / in the lead frame group Solder plate 3 / upper and lower heat sink 1 / between the portion and the heat sink soldering zone 12' and the pin soldering area 21 Γ corresponding matching step 6, solder paste spot on the heat sink soldering area 12 > and pin soldering area 211 >, the heat sink 1 / and the pin 2 / connection are connected to the bottom electrode of the wafer 6 > and the intermediate pin terminal of the pin terminal group 21 > preferably, the lower surface of the wafer stage The upper surface of the heat sink 1> can be in close contact or connected by solder to enhance the heat dissipation effect; finally from the lead frame group welding plate 3 / Removing the heat sink are connected together 1/2 and pin / and washed, to obtain mixed alloy lead frame such as shown in the first packet array and 12Β FIG 12Α wafer containing connection. After plastic encapsulation, the entire package array is diced and separated to form a separately packaged semiconductor device as shown in Figures 12C and 12D. Each of the individually packaged semiconductor devices includes a power semiconductor wafer (such as a MOSFET) and a lead frame including a top surface electrode and a bottom surface electrode, the lead frame including a bottom cost material having good heat dissipation properties (such as an aluminum alloy) ) Made of a heat sink and a conductive material (such as copper alloy) made of a conductive material 098137925 Form No. A0101 Page 13 / 38 pages 0983408055-0 201117338. The heat sink is connected to a pin connection region to connect at least one of the plurality of pins to the pin ί ^ pin connection region, which may be a heat sink pad for a pin on the pin The weld zone is docked by welding. The lead frame includes a chip carrier for carrying the semiconductor wafer stage connected to the at least one pin and made of the same material of the pin, & The upper surface of the heat sink has a close-contact solder joint to enhance the heat dissipation effect. The top surface electrode of the wafer is connected to other pin terminals through the metal bow I line, and the 12C, 12D, and 7D are plastic packages, and a part of the package extends at least to the heat dissipation ha+ The bottom surface of the crucible, the bottom surface of the heat sink may be partially exposed or exposed to better heat dissipation. The lead frame of the S' semiconductor device package is made of different materials to make the heat sink and the lead, and then the two are soldered together, and the heat dissipation performance is right. The process is simple to make 'a thick heat sink can be obtained, which saves the later sealing of the plastic (4), greatly reducing the manufacturing cost of the power semiconductor W package'. At the time of making the pin 2, the wafer is mounted at the same time and the wafer 6 is completed. The connection to pin 2 > makes the process easy to manufacture. [0006] Embodiment 3, referring to FIGS. 13A and 13B, a front view and a side view of a hybrid alloy lead frame array separating element of a power semiconductor device, including a plurality of heat sinks 1 ..., pins 2... The upper part of the heat sink 1 is provided with a fin positioning hole 13 and the heat sink 1 is provided with a heat sink lands 12, >, each heat sink also includes a wafer stage 4 heat sink material 098137925 Form No. A0101 No. 14/Yue 38 pages 0983408055-0 201117338 Aluminum alloy, preferably, heat sink 1 β > thickness is 2mm; Pin 2 array is placed between the upper and lower heat sinks 1, pin array 2 The upper and lower ends are offset from each other to lead out multiple sets of three sets of pin terminal sets 21 - by TIE BAR 23 ' - to connect the pin terminals and the entire pin array. Among them, pin 2 > / The upper pin terminals of each of the three pin terminals 21 of the upper and lower ends of the array are respectively provided with pin soldering regions 211 corresponding to the heat sink soldering regions 12, and the pin soldering regions 211 of the upper and lower ends of the array 2 pin array / / can be separated from the top and bottom Radiating fins connected to a bonding pad 12, a plurality of holes 22 is provided between the positioning pins 21 square pin terminal groups. Pin terminal 21 > / extends a jumper 212 pin array 2 material is copper alloy. The method for manufacturing a mixed alloy lead frame for a power semiconductor device and the method for packaging the same include the following steps: Step 1. As shown in FIGS. 14 and 14, a lead frame group soldering plate 3 is formed, and a lead frame group is welded. The upper and lower jaws of 3 should be provided with a plurality of sets of grooves 31. Each of the grooves 31 is provided with a plurality of fin positioning posts 311 ^ In the middle of the lead frame group welding plate 3 > - a plurality of pin positioning posts 32 are arranged; Step 2 As shown in Figures 13 and 13, the heat sink is provided with a heat sink positioning hole 13 / / on the upper part of the heat sink 1 / /, and a heat sink soldering area 12 is disposed in the lower central portion of the heat sink 1 . Separately separate, or select a plurality of heat sinks together according to the pitch of the pin 2 array (not shown); step 2 further includes: Step 2. 1. Set the wafer slide on the heat sink 1. Table 4 with welding 098137925 Form No. Α 0101 Page 15 / Total 38 pages 0983408055-0 201117338 Solder paste will be soldered to the wafer stage 4 -. Step 3, as shown in the figures i3A and 13B, fabricating the pin 2... array, and respectively drawing a plurality of pin terminal groups each having three pin terminals 21 at the upper and lower ends of the pin 2 - array, wherein each A pin pad 211 ^ corresponding to the heat sink lands 12 / 2 is disposed on the middle pin terminal of the pin terminal group 21 ', and a plurality of W pin locating holes are disposed between the two pin groups 21 / > 22 - '; Step 3 also includes: Step 3. 1. Extend the jumper 212 on the other two pins on the pin terminal group 21 of the pin 2 array; 0 Step 4, as shown in Figures 15A and 15B, Heat sink positioning hole 13 / 'Acoustic,::1. . : Over the lead frame group soldering plate 3 - the heat sink positioning post 311 / /, thereby positioning the heat sink > in the lead frame. Inside the groove 31; Step 5', as shown in Figures 16A and 16B, the pin positioning hole 22 / 'passes the lead frame of the lead frame group - the pin positioning post 32, so that the bow 2 is clamped The portion between the upper and lower fins 1 on the lead frame group soldering plate 3>.'; Step 6. In the gas or gas-hydrogen mixed gas, the stray tin, tin-silver-copper or tin-bismuth is applied to the heat sink. On the die pad 12'' and the pin pad 211, the heat sink 1 is connected to the pin array 2 so that the bottom electrode of the wafer 6" is connected to the intermediate pin terminal of the pin terminal group 21, preferably, The connection temperature is 280~520 degrees Celsius' welding time is 5~6〇 seconds; Step 6 further includes: Step 6·1, connecting the upper surface electrode of the wafer 6 > to other heat sinks through the jumper 212 Pin Terminal 21> Connection. Finally, remove the heat sink 098137925 from the lead frame group soldering plate 3. Form No. 1010101 Page 16 of 38 0983408055-0 201117338 1 and Talk 2...and clean it' A mixed alloy lead frame which does not include wafer bonding as shown in the 17A and Ι7β drawings is obtained, and after the plastic sealing is performed, the entire package array is diced and separated to form a separately packaged semiconductor device as shown in the first embodiment. Each of the individually packaged: conductor devices comprises a power semiconductor wafer (such as M〇SFET) and a bow I-line frame, the power semiconductor wafer comprising a top electrode and a bottom electrode, | the lead frame comprising a bottom having a good heat dissipation performance a heat sink made of a cost material (such as Shao Erjin) and a plurality of pins made of a material having good electrical conductivity (such as an alloy). The heat sink further includes -a, a slab cut piece Carrying the semiconductor wafer, and a pin connection region for connecting at least one of the plurality of pins, the pin connection region may be a heat sink pad for the at least one pin a pin splicing area is docked with solder, and the lead pivot frame is further packaged:
引腳當中至少另一個引腳延伸出來的跳線連接該半導Z 晶片的上表面電極。第17C圖、第17D圖中的附圖標記厂 /為塑膠封裝體，該封裝體一部分至少延伸到散熱片的 底面’散熱片的#面可部分裸露或全部裸露以更好散熱 。 *’、、 由於該半導體裝置封裝的引線框架採用不同材料，分別 製作散熱片和5丨腳，然後將二者焊接在一起’一方面其 散熱性能好，另一方面由於散熱片獨立製作並且鋁合 金工藝製作簡單’可以得到厚度大的散熱片，從而節省 後期封裝過程巾減料’大大降低功率半導體晶片封敦 的製作成本，在引腳上延伸出跳線，將晶片，與引腳的 連接，省去引線的連接，工藝製作簡單。 本發明提供了-種混合合金⑽㈣及其用於功率半導 098137925 表單編號A0101 第17頁/共38頁 0983408055-0 201117338 體裝置封裝的製作方法，該方法將引線框架分成兩部分 ，政熱片部分及引腳部分，將這兩部分用不同材料分別 製作，然後用設計好的引線框架組焊板將這兩部分定位 焊接，從而完成整個引線框架的製作，得到散熱性能好 ，低成本的混合合金引線框架，此外該方法既可分佈實 現引線框架的製作及晶片與引線框架的連接，也可同時 完成引線框架的製作及晶片與引線框架的連接，從而提 高實際應用的靈活性。 當然’必須§忍識到’上述介紹是有随本發明優選實施例 的說明，只要不偏離隨烽所附申讀專利範圍第所顯示的 精神和範圍，本發明還存在著許多修改》 本發明決不是僅局限於上述說明或附圖所顯示的細節和 方法。本發明能夠擁有其他的實施例並可採用多種方 式予以實施。另外，大家還必須認識到，這裏所使用的 措辭和術語以及文摘只是為了實現介紹的目的決不是 僅僅局限於此。 正因為如此’本領域的技術人員將會理解， 哪’本發明所 於的觀點可隨時用來作為實施本發明的继α 嘮種目標而設 其他結構、方法和系統。所以，至關重 I的是，所附 申請專利範圍第將被視為包括了所右技1 ί所有這些等價 只要它們不偏離本發明的精神和範圍。 [0007] 【圖式簡單說明】 參考所附附圖 而 ’以更加充分的描述本發明 ，所附附圖僅用於說明和闌述，並不樽成貫施例 圍的限制。 然 對本發明範 098137925 第1Α圖為本發明一種用於功率半導體| 表單編號A0101 第W頁/共38育 、置的混合合金引 201117338 線框架及製作方法實施例一的混合合金引線框架陣列分 離元件組裝前的正視圖。 第1Β圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的混合合金引線框架陣列分 離元件組裝前的側視圖。 第2Α圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的引線框架組焊板的正視圖 〇 Ο 第2Β圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的引線框架組焊板的侧視圖 第3A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的安裝散熱片的正視圖。 第3B圖為本發明一種用於功率半導體裝置的混合合金引 線棰架及製作方法實施例一的安裝散熱片的侧視圖。 第4A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的安裝引腳的正視圖。 Ο 第4B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的安裝引腳的側視圖。 第5A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的混合合金引線框架陣列的 正視圖。 第5B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的混合合金引線框架陣列的 側視圖。 第5C圖為本發明一種用於功率半導體裝置的混合合金引 098137925 表單編號A0101 第19頁>共38頁 0983408055-0 201117338 線框架及製作方法實施例一的混合合金引線框架陣列塑 封切割後的正視圖。 第5D圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例一的混合合金引線框架陣列塑 封切割後的侧視圖。 第6A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的混合合金引線框架陣列分 離元件組裝前的正視圖。 第6B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的混合合金引線框架陣列分 離元件組裝前的側視圖。 第7A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的引線框架組焊板的正視圖 〇 第7B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的弓丨線框架組焊板的側視圖 〇 第8A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的引腳的正視圖。 第8B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的引腳的侧視圖。 第9A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的引線將引腳與晶片連接的 正視圖。 第9B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的引線將引腳與晶片連接的 098137925 表單編號A0101 第20頁/荬38頁 0983408055-0 201117338 側視圖。 第1 0Α圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的安裝散熱片的正視圖。 第1 0Β圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的安裝散熱片的侧視圖。 第11Α圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的安裝引腳的正視圖。 第11Β圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的安裝引腳的側視圖。 ❹ 第1 2Α圖本發明一種用於功率半導體裝置的混合合金引線 框架及製作方法實施例二的混合合金引線框架陣列的正 視圖。 第12Β圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的混合合金引線框架陣列的 侧視圖。 Ο 第12C圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的混合合金引線框架陣列塑 封切割後的正視圖。 第12D圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例二的混合合金引線框架陣列塑 封切割後的侧視圖。 第13Α圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的混合合金引線框架陣列分 離元件組裝前的的正視圖。 第13Β圖為本發明一種用於功率半導體裝置的混合合金引 098137925 線框架及製作方法實施例三的混合合金引線框架陣列分 表單編號Α0101 第21頁/共38頁 0983408055-0 201117338 離元件組裝前的的側視圖。 第14A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的引線框架組焊板3的正視圖 〇 第14B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的引線框架組焊板3的側視圖 〇 第15A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的安裝散熱片的正視圖。 第15B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的安裝散熱片的側視圖。 第16A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的安裝引腳的正視圖。 第16B圖分別為本發明一種用於功率半導體裝置的混合合 金引線框架及製作方法實施例三的安裝引腳的側視圖。 第17A圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的混合合金引線框架陣列的 正視圖。 第17B圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的混合合金引線框架陣列的 侧視圖。 第17C圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的混合合金引線框架陣列塑 封切割後的正視圖。 第1 7D圖為本發明一種用於功率半導體裝置的混合合金引 線框架及製作方法實施例三的混合合金引線框架陣列塑 098137925 表單編號A0101 第22頁/共38頁 0983408055-0 201117338 ❹ Ο 封切割後的側視圖。 【主要元件符號說明】 [0008] 1 ' 1 ' 1… :散熱片 2 ' 2 ^ ' ί 丨 ：腳 3 ' 3 " > ： 3… .引線框架組焊板 4 ' 4 " ' ^ 1… :晶片載片台 6:功率半導體晶片 6 一 ' 6 — > :晶 片 7、7 ' r 1… .塑膠封裝體 12、12， 、12 一 :散熱片焊接區 13、13， 、13 / / :散熱片定位孔 21 、 21， ' 21 ^ :引腳端子组 22 ' 22 " '22 一 .引腳定位孔 23、23 / '23 一 :連結帶 31 、 31 一 、31 一 / :凹槽 32、32 一 '32 一 •弓丨:腳定位柱 211 、 211 、211 :引腳焊接[ 212 …： 跳線 311 、 311 一、 311 :散熱片定位柱 098137925 表單編號Α0101 第23頁/共38頁 0983408055-0A jumper extending from at least one of the other pins of the pin connects the upper surface electrode of the semiconductor Z wafer. The reference numeral factory in Fig. 17C and Fig. 17D is a plastic package, and a part of the package extends at least to the bottom surface of the heat sink. The # face of the heat sink may be partially exposed or entirely exposed for better heat dissipation. *', Since the lead frame of the semiconductor device package uses different materials, respectively, the heat sink and the 5 feet are fabricated, and then the two are soldered together. On the one hand, the heat dissipation performance is good, and on the other hand, the heat sink is independently fabricated and aluminum The alloy process is simple to make 'a thick heat sink can be obtained, which saves the post-packaging process towel reduction' greatly reduces the manufacturing cost of the power semiconductor chip seal, extends the jumper on the pin, and connects the wafer to the pin. The wiring is omitted, and the process is simple to manufacture. The present invention provides a hybrid alloy (10) (4) and a method for fabricating a power device package for power semiconductor 098137925 Form No. A0101 Page 17 of 38 098340805-5-0 201117338, which divides the lead frame into two parts, the political sheet Part and pin parts, the two parts are made of different materials, and then the two parts are positioned and welded by the designed lead frame group welding plate, thereby completing the whole lead frame, and obtaining good heat dissipation performance and low cost mixing. The alloy lead frame can be distributed to realize the fabrication of the lead frame and the connection of the wafer and the lead frame, and simultaneously complete the fabrication of the lead frame and the connection of the wafer and the lead frame, thereby improving the flexibility of practical application. Of course, the present invention has been described with respect to the preferred embodiments of the present invention, and many modifications are possible in the present invention without departing from the spirit and scope of the invention as set forth in the appended claims. The details and methods shown in the above description or the drawings are in no way limited. The invention is capable of other embodiments and of various embodiments. In addition, you must also be aware that the wording and terminology used herein, as well as the abstracts, are by no means limited to the purpose of the description. As such, it will be understood by those skilled in the art that the present invention may be readily utilized as a structure, method, and system for carrying out the invention. Therefore, it is to be understood that the scope of the appended claims is to be construed as being limited to the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The invention is described more fully herein with reference to the accompanying drawings, However, the invention is directed to a hybrid alloy lead frame array separating element of the first embodiment of the present invention for power semiconductors | Form No. A0101, page W/total 38, mixed alloy lead 201117338 wire frame and manufacturing method Front view before assembly. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a side elevational view showing a mixed alloy lead frame array separating element of a first embodiment of a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. 2 is a front view of a lead frame assembly welding plate of a first embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. FIG. 2 is a mixed alloy lead for a power semiconductor device according to the present invention. Frame and Manufacturing Method Side View of Lead Frame Welding Plate of Embodiment 1 FIG. 3A is a front view of a mounting heat sink for a hybrid alloy lead frame for a power semiconductor device and a manufacturing method of the first embodiment of the present invention. Fig. 3B is a side view showing the mounting fin of the first embodiment of the hybrid alloy lead truss for a power semiconductor device and a manufacturing method thereof. Fig. 4A is a front elevational view showing a mounting pin of a first embodiment of a hybrid alloy lead frame and a manufacturing method for a power semiconductor device according to the present invention. 4B is a side view of a mounting pin of a first embodiment of a hybrid alloy lead frame and a manufacturing method for a power semiconductor device according to the present invention. Fig. 5A is a front elevational view showing a mixed alloy lead frame array of a first embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. Fig. 5B is a side view showing a mixed alloy lead frame array of a first embodiment of a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. 5C is a mixed alloy for power semiconductor device according to the present invention. 098137925 Form No. A0101 Page 19> Total 38 pages 0983408055-0 201117338 Wire frame and manufacturing method The mixed alloy lead frame array of the first embodiment is molded and sealed. Front view. Fig. 5D is a side view of the mixed alloy lead frame array of the first embodiment of the hybrid alloy lead frame for the power semiconductor device of the present invention. Fig. 6A is a front elevational view showing the mixed alloy lead frame array separating element of the second embodiment of the present invention, which is a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. Fig. 6B is a side elevational view showing the mixed alloy lead frame array separating element of the second embodiment of the hybrid alloy lead frame and the manufacturing method for the power semiconductor device of the present invention. 7A is a front view of a lead frame assembly welding plate of a second embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. FIG. 7B is a hybrid alloy lead frame for a power semiconductor device according to the present invention. 2 is a side view of a lead of a hybrid alloy lead frame for a power semiconductor device and a second embodiment of the manufacturing method of the present invention. Fig. 8B is a side view showing a pin of a second embodiment of a hybrid alloy lead frame and a manufacturing method for a power semiconductor device according to the present invention. Fig. 9A is a front elevational view showing a lead wire connecting a lead to a wafer in a second embodiment of a hybrid alloy lead frame for a power semiconductor device according to the present invention. FIG. 9B is a view showing a mixed alloy lead frame for a power semiconductor device according to the present invention and a method for fabricating the same. The lead wire connects the pin to the wafer. 098137925 Form No. A0101 Page 20/荬38 page 0983408055-0 201117338 Side view. Fig. 10 is a front elevational view showing a mounting fin of a second embodiment of a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. Fig. 10 is a side view showing a mounting heat sink of a second embodiment of a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. Figure 11 is a front elevational view showing a mounting pin of a second embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. Figure 11 is a side view showing a mounting pin of a second embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. BRIEF DESCRIPTION OF THE DRAWINGS A front view of a mixed alloy lead frame array of a second embodiment of a mixed alloy lead frame for a power semiconductor device and a method of fabricating the same. Fig. 12 is a side view showing a mixed alloy lead frame array of a second embodiment of a mixed alloy lead frame for a power semiconductor device and a manufacturing method of the present invention. Ο Figure 12C is a front elevational view of the mixed alloy lead frame array of the second embodiment of the hybrid alloy lead frame and the manufacturing method of the power semiconductor device according to the present invention. Fig. 12D is a side view showing the mixed alloy lead frame array of the second embodiment of the hybrid alloy lead frame for the power semiconductor device of the present invention. Fig. 13 is a front elevational view showing the mixed alloy lead frame array separating element of the third embodiment of the present invention, which is a mixed alloy lead frame for a power semiconductor device and a manufacturing method thereof. 13 is a hybrid alloy lead frame for a power semiconductor device according to a third embodiment of the invention. The mixed alloy lead frame array of the third embodiment of the present invention is divided into the form number Α0101, page 21/38, 0983408055-0, 201117338 Side view of the. 14A is a front view of a lead frame group soldering plate 3 of a third embodiment of a hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. FIG. 14B is a mixed alloy lead for a power semiconductor device according to the present invention. Frame and Manufacturing Method A side view of a lead frame group welding plate 3 of the third embodiment is a front view of a mounting heat sink for a hybrid alloy lead frame for a power semiconductor device according to a third embodiment of the present invention. Fig. 15B is a side view showing the mounting fin of the third embodiment of the hybrid alloy lead frame for a power semiconductor device and a manufacturing method thereof. Fig. 16A is a front elevational view showing a mounting lead of a third embodiment of a hybrid alloy lead frame and a manufacturing method for a power semiconductor device according to the present invention. Fig. 16B is a side elevational view showing a mounting lead of a hybrid alloy lead frame for a power semiconductor device and a third embodiment of the manufacturing method of the present invention. Figure 17A is a front elevational view of a hybrid alloy lead frame array of a third embodiment of a hybrid alloy lead frame for a power semiconductor device and a method of fabricating the same. Figure 17B is a side elevational view of a hybrid alloy lead frame array of a third embodiment of a hybrid alloy lead frame for a power semiconductor device and a method of fabricating the same. Fig. 17C is a front elevational view showing the mixed alloy lead frame array of the third embodiment of the hybrid alloy lead frame for the power semiconductor device of the present invention. 1st 7D is a mixed alloy lead frame for a power semiconductor device according to the present invention and a manufacturing method thereof. The mixed alloy lead frame array 098137925 Form No. A0101 Page 22 of 38 0983408055-0 201117338 ❹ 封 Seal cutting Side view after. [Main component symbol description] [0008] 1 ' 1 ' 1... : Heat sink 2 ' 2 ^ ' ί 丨: Foot 3 ' 3 "> : 3... . Lead frame group soldering plate 4 ' 4 " ' ^ 1... : wafer stage 6: power semiconductor wafer 6 '6 ->: wafer 7, 7 ' r 1... plastic package 12, 12, 12: heat sink pads 13, 13, , 13 / / : Heat sink positioning holes 21, 21, ' 21 ^ : Pin terminal group 22 ' 22 " '22 I. Pin positioning holes 23, 23 / '23 A: Connecting strips 31, 31 one, 31 one / : Grooves 32, 32 - '32 a · Bow 丨: Foot positioning posts 211, 211, 211: Pin welding [ 212 ...: Jumpers 311, 311 one, 311: Heat sink positioning post 098137925 Form number Α 0101 Page 23 / Total 38 pages 0983408055-0