JP7179172B6 - 半導体用途の構造体をエッチングするための方法 - Google Patents
半導体用途の構造体をエッチングするための方法 Download PDFInfo
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- JP7179172B6 JP7179172B6 JP2021522545A JP2021522545A JP7179172B6 JP 7179172 B6 JP7179172 B6 JP 7179172B6 JP 2021522545 A JP2021522545 A JP 2021522545A JP 2021522545 A JP2021522545 A JP 2021522545A JP 7179172 B6 JP7179172 B6 JP 7179172B6
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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Description
[0002]集積回路(IC)、すなわちチップの製造において、チップの種々の層を表すパターンは、チップ設計者によって生み出される。製造プロセス中に各チップ層の設計を半導体基板上に転写するために、これらのパターンから一連の再利用可能マスク、すなわちフォトマスクが生み出される。マスクパターン生成システムは、高精度レーザ又は電子ビームを使用して、チップの各層の設計をそれぞれのマスク上に画像化する。次いで、マスクは、写真ネガのように、各層の回路パターンを半導体基板上に転写するために使用される。これらの層は、一連のプロセスを用いて蓄積され、それぞれの完成したチップを含む小さなトランジスタ及び電気回路に移動する。したがって、マスク内の任意の欠陥がチップに転写され、潜在的に性能に悪影響を及ぼし得る。十分に深刻な欠陥は、マスクを完全に役に立たないものにしてしまう恐れがある。通常、15から100個のマスクのセットを使用してチップを構成し、繰り返し使用することができる。
[00075]上記の説明は本開示の実施形態を対象としているが、本開示の基本的な範囲を逸脱しなければ、本開示の他の実施形態及びさらなる実施形態が考案されてよく、本開示の範囲は以下の特許請求の範囲によって決まる。
また、本願は以下に記載する態様を含む。
(態様1)
基板上の導電層をパターニングするための方法であって、
前記基板上に堆積した第1の導電層をエッチングするために、第1の流量で、塩素含有ガスを含む混合ガスを供給すること、
前記第1の導電層をエッチングし続けるために、前記第1の流量よりも低い第2の流量まで、第1の混合ガスの中の前記塩素含有ガスを低下させること、及び
前記基板から前記第1の導電層を取り除くために、前記第2の流量よりも大きい第3の流量まで、前記第1の混合ガスの中の前記塩素含有ガスを増加させること
を含む、方法。
(態様2)
前記第1の導電層が、Ti又はTa含有層である、態様1に記載の方法。
(態様3)
前記第1の混合ガスが、不活性ガスをさらに含む、態様1に記載の方法。
(態様4)
前記塩素含有ガスがCl 2 又はHClである、態様1に記載の方法。
(態様5)
前記第1の流量が、前記第3の流量と同じ又は類似である、態様1に記載の方法。
(態様6)
前記第1の導電層をエッチングする前に、水素処理プロセスを実行することをさらに含む、態様1に記載の方法。
(態様7)
前記水素処理プロセスを実行する間、基板温度を150℃よりも高く維持することをさらに含む、態様6に記載の方法。
(態様8)
前記基板温度が約200℃から約300℃である、態様7に記載の方法。
(態様9)
前記第1の導電層が前記基板から取り除かれた後に、前記基板へのポストアニーリングプロセスを実行することをさらに含む、態様1に記載の方法。
(態様10)
前記ポストアニーリングプロセスが、約5barと100barとの間で処理圧力を維持することをさらに含む、態様9に記載の方法。
(態様11)
前記ポストアニーリングプロセスを実行する間、水素含有ガス又は窒素含有ガスを含むアニーリング混合ガスを供給することをさらに含む、態様10に記載の方法。
(態様12)
前記ポストアニーリングプロセスが、前記基板上に露出された第2の導電層を高密度化する、態様9に記載の方法。
(態様13)
第2の材料含有層が、Ru含有材料である、態様12に記載の方法。
(態様14)
前記第1の流量で供給された前記混合ガスが、金属含有材料から酸化物材料を取り除く、態様1に記載の方法。
(態様15)
前記第2の流量で供給された前記混合ガスが、前記第1の導電層の約5%から約95%を取り除く、態様1に記載の方法。
(態様16)
基板上の導電層をパターニングするための方法であって、
前記基板上の残留物を取り除くために、基板に水素処理プロセスを実行することであって、前記処理プロセスが、第1の導電層から残留物材料を取り除くために、100℃を超える温度で実行される、水素処理プロセスを実行すること、
前記基板上の第1の導電層をエッチングするために、第2の導電層が前記基板上に露出するまで、塩素含有ガスを含むエッチング混合ガスを供給することによって、エッチングプロセスを実行すること、及び、
約5barと100barとの間の処理圧力で、ポストアニーリングプロセスを実行すること
を含む、方法。
(態様17)
前記エッチングプロセスを実行することが、
前記第1の導電層をエッチングしながら、第1の流量から第2の流量まで、さらに第3の流量まで、前記エッチング混合ガスの中の前記塩素含有ガスを維持すること
をさらに含む、態様16に記載の方法。
(態様18)
前記第1の流量が、前記第2の流量よりも大きい、態様17に記載の方法。
(態様19)
前記第1の導電層が、Ta又はTi含有層であり、前記第2の導電層が、Ru含有層である、態様16に記載の方法。
(態様20)
基板上の導電層をパターニングするための方法であって、
水素処理プロセスによって、基板上から残留物を取り除くことであって、前記残留物が有機材料を含み、前記基板が、第2の導電層に配置された第1の導電層を含む、残留物を取り除くこと、
第2の導電層が前記基板上に露出するまで、塩素含有ガスを含むエッチング混合ガスを供給することによって、前記第1の導電層をエッチングすることであって、前記第1の導電層をエッチングしながら、前記エッチング混合ガスの中の前記塩素含有ガスが、第1の流量から第2の流量まで、さらに第3の流量まで維持される、前記第1の導電層をエッチングすること、及び、
前記基板上の前記第2の導電層を熱処理するために、約5barと100barとの間の処理圧力でポストアニーリングプロセスを実行すること
を含む、方法。
Claims (14)
- 基板上の導電層をパターニングするための方法であって、
前記基板上に堆積した第1の導電層をエッチングするために、第1の流量で、塩素含有ガスを含む混合ガスを供給すること、
前記第1の導電層をエッチングし続けるために、前記第1の流量よりも低い第2の流量まで、第1の混合ガスの中の前記塩素含有ガスを低下させること、及び
前記基板から前記第1の導電層を取り除くために、前記第2の流量よりも大きい第3の流量まで、前記第1の混合ガスの中の前記塩素含有ガスを増加させること
を含み、前記第1の導電層が、Ti又はTa含有層である、方法。 - 前記第1の混合ガスが、不活性ガスをさらに含む、請求項1に記載の方法。
- 前記塩素含有ガスがCl2又はHClである、請求項1に記載の方法。
- 前記第1の流量が、前記第3の流量と同じ又は類似である、請求項1に記載の方法。
- 前記第1の導電層をエッチングする前に、水素処理プロセスを実行することをさらに含む、請求項1に記載の方法。
- 前記水素処理プロセスを実行する間、基板温度を150℃よりも高く維持することをさらに含む、請求項5に記載の方法。
- 前記基板温度が約200℃から約300℃である、請求項6に記載の方法。
- 前記第1の導電層が前記基板から取り除かれた後に、前記基板へのポストアニーリングプロセスを実行することをさらに含む、請求項1に記載の方法。
- 前記ポストアニーリングプロセスが、約5barと100barとの間で処理圧力を維持することをさらに含む、請求項8に記載の方法。
- 前記ポストアニーリングプロセスを実行する間、水素含有ガス又は窒素含有ガスを含むアニーリング混合ガスを供給することをさらに含む、請求項9に記載の方法。
- 基板上の導電層をパターニングするための方法であって、
前記基板上に堆積した第1の導電層をエッチングするために、第1の流量で、塩素含有ガスを含む混合ガスを供給すること、
前記第1の導電層をエッチングし続けるために、前記第1の流量よりも低い第2の流量まで、第1の混合ガスの中の前記塩素含有ガスを低下させること、
前記基板から前記第1の導電層を取り除くために、前記第2の流量よりも大きい第3の流量まで、前記第1の混合ガスの中の前記塩素含有ガスを増加させること、及び
前記第1の導電層が前記基板から取り除かれた後に、前記基板へのポストアニーリングプロセスを実行すること
を含み、
前記ポストアニーリングプロセスが、前記基板上に露出された第2の導電層を高密度化する、方法。 - 第2の材料含有層が、Ru含有材料である、請求項11に記載の方法。
- 基板上の導電層をパターニングするための方法であって、
前記基板上に堆積した第1の導電層をエッチングするために、第1の流量で、塩素含有ガスを含む混合ガスを供給すること、
前記第1の導電層をエッチングし続けるために、前記第1の流量よりも低い第2の流量まで、第1の混合ガスの中の前記塩素含有ガスを低下させること、及び
前記基板から前記第1の導電層を取り除くために、前記第2の流量よりも大きい第3の流量まで、前記第1の混合ガスの中の前記塩素含有ガスを増加させること
を含み、
前記第1の流量で供給された前記混合ガスが、金属含有材料から酸化物材料を取り除く、方法。 - 前記第2の流量で供給された前記混合ガスが、前記第1の導電層の約5%から約95%を取り除く、請求項1に記載の方法。
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