JP7155748B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7155748B2 JP7155748B2 JP2018155589A JP2018155589A JP7155748B2 JP 7155748 B2 JP7155748 B2 JP 7155748B2 JP 2018155589 A JP2018155589 A JP 2018155589A JP 2018155589 A JP2018155589 A JP 2018155589A JP 7155748 B2 JP7155748 B2 JP 7155748B2
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- 239000004065 semiconductor Substances 0.000 title claims description 176
- 239000004020 conductor Substances 0.000 claims description 155
- 238000007789 sealing Methods 0.000 claims description 82
- 125000006850 spacer group Chemical group 0.000 claims description 30
- 238000000926 separation method Methods 0.000 claims description 10
- 230000003746 surface roughness Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 description 11
- 239000008393 encapsulating agent Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000004299 exfoliation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000446 fuel Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Description
12:第1導体板
14、114:第2導体板
16:封止体
18a、18b、18c:導体スペーサ
22:第1半導体素子
24、124:第2半導体素子
26:第3半導体素子
32:第1外部接続端子
34:第2外部接続端子
36:第3外部接続端子
X1、X2、X3:接合エリア
Y:密着エリア
Z1、Z2:剥離エリア
Claims (10)
- 第1導体板と、
前記第1導体板上に配置された第1半導体素子及び第2半導体素子と、
前記第1半導体素子及び前記第2半導体素子を挟んで前記第1導体板に対向する第2導体板と、
前記第1半導体素子と前記第2導体板の下面との間に配置された第1導体スペーサと、
前記第2半導体素子と前記第2導体板の前記下面との間に配置された第2導体スペーサと、
前記第1導体板と前記第2導体板との間に充填され、前記第1半導体素子及び前記第2半導体素子を封止している封止体と、を備え、
前記第2導体板の前記下面は、前記第1導体スペーサが接合された第1接合エリアと、前記第2導体スペーサが接合された第2接合エリアと、前記封止体が密着している密着エリアと、前記封止体が剥離している剥離エリアとを有し、
前記密着エリアは、前記第1接合エリア、前記第2接合エリア及び前記剥離エリアを取り囲んでおり、
前記剥離エリアは、前記第1接合エリアと前記第2接合エリアとの間に位置しており、
前記剥離エリアは、前記第1接合エリア及び前記第2接合エリアの少なくとも一方から、前記密着エリアによって隔てられている、
半導体装置。 - 前記剥離エリアの表面粗さは、前記密着エリアの表面粗さよりも小さい、請求項1に記載の半導体装置。
- 前記剥離エリアと前記封止体との間の距離は、5マイクロメートル以下である、請求項1又は2に記載の半導体装置。
- 前記剥離エリアの外形は、矩形状、多角形状、円形状、楕円形状又は長円形状である、請求項1から3のいずれか一項に記載の半導体装置。
- 前記剥離エリアは、前記第1接合エリア及び前記第2接合エリアの少なくとも一方まで広がっている、請求項1から4のいずれか一項に記載の半導体装置。
- 前記第1半導体素子及び前記第2半導体素子は、前記第1導体板上で第1方向に沿って配列されており、
前記第1導体板に垂直な方向から平面視したときに、前記第1方向に垂直な第2方向に関して、前記剥離エリアの寸法は、前記第1半導体素子及び前記第2半導体素子の少なくとも一方の寸法よりも大きい、請求項1から5のいずれか一項に記載の半導体装置。 - 前記第1半導体素子及び前記第2半導体素子は、前記第1導体板上で第1方向に沿って配列されており、
前記第1導体板に垂直な方向から平面視したときに、前記第1方向に垂直な第2方向に関して、前記剥離エリアの寸法は、前記第1半導体素子及び前記第2半導体素子の少なくとも一方の寸法よりも小さい、請求項1から5のいずれか一項に記載の半導体装置。 - 前記第1接合エリアと前記第2接合エリアとの間には、単一の前記剥離エリアが存在する、請求項1から7のいずれか一項に記載の半導体装置。
- 前記第1接合エリアと前記第2接合エリアとの間には、複数の前記剥離エリアが存在する、請求項1から7のいずれか一項に記載の半導体装置。
- 前記第1導体板上に配置された第3半導体素子と、
前記第3半導体素子と前記第2導体板の前記下面との間に配置された第3導体スペーサと、をさらに備え、
前記第2導体板の前記下面は、前記第3導体スペーサが接合された第3接合エリアと、前記封止体が剥離している第2剥離エリアとをさらに有し、
前記密着エリアは、前記第3接合エリア及び前記第2剥離エリアをさらに取り囲んでおり、
前記第2剥離エリアは、前記第2接合エリアと前記第3接合エリアとの間に位置している、
請求項1から9のいずれか一項に記載の半導体装置。
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