JP6136978B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6136978B2 JP6136978B2 JP2014034541A JP2014034541A JP6136978B2 JP 6136978 B2 JP6136978 B2 JP 6136978B2 JP 2014034541 A JP2014034541 A JP 2014034541A JP 2014034541 A JP2014034541 A JP 2014034541A JP 6136978 B2 JP6136978 B2 JP 6136978B2
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- JP
- Japan
- Prior art keywords
- sealing resin
- cavity
- radiating plate
- semiconductor chip
- heat radiating
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
2;半導体チップ
3;放熱板
4;空洞
5;封止樹脂
7;はんだ
8;スペーサー
9;冷却器
21;表面
22;裏面
31;表面側放熱板
32;裏面側放熱板
41;先端部
51;薄肉部
60;モジュール
70;ボンディングワイヤ
100;成形型
101;上型
102;下型
103;中型
104;シール材
105;中型挿入口
106;注入口
110;収容室
151;隙間
Claims (7)
- 第1表面と前記第1表面の反対側に位置する第2表面とを有する第1の半導体チップと、
前記第1の半導体チップに所定間隔をあけて隣接する第2の半導体チップと、
前記第1表面にはんだを介して接合された第1放熱板と、
前記第2表面にはんだを介して接合された第2放熱板と、
前記第1放熱板と前記第2放熱板の間に充填されて前記半導体チップを封止する封止樹脂であって、隣接する2つの前記半導体チップの間に前記第1放熱板及び前記第2放熱板に沿って延びるように空洞が形成されており、端部で前記空洞が開口している封止樹脂と、を備え、
前記封止樹脂に空洞が複数形成されており、
複数の前記空洞が前記半導体チップを取り囲んでいる、半導体装置。 - 前記第1放熱板と前記空洞との間に前記封止樹脂が存在している、請求項1に記載の半導体装置。
- 前記空洞が前記封止樹脂を貫通しており、前記封止樹脂の両端部で開口している、請求項1又は2に記載の半導体装置。
- 前記空洞が前記封止樹脂を貫通しておらず、前記封止樹脂の一端部で開口している、請求項1又は2に記載の半導体装置。
- 第1表面と前記第1表面の反対側に位置する第2表面を有する複数の半導体チップと、前記第1表面にはんだを介して接合された第1放熱板と、前記第2表面にはんだを介して接合された第2放熱板と、を備えるモジュールを成形型にセットするセット工程であって、前記成形型が備える中型が、隣接する2つの前記半導体チップの間において前記第1放熱板と前記第2放熱板の間に配置され、前記第1放熱板及び前記第2放熱板に沿って延びるように前記モジュールをセットするセット工程と、
前記成形型にセットされた前記モジュールの前記第1放熱板と前記第2放熱板の間に封止樹脂を充填して前記半導体チップを封止する封止工程と、を備え、
前記成形型が中型を複数備えており、
前記セット工程では、複数の前記中型が前記半導体チップを取り囲んで配置される、半導体装置の製造方法。 - 前記セット工程では、前記中型は、前記第1放熱板との間に隙間を形成するように配置される、請求項5に記載の半導体装置の製造方法。
- 前記封止樹脂から前記中型を引き抜く引抜工程を更に備える、請求項5又は6に記載の半導体装置の製造方法。
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JP2014034541A JP6136978B2 (ja) | 2014-02-25 | 2014-02-25 | 半導体装置及びその製造方法 |
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JP2014034541A JP6136978B2 (ja) | 2014-02-25 | 2014-02-25 | 半導体装置及びその製造方法 |
Publications (2)
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JP2015159256A JP2015159256A (ja) | 2015-09-03 |
JP6136978B2 true JP6136978B2 (ja) | 2017-05-31 |
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JP2014034541A Expired - Fee Related JP6136978B2 (ja) | 2014-02-25 | 2014-02-25 | 半導体装置及びその製造方法 |
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Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7155748B2 (ja) * | 2018-08-22 | 2022-10-19 | 株式会社デンソー | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10144821A (ja) * | 1996-11-11 | 1998-05-29 | Rohm Co Ltd | 樹脂パッケージ型半導体装置およびその製造方法 |
JP2002170850A (ja) * | 2000-11-30 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 電子部品実装構造体とその製造方法 |
US20060076694A1 (en) * | 2004-10-13 | 2006-04-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency |
JP4407489B2 (ja) * | 2004-11-19 | 2010-02-03 | 株式会社デンソー | 半導体装置の製造方法ならびに半導体装置の製造装置 |
JP5076549B2 (ja) * | 2007-02-23 | 2012-11-21 | 株式会社デンソー | 半導体装置 |
JP2009253206A (ja) * | 2008-04-10 | 2009-10-29 | Sharp Corp | 樹脂封止型半導体装置およびその実装構造 |
DE112011105693T5 (de) * | 2011-09-29 | 2014-08-21 | Toyota Jidosha Kabushiki Kaisha | Halbleitervorrichtung |
JP5737272B2 (ja) * | 2012-11-14 | 2015-06-17 | トヨタ自動車株式会社 | 半導体装置 |
JP6083399B2 (ja) * | 2014-02-25 | 2017-02-22 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
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