JP7010167B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7010167B2 JP7010167B2 JP2018139471A JP2018139471A JP7010167B2 JP 7010167 B2 JP7010167 B2 JP 7010167B2 JP 2018139471 A JP2018139471 A JP 2018139471A JP 2018139471 A JP2018139471 A JP 2018139471A JP 7010167 B2 JP7010167 B2 JP 7010167B2
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Description
上下アーム回路の1つのアームを構成する半導体装置であって、
第1主電極(32)と、第1主電極との間に主電流が流れる第2主電極(33)と、を有する少なくとも1つの半導体素子(30)と、
第1主電極に接続された第1主端子(60C)及び第2主電極に接続された第2主端子(60E)を有するとともに、第1主端子及び第2主端子の少なくとも一方を複数有し、第1主端子と第2主端子とが、半導体素子の厚み方向に直交する一方向において側面同士が対向するように隣り合って配置された主端子(60)と、
備え、
一方向において配置が連続する3つ以上の主端子により主端子群(61)が構成され、
主端子群を構成する主端子それぞれの少なくとも一部が、一方向において、半導体素子の両端面(36,37)から延長された延長線間の領域(A1)内に配置されている。
上下アーム回路の1つのアームを構成する半導体装置であって、
第1主電極(32)及び第1主電極との間に主電流が流れる第2主電極(33)をそれぞれ有し、少なくとも第1半導体素子(30a)及び第2半導体素子(30b)を含む複数の半導体素子(30)と、
第1主電極に接続された第1主端子(60C)及び第2主電極に接続された第2主端子(60E)を有するとともに、第1主端子及び第2主端子をそれぞれ複数有し、第1主端子と第2主端子とが、半導体素子の厚み方向に直交する一方向において側面同士が対向するように交互に配置された主端子(60)と、備え、
第1半導体素子及び第2半導体素子は、一方向に並んで配置されるとともに、第1主端子及び第2主端子の間で互いに並列に接続されており、
一方向において配置が連続する2つ以上の主端子により構成された主端子群(62)として第1群(62a)及び第2群(62b)を有し、
第1群を構成する主端子それぞれの少なくとも一部が、一方向において、第1半導体素子の両端面(36a,37a)から延長された延長線間の領域(A1a)内に配置され、第2群を構成する主端子それぞれの少なくとも一部が、一方向において、第2半導体素子の両端面(36b,37b)から延長された延長線間の領域(A1b)内に配置され、
リードフレームの一部として、第1主端子及び第2主端子の少なくとも一方とともに設けられた連結部(86,86C,86E)をさらに備え、
連結部によって、第1主端子及び第2主端子のうちの少なくとも一方において、同じ主端子同士が連結されている。
図1に示す電力変換装置1は、たとえば電気自動車やハイブリッド自動車に搭載される。電力変換装置1は、車両に搭載された直流電源2から供給される直流電圧を、三相交流に変換して、三相交流方式のモータ3に出力するように構成されている。モータ3は、車両の走行駆動源として機能する。電力変換装置1は、モータ3により発電された電力を、直流に変換して直流電源2に充電することもできる。このように、電力変換装置1は、双方向の電力変換が可能となっている。
図2~図7に示すように、半導体装置10は、封止樹脂体20、IGBT30、導電部材40、ターミナル50、主端子60、及び信号端子70を備えている。なお、図5は、図2に対して、封止樹脂体20を省略した図である。図6は、封止樹脂体20の成形後であって、タイバーなど、リードフレーム90の不要部分を除去する前の状態を示している。図7は、IGBT30と主端子60との位置関係を示す平面図であり、封止樹脂体20の一部、導電部材40E、及びターミナル50を省略して図示している。
主端子60は、主端子60C,60Eの少なくとも一方を複数有している。主端子60Cと主端子60Eとは、板面同士が対向するのではなく、側面同士が対向するように、主端子60の板幅方向であるX方向に並んで配置されてる。半導体装置10は、隣り合う主端子60C,60Eによる側面対向部を複数有している。板面とは、主端子60の表面のうち、主端子60の板厚方向の面であり、側面とは板面をつなぐ面であって主端子60の延設方向に沿う面である。主端子60の残りの表面は、延設方向における両端面、すなわち突出先端面と後端面である。側面対向部を構成する側面は、主端子60の板厚方向において少なくとも一部が対向すればよい。たとえば板厚方向にずれて設けられてもよい。ただし、全面対向の方が効果的である。
上記したように、本実施形態の半導体装置10は、主端子60C,60Eの少なくとも一方を複数有しており、主端子60C,60EがX方向において隣り合って配置されている。そして、隣り合う主端子60C,60Eの側面同士が対向している。主端子60C,60Eで主電流の向きは逆向きとなる。このように、主端子60C,60Eは、主電流が流れたときに生じる磁束をお互いに打ち消すように配置されている。したがって、インダクタンスを低減することができる。特に本実施形態では、主端子60C,60Eの側面対向部を複数有するため、インダクタンスを効果的に低減することができる。同じ種類の主端子60を複数にして並列化するため、インダクタンスを低減することができる。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
Claims (14)
- 上下アーム回路の1つのアームを構成する半導体装置であって、
第1主電極(32)と、前記第1主電極との間に主電流が流れる第2主電極(33)と、を有する少なくとも1つの半導体素子(30)と、
前記第1主電極に接続された第1主端子(60C)及び前記第2主電極に接続された第2主端子(60E)を有するとともに、前記第1主端子及び前記第2主端子の少なくとも一方を複数有し、前記第1主端子と前記第2主端子とが、前記半導体素子の厚み方向に直交する一方向において側面同士が対向するように隣り合って配置された主端子(60)と、
備え、
前記一方向において配置が連続する3つ以上の前記主端子により主端子群(61)が構成され、
前記主端子群を構成する前記主端子それぞれの少なくとも一部が、前記一方向において、前記半導体素子の両端面(36,37)から延長された延長線間の領域(A1)内に配置されている半導体装置。 - 前記主端子群を構成する一部の前記主端子は、それぞれの全体が前記領域内に配置され、残りの前記主端子はそれぞれの一部が前記領域内に配置されている請求項1に記載の半導体装置。
- 前記主端子群を構成する前記主端子は、それぞれの全体が前記領域内に配置されている前記主端子を複数含む請求項2に記載の半導体装置。
- 前記主端子群を構成する複数の前記主端子について、それぞれの全体が前記領域内に配置されている請求項1に記載の半導体装置。
- 前記主端子の数が奇数とされている請求項1~4いずれか1項に記載の半導体装置。
- 前記第1主端子及び前記第2主端子は、前記一方向において、前記半導体素子の中心を通る中心線に対して線対称配置とされている請求項5に記載の半導体装置。
- 前記第1主端子及び前記第2主端子のうち、数が少ない前記主端子のほうが数が多い前記主端子よりも断面積が大きくされている請求項5又は請求項6に記載の半導体装置。
- 数が少ない前記主端子の延設長さが、数が多い前記主端子よりも長くされている請求項7に記載の半導体装置。
- 前記主端子の数が偶数とされている請求項1~4いずれか1項に記載の半導体装置。
- 前記第1主端子及び前記第2主端子の延設長さが等しく、且つ、断面積も等しくされている請求項9に記載の半導体装置。
- 前記主端子群を構成する前記主端子の数が5以上とされている請求項1~10いずれか1項に記載の半導体装置。
- すべての前記主端子によって前記主端子群が構成されている請求項1~11いずれか1項に記載の半導体装置。
- リードフレームの一部として、前記第1主端子及び前記第2主端子の少なくとも一方とともに設けられた連結部(86,86C,86E)をさらに備え、
前記連結部によって、前記第1主端子及び前記第2主端子のうちの少なくとも一方において、同じ前記主端子同士が連結されている請求項1~12いずれか1項に記載の半導体装置。 - 上下アーム回路の1つのアームを構成する半導体装置であって、
第1主電極(32)及び前記第1主電極との間に主電流が流れる第2主電極(33)をそれぞれ有し、少なくとも第1半導体素子(30a)及び第2半導体素子(30b)を含む複数の半導体素子(30)と、
前記第1主電極に接続された第1主端子(60C)及び前記第2主電極に接続された第2主端子(60E)を有するとともに、前記第1主端子及び前記第2主端子をそれぞれ複数有し、前記第1主端子と前記第2主端子とが、前記半導体素子の厚み方向に直交する一方向において側面同士が対向するように交互に配置された主端子(60)と、備え、
前記第1半導体素子及び前記第2半導体素子は、前記一方向に並んで配置されるとともに、前記第1主端子及び前記第2主端子の間で互いに並列に接続されており、
前記一方向において配置が連続する2つ以上の前記主端子により構成された主端子群(62)として第1群(62a)及び第2群(62b)を有し、
前記第1群を構成する前記主端子それぞれの少なくとも一部が、前記一方向において、前記第1半導体素子の両端面(36a,37a)から延長された延長線間の領域(A1a)内に配置され、前記第2群を構成する前記主端子それぞれの少なくとも一部が、前記一方向において、前記第2半導体素子の両端面(36b,37b)から延長された延長線間の領域(A1b)内に配置され、
リードフレームの一部として、前記第1主端子及び前記第2主端子の少なくとも一方とともに設けられた連結部(86,86C,86E)をさらに備え、
前記連結部によって、前記第1主端子及び前記第2主端子のうちの少なくとも一方において、同じ前記主端子同士が連結されている半導体装置。
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