JP7001050B2 - 半導体装置 - Google Patents
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- JP7001050B2 JP7001050B2 JP2018247101A JP2018247101A JP7001050B2 JP 7001050 B2 JP7001050 B2 JP 7001050B2 JP 2018247101 A JP2018247101 A JP 2018247101A JP 2018247101 A JP2018247101 A JP 2018247101A JP 7001050 B2 JP7001050 B2 JP 7001050B2
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 238000000926 separation method Methods 0.000 claims description 63
- 238000009792 diffusion process Methods 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
図1は、実施の形態1に係る半導体装置を示すブロック図である。半導体装置1は、ハーフブリッジを構成するパワーチップ2,3の駆動に用いられるHVICである。半導体装置1は、ハイサイド回路領域4と、ローサイド回路領域5と、ハイサイド回路領域4とローサイド回路領域5の間の信号伝達を行うレベルシフト回路6とを備えている。ローサイド回路領域5は、基板電位GNDを基準とし、入力信号INに応じてパワーチップ3を駆動する。ハイサイド回路領域4は、基板電位から高耐圧に分離され、入力信号INに応じてパワーチップ2を駆動する。
図6は、実施の形態2に係る半導体装置のハイサイド回路領域周辺を示す上面図である。図7は図6のIII-IVに沿った断面図である。図8は図6のI-IIに沿った断面図である。
図9及び図10は、実施の形態3に係る半導体装置を示す断面図である。図9は図2のI-IIに沿った断面図に対応し、図10は図2のIII-IVに沿った断面図に対応する。
図11及び図12は、実施の形態4に係る半導体装置を示す断面図である。図11は図2のI-IIに沿った断面図に対応し、図12は図2のIII-IVに沿った断面図に対応する。埋め込み絶縁膜26の下で半導体基板8に空洞27が設けられている。このCavity-SOI構造により実施の形態3よりも高耐圧分離領域9及び高耐圧MOS7を高耐圧化することができる。その他の構成及び効果は実施の形態3と同様である。
図13及び図14は、実施の形態5に係る半導体装置を示す断面図である。図13は図2のI-IIに沿った断面図に対応し、図14は図2のIII-IVに沿った断面図に対応する。N型拡散層12よりも不純物濃度の濃いN+型層28が埋め込み絶縁膜26の上にP型拡散層13と接して設けられている。これにより実施の形態3よりも高耐圧分離領域9及び高耐圧MOS7を高耐圧化することができる。その他の構成及び効果は実施の形態3と同様である。
4 ハイサイド回路領域、5 ローサイド回路領域、7 高耐圧MOS、8 半導体基板、9 高耐圧分離領域、11 トレンチ分離、12 N型拡散層、14 N-型領域、24 複数のN型領域、25 複数の金属配線、26 埋め込み絶縁膜、27 空洞、28 N+型層
Claims (5)
- ハイサイド回路領域と、ローサイド回路領域と、前記ハイサイド回路領域と前記ローサイド回路領域の間の信号伝達を行う高耐圧MOSが1つの半導体基板に設けられた半導体装置であって、
前記ハイサイド回路領域と前記ローサイド回路領域を分離する高耐圧分離領域と、
前記高耐圧MOSと前記高耐圧分離領域を分離するトレンチ分離と、
前記ハイサイド回路領域及び前記高耐圧分離領域において前記半導体基板の上面に設けられたN型拡散層と、
前記トレンチ分離の両側面に設けられ、前記N型拡散層よりも不純物濃度の薄いN型領域とを備えることを特徴とする半導体装置。 - 前記半導体基板と前記N型拡散層の間に設けられた埋め込み絶縁膜を更に備え、
前記トレンチ分離は前記埋め込み絶縁膜に達していることを特徴とする請求項1に記載の半導体装置。 - 前記埋め込み絶縁膜の下に空洞が設けられていることを特徴とする請求項2に記載の半導体装置。
- 前記埋め込み絶縁膜の上に設けられ、前記N型拡散層よりも不純物濃度の濃いN+型層を更に備えることを特徴とする請求項2又は3に記載の半導体装置。
- 前記半導体基板はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2018247101A JP7001050B2 (ja) | 2018-12-28 | 2018-12-28 | 半導体装置 |
US16/452,688 US11211449B2 (en) | 2018-12-28 | 2019-06-26 | Semiconductor device |
DE102019220407.4A DE102019220407B4 (de) | 2018-12-28 | 2019-12-20 | Halbleitervorrichtung |
DE102019009424.7A DE102019009424B4 (de) | 2018-12-28 | 2019-12-20 | Halbleitervorrichtung |
CN201911335808.4A CN111384177B (zh) | 2018-12-28 | 2019-12-23 | 半导体装置 |
JP2021183403A JP7160167B2 (ja) | 2018-12-28 | 2021-11-10 | 半導体装置 |
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JP2010147181A (ja) | 2008-12-17 | 2010-07-01 | Mitsubishi Electric Corp | 半導体装置 |
JP2012195394A (ja) | 2011-03-16 | 2012-10-11 | Toshiba Corp | 半導体装置の製造方法 |
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JP2015088597A (ja) | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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CN104247005A (zh) * | 2012-10-12 | 2014-12-24 | 富士电机株式会社 | 半导体装置 |
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JP6458878B2 (ja) * | 2015-11-19 | 2019-01-30 | 富士電機株式会社 | 半導体装置 |
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- 2019-12-20 DE DE102019220407.4A patent/DE102019220407B4/de active Active
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JP2006093229A (ja) | 2004-09-21 | 2006-04-06 | Denso Corp | 半導体装置およびその製造方法 |
JP2010147181A (ja) | 2008-12-17 | 2010-07-01 | Mitsubishi Electric Corp | 半導体装置 |
JP2012195394A (ja) | 2011-03-16 | 2012-10-11 | Toshiba Corp | 半導体装置の製造方法 |
JP2013232577A (ja) | 2012-05-01 | 2013-11-14 | Mitsubishi Electric Corp | 半導体装置 |
JP2015088597A (ja) | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017045966A (ja) | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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