JP6963448B2 - 電子部品 - Google Patents
電子部品 Download PDFInfo
- Publication number
- JP6963448B2 JP6963448B2 JP2017176140A JP2017176140A JP6963448B2 JP 6963448 B2 JP6963448 B2 JP 6963448B2 JP 2017176140 A JP2017176140 A JP 2017176140A JP 2017176140 A JP2017176140 A JP 2017176140A JP 6963448 B2 JP6963448 B2 JP 6963448B2
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- pad
- device chips
- substrate
- bump
- bumps
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description
実施例1におけるバンプ16aに加わる応力をシミュレーションした。比較例1として、バンプ16aの代わりに径の小さなバンプ16を用いたサンプルについてもシミュレーションした。
基板10:長さLx1=2.5mm、長さLy1=2.0mm
絶縁層20a:厚さt1が85μmのHTCC
絶縁層20b:厚さt3が10μmのHTCC
配線22c:厚さt2が10μmのタングステン
パッド24、環状金属層28:厚さt4が15μmのタングステン
バンプ16:高さHが12.5μmおよび直径φ1が60μmの金
バンプ16a:高さHが12.5μmおよび直径φ2が120μmの金
デバイスチップ11aから11d:厚さt5が0.15mm、長さLx2が1.01mmおよび長さLy2が0.77mmの42°回転YカットX伝搬タンタル酸リチウム基板、Y方向が結晶方位のX軸方向
シミュレーション2として、デバイスチップ11aから11dの平面形状が互いに異なる場合についてバンプ16aに加わる応力を算出した。
デバイスチップ11a:Lx2a=1.07mm、Ly2a=0.77mm
デバイスチップ11b:Lx2b=0.94mm、Ly2b=0.70mm
デバイスチップ11c:Lx2c=0.84mm、Ly2c=0.77mm
デバイスチップ11d:Lx2d=1.01mm、Ly2d=0.60mm
その他のシミュレーション条件はシミュレーション1と同じである。
図13は、実施例1の変形例1に係る電子部品の平面図であり、基板20の上面図であり、デバイスチップを破線で図示している。図13に示すように、パッド24aに他のバンプ16と同じ径のバンプ16bが複数設けられている。その他の構成は実施例1と同じであり説明を省略する。
12 機能素子
16、16a、16b バンプ
14、14a、24、24a パッド
51−54 フィルタ
Claims (10)
- 基板と、
平面形状が矩形状であり、1つのデバイスチップの矩形を構成する4つの角のうちの1つである角部が他の3つのデバイスチップ各々の前記角部と互いに隣接するよう前記基板上に配置された4つのデバイスチップと、
前記4つのデバイスチップの各々の前記基板側の面に設けられ、前記角部に最も近い第1パッドと、
前記4つのデバイスチップの各々において、前記第1パッドと前記基板とを接合する1または複数の第1バンプと、
前記4つのデバイスチップの各々の前記基板側の面に設けられ、前記第1パッド以外のパッドの一つである第2パッドと、
前記4つのデバイスチップの各々において、前記第2パッドと前記基板とを接合し、前記第2パッドとの接合面積の和が前記第1パッドと前記1または複数の第1バンプとの接合面積の和より小さい第2バンプと、
を備える電子部品。 - 前記4つのデバイスチップのうちの1つのデバイスチップにおいて、前記第2パッドと前記第2バンプとの接合面積は、前記第1パッドと前記1または複数の第1バンプとの接合面積の和の2/3以下である請求項1に記載の電子部品。
- 前記4つのデバイスチップの各々において、前記第1パッドは、前記第1バンプが1つのみ接合する請求項1または2に記載の電子部品。
- 前記4つのデバイスチップの各々において、前記第1パッドは、複数の第1バンプが接合する請求項1または2に記載の電子部品。
- 前記4つのデバイスチップの各々において、前記第1パッドと前記複数の第1バンプの一つとの接合面積は前記第2パッドと前記第2バンプとの接合面積と等しい請求項4に記載の電子部品。
- 前記4つのデバイスチップのうち隣接する2つのデバイスチップのそれぞれに設けられた互いに隣接する2辺は平行である請求項1から5のいずれか一項記載の電子部品。
- 前記4つのデバイスチップは、各々前記基板に空隙を介し対向する弾性波素子を有する請求項1から6のいずれか一項に記載の電子部品。
- 前記4つのデバイスチップは、各々前記基板に空隙を介し対向し、入力端子と出力端子との間に接続された弾性波フィルタを有する請求項1から6のいずれか一項に記載の電子部品。
- 前記第1パッドは、前記入力端子または前記出力端子に接続される請求項8記載の電子部品。
- 前記4つのデバイスチップは、各々前記基板に空隙を介し対向し、共通端子と信号端子との間に接続された弾性波フィルタを有し、
前記第1パッドは前記共通端子に接続される請求項1から6のいずれか一項に記載の電子部品。
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