JP6822791B2 - 半導体装置および半導体チップ - Google Patents
半導体装置および半導体チップ Download PDFInfo
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- JP6822791B2 JP6822791B2 JP2016132628A JP2016132628A JP6822791B2 JP 6822791 B2 JP6822791 B2 JP 6822791B2 JP 2016132628 A JP2016132628 A JP 2016132628A JP 2016132628 A JP2016132628 A JP 2016132628A JP 6822791 B2 JP6822791 B2 JP 6822791B2
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- 239000004065 semiconductor Substances 0.000 title claims description 110
- 230000010355 oscillation Effects 0.000 claims description 36
- 230000000052 comparative effect Effects 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49596—Oscillators in combination with lead-frames
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、本発明の実施形態に係る半導体装置1の構成を示す平面図、図2は、半導体装置1の斜視図である。半導体装置1は、リードフレームを構成するダイパッド50上に半導体チップ10および発振子30が搭載されている。半導体チップ10は、矩形の外形を有し、半導体チップ10の外縁を形成する各辺に沿って複数の電極パッドが設けられている。半導体チップ10の1つの辺A1に対向する位置に、リードフレームを構成する複数のリード端子51が設けられている。複数のリード端子51は、辺A1の方向に沿って配列されている。発振子30は、複数のリード端子51と半導体チップ10との間に配置されている。
図5は、本発明の第2の実施形態に係る半導体装置1Aの構成を示す平面図である。半導体装置1Aを構成する半導体チップ10Aは、発振回路11に接続された電極パッド21と、発振回路11に接続されていない電極パッド22とを含む複数の電極パッドが、半導体チップ10Aの外縁を形成する辺A1に沿って複数の列をなして配置されている。図5に示す例では、発振回路11に接続された2つの電極パッド21と、発振回路11に接続されていない複数の電極パッド22の一部が、外側(辺A1から近い側)に配列され、発振回路11に接続されていない複数の電極パッド22の他の一部が内側(辺A1から遠い側)に配列されている。
10 10A 半導体チップ
11 発振回路
21、22 電極パッド
30 発振子
31 電極パッド
41、42 ワイヤ
51 リード端子
Claims (5)
- 所定の機能を有する回路を含み、互いに離間して配置され且つ前記回路に接続された2つの第1の端子および前記2つの第1の端子の一方と他方との間に配置され且つ前記回路に接続されていない複数の第2の端子が1つの辺に沿って形成された半導体チップと、
前記1つの辺に対向する前記半導体チップ外の位置に設けられ、各々が前記複数の第2の端子のいずれかと第1のワイヤによって接続された複数の第3の端子と、
前記半導体チップと前記第3の端子との間に設けられ、前記2つの第1の端子の各々と第2のワイヤによってそれぞれ接続され且つ前記第1のワイヤの少なくとも一部の下方において、前記1つの辺の方向に沿って互いに離間して配置された2つの第4の端子を有する電子部品と、
を含み、
前記第1の端子は、前記第1のワイヤと前記第2のワイヤとが交差しない位置であって、前記回路との距離が前記第2の端子よりも遠い位置に配置されており、
前記半導体チップは、前記複数の第2の端子の端子間および前記第1の端子と前記1つの辺との間の領域を経由して前記回路と前記第1の端子とを接続する内部配線を有する
半導体装置。 - 前記第1の端子は、前記1つの辺の方向において前記第4の端子と重なる位置に設けられている
請求項1に記載の半導体装置。 - 前記第1の端子および前記複数の第2の端子は、前記1つの辺に沿って複数の列をなして配置されている
請求項1または請求項2に記載の半導体装置。 - 前記電子部品は発振子であり、
前記回路は、前記第2のワイヤによって前記発振子に接続された発振回路である
請求項1から請求項3のいずれか1項に記載の半導体装置。 - 前記複数の第3の端子の各々はリードフレームを構成するリード端子である
請求項1から請求項4のいずれか1項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016132628A JP6822791B2 (ja) | 2016-07-04 | 2016-07-04 | 半導体装置および半導体チップ |
US15/636,671 US10497618B2 (en) | 2016-07-04 | 2017-06-29 | Semiconductor device and semiconductor chip |
CN201710532505.6A CN107579709B (zh) | 2016-07-04 | 2017-07-03 | 半导体装置以及半导体芯片 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016132628A JP6822791B2 (ja) | 2016-07-04 | 2016-07-04 | 半導体装置および半導体チップ |
Publications (2)
Publication Number | Publication Date |
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JP2018006602A JP2018006602A (ja) | 2018-01-11 |
JP6822791B2 true JP6822791B2 (ja) | 2021-01-27 |
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Application Number | Title | Priority Date | Filing Date |
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JP2016132628A Active JP6822791B2 (ja) | 2016-07-04 | 2016-07-04 | 半導体装置および半導体チップ |
Country Status (3)
Country | Link |
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US (1) | US10497618B2 (ja) |
JP (1) | JP6822791B2 (ja) |
CN (1) | CN107579709B (ja) |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0386498B1 (en) * | 1989-02-17 | 1996-06-19 | Kabushiki Kaisha Toshiba | Oscillator |
JP3178068B2 (ja) * | 1991-05-31 | 2001-06-18 | セイコーエプソン株式会社 | 圧電発振器 |
US5912592A (en) * | 1994-07-04 | 1999-06-15 | Seiko Epson Corporation | Piezoelectric oscillator |
US5608359A (en) * | 1995-10-10 | 1997-03-04 | Motorola, Inc. | Function-differentiated temperature compensated crystal oscillator and method of producing the same |
US5751015A (en) * | 1995-11-17 | 1998-05-12 | Micron Technology, Inc. | Semiconductor reliability test chip |
JPH11355042A (ja) * | 1998-06-12 | 1999-12-24 | Murata Mfg Co Ltd | 発振器モジュールおよびそれを用いた通信機 |
US6291898B1 (en) * | 2000-03-27 | 2001-09-18 | Advanced Semiconductor Engineering, Inc. | Ball grid array package |
JP2004047811A (ja) * | 2002-07-12 | 2004-02-12 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2004165429A (ja) | 2002-11-13 | 2004-06-10 | Sony Corp | 半導体装置及びその製造方法、受動素子及びその集積体、並びにリードフレーム |
JP3783235B2 (ja) | 2003-06-16 | 2006-06-07 | セイコーエプソン株式会社 | 圧電発振器とその製造方法ならびに圧電発振器を利用した携帯電話装置および圧電発振器を利用した電子機器 |
JP4314580B2 (ja) * | 2004-10-01 | 2009-08-19 | ヤマハ株式会社 | 物理量センサ、およびこれに使用するリードフレーム |
JP5952074B2 (ja) * | 2012-04-27 | 2016-07-13 | ラピスセミコンダクタ株式会社 | 半導体装置及び計測機器 |
-
2016
- 2016-07-04 JP JP2016132628A patent/JP6822791B2/ja active Active
-
2017
- 2017-06-29 US US15/636,671 patent/US10497618B2/en active Active
- 2017-07-03 CN CN201710532505.6A patent/CN107579709B/zh active Active
Also Published As
Publication number | Publication date |
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US10497618B2 (en) | 2019-12-03 |
CN107579709B (zh) | 2022-03-01 |
CN107579709A (zh) | 2018-01-12 |
JP2018006602A (ja) | 2018-01-11 |
US20180005888A1 (en) | 2018-01-04 |
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