JP6598723B2 - パッケージウェーハの製造方法 - Google Patents
パッケージウェーハの製造方法 Download PDFInfo
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- JP6598723B2 JP6598723B2 JP2016076473A JP2016076473A JP6598723B2 JP 6598723 B2 JP6598723 B2 JP 6598723B2 JP 2016076473 A JP2016076473 A JP 2016076473A JP 2016076473 A JP2016076473 A JP 2016076473A JP 6598723 B2 JP6598723 B2 JP 6598723B2
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- Prior art keywords
- wafer
- groove
- mold
- mold resin
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000011347 resin Substances 0.000 claims description 76
- 229920005989 resin Polymers 0.000 claims description 76
- 230000002093 peripheral effect Effects 0.000 claims description 27
- 238000000465 moulding Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/04—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
Description
12 溝
13 リング状溝
14 リング状溝底面
17 デバイス領域の表面
18 金型とウェーハの間の空間
31 金型
32 金型の側壁(側部)
A1 デバイス領域
A2 外周余剰領域
D デバイス
L 分割予定ライン
t1 仕上げ厚さ
PW パッケージウェーハ
W ウェーハ
Claims (1)
- 格子状の分割予定ラインによって区画され表面にバンプを備えたデバイスが形成されたデバイス領域と該デバイス領域を囲繞して形成された外周余剰領域とを備えるウェーハの表面側から該分割予定ラインに沿って仕上げ厚さ以上の深さの溝を形成する溝形成ステップと、
ウェーハの該デバイス領域及び該外周余剰領域の境界に沿って該溝の深さ以上でウェーハの厚み方向途中までの深さのリング状溝を形成するリング状溝形成ステップと、
該溝形成ステップ及び該リング状溝形成ステップを実施した後に、該リング状溝に係合する凹形状の成形装置の金型を、該金型の凹形状の側部を該リング状溝底面に当接させ且つデバイス領域の表面と空間をもって係合させて載置し、該金型の該デバイス領域の表面との該空間内にモールド樹脂を充填するモールド樹脂充填ステップと、を備え、
該デバイス領域の表面にモールド樹脂が被覆され該溝にモールド樹脂が埋設されたパッケージウェーハを製造するパッケージウェーハの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016076473A JP6598723B2 (ja) | 2016-04-06 | 2016-04-06 | パッケージウェーハの製造方法 |
TW106106087A TWI723135B (zh) | 2016-04-06 | 2017-02-23 | 封裝晶圓的製造方法 |
CN201710149666.7A CN107275233B (zh) | 2016-04-06 | 2017-03-14 | 封装晶片的制造方法 |
US15/472,995 US10269639B2 (en) | 2016-04-06 | 2017-03-29 | Method of manufacturing packaged wafer |
KR1020170039970A KR102253564B1 (ko) | 2016-04-06 | 2017-03-29 | 패키지 웨이퍼의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016076473A JP6598723B2 (ja) | 2016-04-06 | 2016-04-06 | パッケージウェーハの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017188575A JP2017188575A (ja) | 2017-10-12 |
JP6598723B2 true JP6598723B2 (ja) | 2019-10-30 |
Family
ID=59998797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016076473A Active JP6598723B2 (ja) | 2016-04-06 | 2016-04-06 | パッケージウェーハの製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10269639B2 (ja) |
JP (1) | JP6598723B2 (ja) |
KR (1) | KR102253564B1 (ja) |
CN (1) | CN107275233B (ja) |
TW (1) | TWI723135B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861761B2 (en) * | 2017-09-29 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor packaged wafer and method for forming the same |
DE102020108114A1 (de) * | 2020-03-24 | 2021-09-30 | Infineon Technologies Ag | Halbleitergehäuse und verfahren zur herstellung eines halbleitergehäuses |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH02125633A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 集積回路 |
JP3516592B2 (ja) * | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
JP3982082B2 (ja) * | 1998-09-28 | 2007-09-26 | ソニー株式会社 | 半導体装置の製造方法 |
JP3291289B2 (ja) * | 2000-01-19 | 2002-06-10 | サンユレック株式会社 | 電子部品の製造方法 |
JP3455762B2 (ja) * | 1999-11-11 | 2003-10-14 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP3784597B2 (ja) * | 1999-12-27 | 2006-06-14 | 沖電気工業株式会社 | 封止樹脂及び樹脂封止型半導体装置 |
JP3815267B2 (ja) * | 2001-06-28 | 2006-08-30 | 株式会社デンソー | マスキング剤塗布方法と装置及びマスク方法と装置 |
DE10202881B4 (de) * | 2002-01-25 | 2007-09-20 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips |
JP3727939B2 (ja) * | 2003-01-08 | 2005-12-21 | 新光電気工業株式会社 | 半導体装置の製造方法 |
KR100546372B1 (ko) * | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | 웨이퍼 레벨 칩 사이즈 패키지의 제조방법 |
JP2006032661A (ja) * | 2004-07-16 | 2006-02-02 | Disco Abrasive Syst Ltd | 切削装置 |
JP4607531B2 (ja) | 2004-09-29 | 2011-01-05 | カシオマイクロニクス株式会社 | 半導体装置の製造方法 |
JP2006148004A (ja) * | 2004-11-24 | 2006-06-08 | Toshiba Corp | 薬液塗布方法及び薬液塗布装置 |
US7400037B2 (en) * | 2004-12-30 | 2008-07-15 | Advanced Chip Engineering Tachnology Inc. | Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP |
JP5192646B2 (ja) * | 2006-01-16 | 2013-05-08 | Towa株式会社 | 光素子の樹脂封止方法、その樹脂封止装置、および、その製造方法 |
US20080044984A1 (en) * | 2006-08-16 | 2008-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors |
JP2009043992A (ja) * | 2007-08-09 | 2009-02-26 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
JP4538764B2 (ja) * | 2008-07-24 | 2010-09-08 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP5202493B2 (ja) * | 2009-10-21 | 2013-06-05 | シャープ株式会社 | 半導体装置の製造装置および半導体装置の製造方法 |
JP2011124266A (ja) * | 2009-12-08 | 2011-06-23 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
TWI447798B (zh) * | 2010-12-07 | 2014-08-01 | Alpha & Omega Semiconductor Cayman Ltd | 一種在晶圓級封裝的模封程序中避免晶圓破損的方法 |
CN102543767B (zh) * | 2010-12-07 | 2015-04-08 | 万国半导体(开曼)股份有限公司 | 一种在晶圆级封装的塑封工序中避免晶圆破损的方法 |
KR101867489B1 (ko) * | 2012-06-20 | 2018-06-14 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 형성방법 |
JP6366351B2 (ja) * | 2014-05-13 | 2018-08-01 | 株式会社ディスコ | ウェーハの加工方法 |
JP6295154B2 (ja) * | 2014-07-18 | 2018-03-14 | 株式会社ディスコ | ウェーハの分割方法 |
US9466585B1 (en) * | 2015-03-21 | 2016-10-11 | Nxp B.V. | Reducing defects in wafer level chip scale package (WLCSP) devices |
-
2016
- 2016-04-06 JP JP2016076473A patent/JP6598723B2/ja active Active
-
2017
- 2017-02-23 TW TW106106087A patent/TWI723135B/zh active
- 2017-03-14 CN CN201710149666.7A patent/CN107275233B/zh active Active
- 2017-03-29 KR KR1020170039970A patent/KR102253564B1/ko active IP Right Grant
- 2017-03-29 US US15/472,995 patent/US10269639B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN107275233B (zh) | 2022-06-17 |
CN107275233A (zh) | 2017-10-20 |
TW201803024A (zh) | 2018-01-16 |
US20170294353A1 (en) | 2017-10-12 |
KR20170114939A (ko) | 2017-10-16 |
KR102253564B1 (ko) | 2021-05-17 |
TWI723135B (zh) | 2021-04-01 |
US10269639B2 (en) | 2019-04-23 |
JP2017188575A (ja) | 2017-10-12 |
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