JP6580728B2 - ファン−アウト半導体パッケージモジュール - Google Patents
ファン−アウト半導体パッケージモジュール Download PDFInfo
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- JP6580728B2 JP6580728B2 JP2018029726A JP2018029726A JP6580728B2 JP 6580728 B2 JP6580728 B2 JP 6580728B2 JP 2018029726 A JP2018029726 A JP 2018029726A JP 2018029726 A JP2018029726 A JP 2018029726A JP 6580728 B2 JP6580728 B2 JP 6580728B2
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- fan
- semiconductor package
- package module
- hole
- out semiconductor
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Classifications
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Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割を果たすことはできず、外部からの物理的又は化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3はファン−イン半導体パッケージのパッケージング前後を概略的に示した断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示した断面図である。
図9はファン−アウト半導体パッケージモジュールの一例を概略的に示した断面図である。
1010 メインボード
1020 チップ関連部品
1030 ネットワーク関連部品
1040 その他の部品
1050 カメラ
1060 アンテナ
1070 ディスプレイ
1080 電池
1090 信号ライン
1100 スマートフォン
1101 本体
1110 メインボード
1120 部品
1121 半導体パッケージ
1130 カメラ
2200 ファン−イン半導体パッケージ
2220 半導体チップ
2221 本体
2222 接続パッド
2223 パッシベーション膜
2240 連結部材
2241 絶縁層
2242 再配線層
2243 ビア
2250 パッシベーション層
2260 アンダーバンプ金属層
2270 半田ボール
2280 アンダーフィル樹脂
2290 モールディング材
2500 メインボード
2301 プリント回路基板
2302 プリント回路基板
2100 ファン−アウト半導体パッケージ
2120 半導体チップ
2121 本体
2122 接続パッド
2140 連結部材
2141 絶縁層
2142 再配線層
2143 ビア
2150 パッシベーション層
2160 アンダーバンプ金属層
2170 半田ボール
100A〜100D ファン−アウト半導体パッケージモジュール
110 コア部材
111、111a、111b、111c 絶縁層
112a、112b、112c、112d 配線層
113a、113b、113c ビア
115 金属層
120 半導体チップ
121 本体
122 接続パッド
125A、125B、125C、125D、125E、125F 受動部品
131、132 封止材
140 連結部材
141 絶縁層
142 再配線層
143 ビア
150 パッシベーション層
160 アンダーバンプ金属層
170 電気接続構造体
180 補強部材
182a、182b 金属パターン
211、212 粘着フィルム
Claims (24)
- 互いに離隔している第1貫通孔及び第2貫通孔を有するコア部材と、
前記第1貫通孔内に配置され、接続パッドが配置された活性面、及び前記活性面の反対側である非活性面を有する半導体チップと、
前記第2貫通孔内に配置された第2受動部品と、
前記コア部材及び前記第2受動部品のそれぞれの少なくとも一部を覆い、前記第2貫通孔内の少なくとも一部を満たす第1封止材と、
前記第1封止材上に配置された補強部材と、
前記半導体チップの少なくとも一部を覆い、前記第1貫通孔内の少なくとも一部を満たす第2封止材と、
前記コア部材、前記半導体チップの活性面、及び前記第2受動部品上に配置され、前記接続パッド、及び前記第2受動部品と電気的に連結された再配線層を含む連結部材と、を含む、ファン−アウト半導体パッケージモジュール。 - 前記第1貫通孔内に前記半導体チップと並んで配置された第1受動部品をさらに含み、
前記第2封止材は、前記第1受動部品の少なくとも一部を覆い、
前記第1受動部品は、前記再配線層と電気的に連結される、請求項1に記載のファン−アウト半導体パッケージモジュール。 - 前記第1受動部品は、前記第2受動部品よりも厚さが厚い、請求項2に記載のファン−アウト半導体パッケージモジュール。
- 前記半導体チップは、前記コア部材よりも厚さが厚い、請求項1から3のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記第1貫通孔は、前記第1封止材及び前記補強部材を貫通する、請求項1から4のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記第2封止材は、前記補強部材の少なくとも一部を覆う、請求項1から5のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記第2封止材の上面は、前記第1封止材の上面よりも上部に位置する、請求項1から6のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記補強部材は、前記第1封止材よりも弾性係数が大きい、請求項1から7のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記補強部材は、ガラス繊維、無機フィラー、及び絶縁樹脂を含む、請求項1から8のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記補強部材の少なくとも一面に金属パターンが配置される、請求項1から9のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記第2貫通孔の壁面に配置された金属層をさらに含む、請求項1から10のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
- 前記第1貫通孔の壁面は、前記第2封止材と物理的に接する、請求項11に記載のファン−アウト半導体パッケージモジュール。
- 前記半導体チップと前記第1及び第2受動部品は互いに並んで配置され、
前記連結部材の前記再配線層を介して互いに電気的に連結される、請求項2、3、または、請求項2に従属する場合の請求項4から12のいずれか一項、に記載のファン−アウト半導体パッケージモジュール。 - 前記連結部材は、前記接続パッド、前記第1受動部品、及び前記第2受動部品を前記再配線層とそれぞれ連結するビアをさらに含み、
前記接続パッド、前記第1受動部品、及び前記第2受動部品はそれぞれ、前記ビアと物理的に接する、請求項13に記載のファン−アウト半導体パッケージモジュール。 - 前記半導体チップは電力管理集積回路(PMIC)を含み、
前記第1及び第2受動部品はそれぞれキャパシタを含む、請求項2、3、または、請求項2に従属する場合の請求項4から14のいずれか一項、に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材は、前記第1及び第2貫通孔と離隔している第3貫通孔をさらに有し、
前記第3貫通孔内には第3受動部品が配置され、
前記第1封止材は、前記第3受動部品の少なくとも一部を覆い、前記第3貫通孔内の少なくとも一部を満たし、
前記再配線層は、前記第3受動部品と電気的に連結される、請求項2から15のいずれか一項に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材は、前記連結部材と接する第1絶縁層と、前記連結部材と接し、前記第1絶縁層に埋め込まれた第1配線層と、前記第1絶縁層において前記第1配線層が埋め込まれた側の反対側に配置された第2配線層と、を含み、
前記第1及び第2配線層は、前記接続パッドと電気的に連結される、請求項1から16のいずれか一項に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材は、前記第1絶縁層上に配置され、前記第2配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、をさらに含み、
前記第3配線層は、前記接続パッドと電気的に連結される、請求項17に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材は、第1絶縁層と、前記第1絶縁層の両面に配置された第1配線層及び第2配線層と、を含み、
前記第1及び第2配線層は、前記接続パッドと電気的に連結される、請求項1から16のいずれか一項に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材は、前記第1絶縁層上に配置され、前記第1配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、前記第1絶縁層上に配置され、前記第2配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4配線層と、をさらに含み、
前記第3及び第4配線層は、前記接続パッドと電気的に連結される、請求項19に記載のファン−アウト半導体パッケージモジュール。 - 第1及び第2貫通孔を有するコア部材と、
前記コア部材上に配置され、前記コア部材の前記第1貫通孔上に配置される第1貫通孔を有し、前記コア部材の前記第2貫通孔を覆う補強層と、
前記第1貫通孔内に配置された第1部品と、
前記第2貫通孔内に配置された第2部品と、
前記第1部品及び前記補強層のそれぞれの少なくとも一部を覆う封止材と、を含む、ファン−アウト半導体パッケージモジュール。 - 前記封止材は、前記コア部材、前記第2部品、及び前記コア部材の前記第2貫通孔を覆う第1封止材と、前記補強層、前記第1部品、前記補強層の前記第1貫通孔、及び前記コア部材の前記第1貫通孔を覆う第2封止材と、を含む、請求項21に記載のファン−アウト半導体パッケージモジュール。
- 前記第1部品は前記コア部材よりも厚く、
前記第2部品は前記コア部材よりも薄い、請求項21または22に記載のファン−アウト半導体パッケージモジュール。 - 前記コア部材の前記第1貫通孔は前記コア部材の前記第2貫通孔と離隔しており、
前記コア部材は、前記コア部材の前記第1及び第2貫通孔の間に配置される金属層を含む、請求項21から23のいずれか一項に記載のファン−アウト半導体パッケージモジュール。
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US10804188B2 (en) | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
US10755994B2 (en) * | 2018-10-29 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor substrate |
US11075260B2 (en) * | 2018-10-31 | 2021-07-27 | Qualcomm Incorporated | Substrate comprising recessed interconnects and a surface mounted passive component |
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US11876085B2 (en) | 2021-06-25 | 2024-01-16 | Qualcomm Incorporated | Package with a substrate comprising an embedded capacitor with side wall coupling |
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JP3798597B2 (ja) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
US6972964B2 (en) * | 2002-06-27 | 2005-12-06 | Via Technologies Inc. | Module board having embedded chips and components and method of forming the same |
US20040012097A1 (en) * | 2002-07-17 | 2004-01-22 | Chien-Wei Chang | Structure and method for fine pitch flip chip substrate |
EP1848029B1 (en) | 2006-04-18 | 2017-01-11 | Unimicron Technology Corp. | Carrying structure of electronic components |
JP2011061004A (ja) | 2009-09-10 | 2011-03-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
WO2012077522A1 (ja) | 2010-12-10 | 2012-06-14 | 株式会社村田製作所 | 回路モジュール |
WO2013054504A1 (ja) * | 2011-10-13 | 2013-04-18 | 住友ベークライト株式会社 | 半導体パッケージおよび半導体装置 |
US8890628B2 (en) | 2012-08-31 | 2014-11-18 | Intel Corporation | Ultra slim RF package for ultrabooks and smart phones |
US9245137B2 (en) * | 2013-03-04 | 2016-01-26 | International Business Machines Corporation | Management of digital information |
US9627338B2 (en) * | 2013-03-06 | 2017-04-18 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming ultra high density embedded semiconductor die package |
KR20150009826A (ko) * | 2013-07-17 | 2015-01-27 | 삼성전자주식회사 | 소자 내장형 패키지 기판 및 이를 포함하는 반도체 패키지 |
US9240392B2 (en) * | 2014-04-09 | 2016-01-19 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd. | Method for fabricating embedded chips |
US9696199B2 (en) | 2015-02-13 | 2017-07-04 | Taiwan Biophotonic Corporation | Optical sensor |
US9576910B2 (en) * | 2015-03-11 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor packaging structure and manufacturing method thereof |
US9806063B2 (en) * | 2015-04-29 | 2017-10-31 | Qualcomm Incorporated | Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability |
US10199337B2 (en) * | 2015-05-11 | 2019-02-05 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
KR101999625B1 (ko) | 2016-03-25 | 2019-07-17 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10276467B2 (en) | 2016-03-25 | 2019-04-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
KR20170112363A (ko) | 2016-03-31 | 2017-10-12 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
US10373884B2 (en) | 2016-03-31 | 2019-08-06 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package for packaging semiconductor chip and capacitors |
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