JP6541080B2 - 固体撮像装置 - Google Patents
固体撮像装置 Download PDFInfo
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- JP6541080B2 JP6541080B2 JP2017133675A JP2017133675A JP6541080B2 JP 6541080 B2 JP6541080 B2 JP 6541080B2 JP 2017133675 A JP2017133675 A JP 2017133675A JP 2017133675 A JP2017133675 A JP 2017133675A JP 6541080 B2 JP6541080 B2 JP 6541080B2
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- 238000003384 imaging method Methods 0.000 title claims description 79
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- 239000004065 semiconductor Substances 0.000 claims description 105
- 238000002955 isolation Methods 0.000 claims description 79
- 230000003321 amplification Effects 0.000 claims description 69
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 69
- 238000006243 chemical reaction Methods 0.000 claims description 58
- 238000003860 storage Methods 0.000 claims description 21
- 238000000926 separation method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 description 46
- 150000002500 ions Chemical class 0.000 description 30
- 230000015572 biosynthetic process Effects 0.000 description 25
- 239000010410 layer Substances 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 22
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- 238000009792 diffusion process Methods 0.000 description 18
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- 230000000875 corresponding effect Effects 0.000 description 10
- 230000006866 deterioration Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- 238000009825 accumulation Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
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- 230000001276 controlling effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 241000519995 Stachys sylvatica Species 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- 238000011065 in-situ storage Methods 0.000 description 1
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Description
このようにすると、リセットトランジスタのしきい値電圧を高く設定して、オフリークを低減することができるため、FDリークを減らすことが可能となる。これに対し、増幅トランジスタのしきい値電圧を低く設定することができるので、飽和領域で確実に駆動させることが可能となる。
図1は第1の実施形態に係る固体撮像装置の回路構成を示している。
以下、前記のように構成された第1の実施形態に係る固体撮像装置の製造方法について、図6(a)〜図6(d)を参照しながらその概略を説明する。
以下、第2の実施形態に係る固体撮像装置について図7を参照しながら説明する。
以下、第2の実施形態の一変形例に係る固体撮像装置について図8を参照しながら説明する。
2A、2B、2C ゲート絶縁膜
3A、3B、3C ゲート電極
4、4A、4B、4C チャネル領域
5 画素電極
6 光電変換膜
7 透明電極
8 コンタクトプラグ
9 光電変換部
10 増幅トランジスタ
11 リセットトランジスタ
12 アドレストランジスタ
13 単位画素セル
14A、14B、14C 層間絶縁膜
15 垂直走査部
16 光電変換部制御線
17 垂直信号線
18 負荷部
19 カラム信号処理部
20 水平信号読み出し部
21 電源配線
22 第1の活性領域
23 差動増幅器
24 フィードバック線
25 第2活性領域
26A、26B、26C 配線
27 リセット信号線
28 アドレス信号線
29 リセットトランジスタドレイン周辺領域
30A、30B、30C プラグ
31 素子分離領域
40A、40B、40C、40D、40E n型不純物領域
Claims (15)
- 第1導電型の半導体領域と、
複数の単位画素セルとを備え、
前記単位画素セルは、
電荷を生成する光電変換部と、
前記光電変換部からの電荷を蓄積する蓄積ダイオードを前記半導体領域との間で形成する第2導電型の不純物領域と、
前記不純物領域と電気的に接続されたゲート電極を有する増幅トランジスタと、
前記半導体領域に位置し、前記増幅トランジスタを囲み、前記第1導電型の不純物を含む第1分離領域とを有し、
前記増幅トランジスタは、前記半導体領域に位置する前記第2導電型のソース領域及び前記第2導電型のドレイン領域と、前記半導体領域における前記ゲート電極の下側に形成されたチャネル領域とを有し、
前記第1分離領域は、ゲート幅方向に垂直な第1面と、前記第1面と対向する第2面と、前記ゲート幅方向に垂直な第3面と、前記第3面と対向する第4面と、前記ゲート幅方向に垂直な第5面と、前記第5面と対向する第6面と、を有し、
前記第1面と前記第2面との間に前記チャネル領域が位置し、前記第3面と前記第4面との間に前記ソース領域が位置し、前記第5面と前記第6面との間に前記ドレイン領域が位置し、
前記第1面と前記第2面との距離は、前記第3面と前記第4面との距離よりも大きく、且つ、前記第5面と前記第6面との距離よりも大きい、固体撮像装置。 - 前記チャネル領域のゲート幅方向の幅は、前記ソース領域のゲート幅方向の幅よりも大きく、且つ、前記ドレイン領域のゲート幅方向の幅よりも大きい、請求項1に記載の固体撮像装置。
- 第1導電型の半導体領域と、
複数の単位画素セルとを備え、
前記単位画素セルは、
電荷を生成する光電変換部と、
前記光電変換部からの電荷を蓄積する蓄積ダイオードを前記半導体領域との間で形成する第2導電型の不純物領域と、
前記不純物領域と電気的に接続されたゲート電極を有する増幅トランジスタと、
前記半導体領域に位置し、前記増幅トランジスタを囲み、前記第1導電型の不純物を含む第1分離領域とを有し、
前記増幅トランジスタは、前記半導体領域に位置する前記第2導電型のソース領域及び前記第2導電型のドレイン領域と、前記半導体領域における前記ゲート電極の下側に形成されたチャネル領域とを有し、
前記チャネル領域のゲート幅方向の幅は、前記ソース領域のゲート幅方向の幅よりも大きく、且つ、前記ドレイン領域のゲート幅方向の幅よりも大きい、
固体撮像装置。 - 前記単位画素セルは、
前記増幅トランジスタのゲート電極の電位をリセットするリセットトランジスタを有し、
前記増幅トランジスタのチャネル領域は、前記第1導電型の不純物からなり、且つ、
前記リセットトランジスタのチャネル領域は、前記第1導電型の不純物からなる、請求項1〜3のいずれか1項に記載の固体撮像装置。 - 前記単位画素セルは、
前記増幅トランジスタのゲート電極の電位をリセットするリセットトランジスタを有し、
前記増幅トランジスタのチャネル領域は、前記第2導電型の不純物からなり、一方、
前記リセットトランジスタのチャネル領域は、前記第1導電型の不純物からなる、請求項1〜3のいずれか1項に記載の固体撮像装置。 - 前記第1分離領域は、前記不純物領域を囲む、請求項1〜5のいずれか1項に記載の固体撮像装置。
- 第1導電型の半導体領域と、
複数の単位画素セルとを備え、
前記単位画素セルは、
電荷を生成する光電変換部と、
前記光電変換部からの電荷を蓄積する蓄積ダイオードを前記半導体領域との間で形成する第2導電型の不純物領域と、
その一方が前記不純物領域である、前記第2導電型のソース領域及び前記第2導電型のドレイン領域と、ゲート電極と、前記半導体領域における前記ゲート電極の下方に位置するチャネル領域とを含むリセットトランジスタと、
前記半導体領域に位置し、前記リセットトランジスタを囲み、且つ、前記第1導電型の不純物を含む第1分離領域とを有し、
前記第1分離領域は、ゲート幅方向に垂直な第1面と、前記第1面と対向する第2面と、前記ゲート幅方向に垂直な第3面と、前記第3面と対向する第4面と、前記ゲート幅方向に垂直な第5面と、前記第5面と対向する第6面と、を有し、
前記第1面と前記第2面との間に前記チャネル領域が位置し、前記第3面と前記第4面との間に前記ソース領域が位置し、前記第5面と前記第6面との間に前記ドレイン領域が位置し、
前記第1面と前記第2面との距離は、前記第3面と前記第4面との距離よりも大きく、且つ、前記第5面と前記第6面との距離よりも大きい、
固体撮像装置。 - 前記チャネル領域のゲート幅方向の幅は、前記ソース領域のゲート幅方向の幅よりも大きく、且つ、前記ドレイン領域のゲート幅方向の幅よりも大きい、請求項7に記載の固体撮像装置。
- 第1導電型の半導体領域と、
複数の単位画素セルとを備え、
前記単位画素セルは、
電荷を生成する光電変換部と、
前記光電変換部からの電荷を蓄積する蓄積ダイオードを前記半導体領域との間で形成する第2導電型の不純物領域と、
前記不純物領域であるソース領域及びドレイン領域と、ゲート電極と、前記半導体領域における前記ゲート電極の下方に位置するチャネル領域とを含むリセットトランジスタと、
前記半導体領域に位置し、前記リセットトランジスタを囲み、且つ、前記第1導電型の不純物を含む第1分離領域とを有し、
前記チャネル領域のゲート幅方向の幅は、前記ソース領域のゲート幅方向の幅よりも大きく、且つ、前記ドレイン領域のゲート幅方向の幅よりも大きい、
固体撮像装置。 - 前記第1面と、前記ゲート電極の幅方向の端面とが同一の面上に位置する、請求項1、2、7及び8のいずれか1項に記載の固体撮像装置。
- 前記第1導電型の不純物を含み、隣り合う前記単位画素セル同士を電気的に分離する第2分離領域を備え、
前記第2分離領域は、前記半導体領域に位置し、
前記第1分離領域の不純物濃度は、前記半導体領域の不純物濃度よりも高い、請求項1〜10のいずれか1項に記載の固体撮像装置。 - 前記第1分離領域の不純物濃度と、前記第2分離領域の不純物濃度とは同一である、請求項11に記載の固体撮像装置。
- 前記第1分離領域は、前記ゲート電極の下方に位置しない、請求項6に記載の固体撮像装置。
- 前記チャネル領域の全体は、前記ゲート電極の下方に位置する、請求項6に記載の固体撮像装置。
- 前記第1面と前記第2面との距離は、前記ゲート幅方向における、前記ゲート電極と前記ソース領域との境界、又は前記ゲート電極と前記ドレイン領域との境界の距離よりも大きい、請求項1に記載の固体撮像装置。
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