JP6355541B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6355541B2 JP6355541B2 JP2014246296A JP2014246296A JP6355541B2 JP 6355541 B2 JP6355541 B2 JP 6355541B2 JP 2014246296 A JP2014246296 A JP 2014246296A JP 2014246296 A JP2014246296 A JP 2014246296A JP 6355541 B2 JP6355541 B2 JP 6355541B2
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- rewiring
- film
- semiconductor device
- pad electrode
- opening
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本実施の形態の半導体装置(半導体集積回路装置)は、例えば複数の半導体素子と、複数の半導体素子の上部に形成された複数層の配線(多層配線)と、複数層の内の最上層の配線に接続された複数の再配線を有する半導体チップを有し、複数の半導体素子は前記多層配線または複数の再配線により接続される。本実施の形態の半導体装置1Aについて説明する。
図1は、本実施の形態である半導体装置の要部平面図である。図2は、図1のA−A線に沿う要部断面図であり、図3は、図1のB−B線に沿う要部断面図である。
以下に、本実施の形態の半導体装置1Aの主な特徴を説明する。
次に、本実施の形態である半導体装置1Aの製造方法について説明するが、本実施の形態の特徴である再配線の製造方法を中心に説明する。再配線の製造方法は、図2に示した断面に対応している。
以下に、本実施の形態の半導体装置1Aの製造方法の主な特徴を説明する。
図11は、本実施の形態の変形例1である半導体装置の製造工程の一部を示すプロセスフロー図である。図12〜14は、変形例1の半導体装置の製造工程中の要部断面図である。本実施の形態の半導体装置1Aと区別するために、変形例1では半導体装置1Bとするが、本実施の形態と共通する部分には同様の符号を付してその説明も省略する。
図15は、本実施の形態の変形例2である半導体装置の製造工程の一部を示すプロセスフロー図である。図16および図17は、変形例2の半導体装置の製造工程中の要部断面図である。本実施の形態の半導体装置1Aと区別するために、変形例2では半導体装置1Cとするが、本実施の形態と共通する部分には同様の符号を付してその説明も省略する。
図18は、本実施の形態の変形例3である半導体装置の要部平面図である。図19は、図18のC−C線に沿う要部断面図である。本実施の形態の半導体装置1Aと区別するために、変形例3では半導体装置1Dとするが、本実施の形態と共通する部分には同様の符号を付してその説明も省略する。
PR1、PR2、PR3 フォトレジスト膜
p1、p2、p3 プラグ
Qn nチャネル型MISFET
Qp pチャネル型MISFET
RM 再配線
RM1 シード膜
RM2 メッキ膜
UM 下地金属膜
1A、1B、1C、1D 半導体装置
1P 半導体基板
2P p型ウエル
2N n型ウエル
3 素子分離溝
3a 素子分離絶縁膜
4,6,8 層間絶縁膜
5、7、9 Al配線
9a パッド電極
10 表面保護膜
10a パッド開口
11 下地絶縁膜
11a 開口
12 保護膜
12a 外部パッド開口
13 外部パッド電極
13a ボール接続部
13b 突出部
14 コンタクト金属膜
15 防錆膜
25D ダイパッド部
25L リード
26 封止体
27 ワイヤ
27a ボール部
Claims (14)
- 半導体基板と、
前記半導体基板上に形成された複数の配線層と、
前記複数の配線層の最上層に形成されたパッド電極と、
前記パッド電極上に第1開口を有する絶縁膜と、
前記パッド電極に電気的に接続され、前記絶縁膜上に延在する再配線と、
前記再配線の上面を覆い、前記再配線の前記上面の一部を露出する第2開口を有する保護膜と、
前記第2開口において、前記再配線に電気的に接続され、前記保護膜上に延在する外部パッド電極と、
前記外部パッド電極に接続されたワイヤと、
を有し、
平面視において、前記外部パッド電極の一部は、前記再配線の外側の領域に位置し、
前記ワイヤは、前記外部パッド電極に接続されたボール部を有し、
平面視において、前記ボール部の一部は、前記再配線の外側の領域に位置する、半導体装置。 - 請求項1に記載の半導体装置において、さらに、
前記絶縁膜上に形成され、前記再配線に隣り合って配置された隣接再配線と、
を有し、
平面視において、前記ボール部は、前記再配線と前記隣接再配線との間の、前記絶縁膜と重なる、半導体装置。 - 請求項1に記載の半導体装置において、
前記絶縁膜または保護膜は有機膜からなる、半導体装置。 - 請求項3に記載の半導体装置において、
前記有機膜は、ヤング率が6GPa以下で、膜厚が0.5μm以上である、半導体装置。 - 請求項4に記載の半導体装置において、
前記有機膜はポリイミド樹脂膜である、半導体装置。 - 請求項1に記載の半導体装置において、
前記外部パッド電極の膜厚は、前記再配線の膜厚よりも薄い、半導体装置。 - 請求項1に記載の半導体装置において、
前記外部パッド電極は、前記ワイヤが接続されるボール接続部と、前記ボール接続部から延び、前記再配線と接続される突出部と、
を有し、
平面視における、前記再配線の延在方向と直交する方向において、前記ボール接続部の幅は、前記再配線の幅よりも広い、半導体装置。 - 請求項1に記載の半導体装置において、さらに、
前記第2開口において、前記再配線と前記外部パッド電極間に配置されたコンタクト金属膜を有する、半導体装置。 - 請求項1に記載の半導体装置において、さらに、
前記再配線の上面および側面を覆うキャップ金属膜を有する、半導体装置。 - (a)複数の配線層と、前記複数の配線層の最上層に形成されたパッド電極とを有する半導体基板を準備する工程、
(b)前記パッド電極上に第1開口を有する第1絶縁膜を形成する工程、
(c)前記第1絶縁膜上に延在し、前記第1開口を介して前記パッド電極に電気的に接続する再配線を形成する工程、
(d)前記再配線の上面を覆い、前記再配線の前記上面の一部を露出する第2開口を有する第2絶縁膜を形成する工程、
(e)前記第2開口において、前記再配線に電気的に接続され、前記第2絶縁膜上に延在する外部パッド電極を形成する工程、
(f)前記外部パッド電極にワイヤを接続する工程、
を有し、
前記ワイヤは、前記外部パッド電極に接続されたボール部を有し、
平面視において、前記ボール部の一部は、前記再配線の外側の領域に位置する、半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、前記工程(c)と(d)の間に、
(g)前記再配線の上面の一部にコンタクト金属膜を形成する工程、を有する、半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、前記工程(c)と(d)の間に、
(h)前記再配線の上面および側面をキャップ金属膜で被覆する工程、を有する、半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、前記工程(c)と(d)の間に、
(i)前記再配線の上面および側面を絶縁性の防錆膜で被覆する工程、を有する、半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記再配線はメッキ法で形成し、前記外部パッド電極はスパッタ法で形成する、半導体装置の製造方法。
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JP2014246296A JP6355541B2 (ja) | 2014-12-04 | 2014-12-04 | 半導体装置およびその製造方法 |
TW104132832A TW201622107A (zh) | 2014-12-04 | 2015-10-06 | 半導體裝置及其製造方法 |
US14/952,468 US9576921B2 (en) | 2014-12-04 | 2015-11-25 | Semiconductor device and manufacturing method for the same |
CN201520996498.1U CN205177838U (zh) | 2014-12-04 | 2015-12-03 | 半导体器件 |
CN201510884600.3A CN105679730A (zh) | 2014-12-04 | 2015-12-03 | 半导体器件及其制造方法 |
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- 2015-10-06 TW TW104132832A patent/TW201622107A/zh unknown
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US20160163666A1 (en) | 2016-06-09 |
US9576921B2 (en) | 2017-02-21 |
JP2016111154A (ja) | 2016-06-20 |
CN205177838U (zh) | 2016-04-20 |
CN105679730A (zh) | 2016-06-15 |
TW201622107A (zh) | 2016-06-16 |
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