JP6280913B2 - 特別仕様の端子を収容するための充填ビアを有する配線基板 - Google Patents
特別仕様の端子を収容するための充填ビアを有する配線基板 Download PDFInfo
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- JP6280913B2 JP6280913B2 JP2015505895A JP2015505895A JP6280913B2 JP 6280913 B2 JP6280913 B2 JP 6280913B2 JP 2015505895 A JP2015505895 A JP 2015505895A JP 2015505895 A JP2015505895 A JP 2015505895A JP 6280913 B2 JP6280913 B2 JP 6280913B2
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- 239000000523 sample Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004020 conductor Substances 0.000 claims description 24
- 238000012360 testing method Methods 0.000 claims description 19
- 239000012777 electrically insulating material Substances 0.000 claims description 16
- 239000011810 insulating material Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004891 communication Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
Claims (20)
- 配線基板の第1表面上に特別仕様の導電性端子を設けるプロセスであって、前記配線基板は前記第1表面から該配線基板の反対表面まで複数の導電性ビアを備え、前記プロセスは、
前記複数のビアのうち第1ビアにおいて、前記第1表面から前記配線基板内へ孔を形成し、それにより前記第1表面から前記配線基板内までの間隙内にある前記第1ビアの全ての導電性材料を除去することと、
前記孔内に電気絶縁材料を堆積させることであって、前記電気絶縁材料は、全ての残存する前記第1ビアの導電性材料と前記配線基板の前記第1表面との間に配置されるように、堆積させることと、
前記特別仕様の端子が、前記第1ビアに電気的に接触することなく、前記第1ビアと、前記複数のビアのうち前記第1ビアに隣接する第2ビアとを覆うように、前記配線基板の前記第1表面および前記絶縁材料上に、前記特別仕様の端子を設けることと、を含む、プロセス。 - 前記特別仕様の端子は、前記第1ビア、前記第2ビア、および前記複数のビアのうちの第3ビアを覆う、請求項1に記載のプロセス。
- 前記特別仕様の端子は、前記第2ビアのみに電気的に接続される、請求項2に記載のプロセス。
- 前記第3ビアにおいて、前記第1表面から前記配線基板内へと第2の孔を形成し、それにより前記第1表面から前記配線基板内までの第2間隙内にある前記第3ビアの全ての導電材料を除去することをさらに含む、請求項2に記載のプロセス。
- 前記第3ビアの残存する導電材料の全てと前記配線基板の前記第1表面との間に前記電気絶縁材料が配置されるように、前記電気絶縁材料を前記第2の孔内に堆積することをさらに含む、請求項4に記載のプロセス。
- 前記配線基板を電子デバイスの試験において使用することをさらに含む、請求項1に記載のプロセス。
- 配線基板上に特別仕様の導電性端子を設けるプロセスであって、
複数の導電性ビアを第1表面と第2表面との間に有する配線基板を提供することと、
前記複数のビアのうちの第1ビアにおいて、前記第1表面と前記配線基板内のある深さとの間の全ての導電性材料を除去することによって、前記第1表面から前記配線内へと孔を形成し、それにより前記第1ビアと前記第1表面との間に間隙を形成することと、
前記特別仕様の端子が、前記第1ビアと、前記複数のビアのうち前記第1ビアに隣接する第2ビアとを覆うように、前記配線基板の前記第1表面上に前記特別仕様の端子を設けることと、を含む、
プロセス。 - 前記間隙内に電気絶縁材料を堆積することをさらに含む、請求項7に記載のプロセス。
- 前記堆積することは、前記間隙に前記電気絶縁材料を充填することをさらに含む、請求項8に記載のプロセス。
- 前記特別仕様の端子は、前記第1ビア、前記第2ビア、および前記複数のビアのうちの第3ビアを覆う、請求項7記載のプロセス。
- 前記特別仕様の端子は、前記第2ビアのみに電気的に接続される、請求項7に記載のプロセス。
- 前記第3ビアにおいて、前記第1表面から前記配線基板内へと第2の孔を形成し、それにより前記第1表面から前記配線基板内までの第2間隙内にある前記第3ビアの全ての導電材料を除去することをさらに含む、請求項10に記載のプロセス。
- 前記第3ビアの残存する導電材料の全てと前記配線基板の前記第1表面との間に前記電気絶縁材料が配置されるように、前記電気絶縁材料を前記第2の孔内に堆積することをさらに含む、請求項12に記載のプロセス。
- 前記配線基板を電子デバイスの試験において使用することをさらに含む、請求項7に記載のプロセス。
- プローブ基板から延在し、かつ試験対象の電子デバイスの端子に接触するように配置される導電性プローブと、
前記電子デバイスの試験を制御するためのテスタへの電気的インタフェースを備える配線基板と、を備えたプローブカードアセンブリであって、
前記インタフェースは前記プローブに電気的に接続され、
前記配線基板は、
第1表面および反対表面と、
前記反対表面から前記配線基板内に延在し、前記第1表面に至る前に終了する導電性材料を含む導電性第1ビアと、
それぞれが前記第1表面から前記反対表面へ導電性を有する複数の導電性第2ビアと、
前記第1表面上に配置される特別仕様の導電性端子であって、前記特別仕様の導電性端子が前記第1ビアを被覆し、かつ前記第1ビアに電気的に接触することなく前記第1ビアに隣接する前記第2ビアのうちの1つに接触するように配置される、導電性端子と、を備える、
プローブカードアセンブリ。 - 前記第1ビアにおいて孔内に配置される電気絶縁材料をさらに備え、前記孔は、前記第1ビアの前記導電性材料と前記第1表面との間に、前記第1表面から前記配線基板内へと延在する、請求項15に記載のプローブカードアセンブリ。
- 前記特別仕様の端子は、前記第1ビア、前記第2ビアの1つ、および第3の導電性ビアを覆う、請求項15に記載のプローブカードアセンブリ。
- 前記特別仕様の端子は、前記第2ビアのうちの1つのみに電気的に接続される、請求項17に記載のプローブカードアセンブリ。
- 前記第3ビアに第2の孔をさらに備える、請求項17に記載のプローブカードアセンブリ。
- 前記第2の孔は、前記第2の孔内に配置された電気絶縁材料を含む、請求項19に記載のプローブカードアセンブリ。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261624205P | 2012-04-13 | 2012-04-13 | |
US61/624,205 | 2012-04-13 | ||
US13/856,091 | 2013-04-03 | ||
US13/856,091 US9523715B2 (en) | 2012-04-13 | 2013-04-03 | Wiring substrate with filled vias to accommodate custom terminals |
PCT/US2013/036092 WO2013155256A1 (en) | 2012-04-13 | 2013-04-11 | Wiring substrate with filled vias to accommodate custom terminals |
Publications (2)
Publication Number | Publication Date |
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JP2015528097A JP2015528097A (ja) | 2015-09-24 |
JP6280913B2 true JP6280913B2 (ja) | 2018-02-14 |
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JP2015505895A Active JP6280913B2 (ja) | 2012-04-13 | 2013-04-11 | 特別仕様の端子を収容するための充填ビアを有する配線基板 |
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Country | Link |
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US (2) | US9523715B2 (ja) |
JP (1) | JP6280913B2 (ja) |
TW (1) | TWI601458B (ja) |
WO (1) | WO2013155256A1 (ja) |
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KR102192569B1 (ko) * | 2015-11-06 | 2020-12-17 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
US9941652B2 (en) * | 2015-12-17 | 2018-04-10 | Intel Corporation | Space transformer with perforated metallic plate for electrical die test |
US10978590B2 (en) | 2016-09-30 | 2021-04-13 | Intel Corporation | Methods and apparatus to remove epitaxial defects in semiconductors |
TWI679424B (zh) * | 2019-03-29 | 2019-12-11 | 矽品精密工業股份有限公司 | 檢測裝置及其製法 |
TWI799834B (zh) * | 2020-05-22 | 2023-04-21 | 南韓商李諾工業股份有限公司 | 測試座以及其製造方法 |
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-
2013
- 2013-04-03 US US13/856,091 patent/US9523715B2/en active Active
- 2013-04-11 TW TW102112852A patent/TWI601458B/zh not_active IP Right Cessation
- 2013-04-11 WO PCT/US2013/036092 patent/WO2013155256A1/en active Application Filing
- 2013-04-11 JP JP2015505895A patent/JP6280913B2/ja active Active
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2016
- 2016-11-16 US US15/353,324 patent/US9869697B2/en active Active
Also Published As
Publication number | Publication date |
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US20130271175A1 (en) | 2013-10-17 |
US9523715B2 (en) | 2016-12-20 |
TW201352093A (zh) | 2013-12-16 |
TWI601458B (zh) | 2017-10-01 |
US9869697B2 (en) | 2018-01-16 |
WO2013155256A1 (en) | 2013-10-17 |
US20170067937A1 (en) | 2017-03-09 |
JP2015528097A (ja) | 2015-09-24 |
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