JP6108037B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP6108037B2
JP6108037B2 JP2016537686A JP2016537686A JP6108037B2 JP 6108037 B2 JP6108037 B2 JP 6108037B2 JP 2016537686 A JP2016537686 A JP 2016537686A JP 2016537686 A JP2016537686 A JP 2016537686A JP 6108037 B2 JP6108037 B2 JP 6108037B2
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recess
semiconductor device
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JPWO2016017007A1 (ja
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みさと 久野
みさと 久野
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Mitsubishi Electric Corp
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Description

本発明は、Ｓｉ基板の裏面に金属電極を形成する半導体装置の製造方法に関する。
大電流を駆動させるための電力用半導体装置においてＳｉ基板の裏面に金属電極を形成する（例えば、特許文献１参照）。Ｓｉ基板と金属電極の剥離を抑制するために両者の間にＡｌ−Ｓｉ膜を形成する。
日本特開２００６−０７４０２４号公報
ウエハ製造時の機械的ストレスによりＳｉ基板の裏面に凹部が形成される。この凹部を介してＡｌ−Ｓｉ膜からＳｉ基板にＡｌが拡散してｐ型層が形成される。このｐ型層に空乏層が到達するため、リーク電流が発生し、デバイスの耐圧が劣化するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的はＳｉ基板の裏面に凹部が存在してもリーク電流と耐圧劣化を抑制することができる半導体装置の製造方法を得るものである。
本発明に係る半導体装置は、凹部が形成された裏面を有するＳｉ基板の前記裏面にｎ型不純物を注入してｎ型層を形成する工程と、前記ｎ型層を形成した後に前記裏面上と前記凹部内に保護膜を形成する工程と、前記凹部内の前記保護膜を残しつつ前記裏面上の前記保護膜を除去する工程と、前記保護膜を除去した後に前記裏面上にＡｌ−Ｓｉ膜を形成する工程と、前記Ａｌ−Ｓｉ膜上に金属電極を形成する工程とを備え、前記凹部内の前記保護膜は、前記Ａｌ−Ｓｉ膜から前記凹部を介して前記Ｓｉ基板にＡｌが拡散するのを防ぐことを特徴とする。
本発明では、凹部内の保護膜がＡｌ−Ｓｉ膜から凹部を介してＳｉ基板にＡｌが拡散するのを防ぐ。従って、Ｓｉ基板の裏面に凹部が存在してもリーク電流と耐圧劣化を抑制することができる。
本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。 比較例に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態２に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態３に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態４に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態５に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態６に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態６に係る半導体装置の製造方法を示す断面図である。 本発明の実施の形態６に係る半導体装置の製造方法の変型例を示す断面図である。
本発明の実施の形態に係る半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
本発明の実施の形態１に係る半導体装置の製造方法について図面を参照しながら説明する。図１〜４は、本発明の実施の形態１に係る半導体装置の製造方法を示す断面図である。
まず、図１に示すように、ｎ−型のＳｉ基板１の表面にｐ型不純物を注入してｐ型層２を形成し、裏面にｎ型不純物を注入してｎ型層３を形成する。Ｓｉ基板１の裏面には凹部４（傷）が形成されている。次に、図２に示すように、裏面上と凹部４内に酸化膜５を形成する。次に、図３に示すように、スパッタエッチングにより凹部４内の酸化膜５を残しつつ裏面上の酸化膜５を除去する。ここで、酸化膜５は少なくとも凹部４の最深部に残っている必要がある。次に、図４に示すように、裏面上にＡｌ−Ｓｉ膜６を形成する。次に、Ａｌ−Ｓｉ膜６上に金属電極７を形成する。なお、金属電極７は多層電極である。
続いて、本実施の形態の効果を比較例と比較して説明する。図５は比較例に係る半導体装置の製造方法を示す断面図である。比較例では凹部４の最深部においてＳｉ基板１に直接にＡｌ−Ｓｉ膜６が接する。このため、デバイスに逆方向の電圧を印加した際にＡｌ−Ｓｉ膜６から凹部４を介してＳｉ基板１にＡｌが拡散してｐ型層が形成される。このｐ型層に空乏層が到達するため、リーク電流が発生し、デバイスの耐圧が劣化する。
一方、本実施の形態では、凹部４内の酸化膜５がＡｌ−Ｓｉ膜６から凹部４を介してＳｉ基板１にＡｌが拡散するのを防ぐ保護膜として機能する。従って、Ｓｉ基板１の裏面に凹部４が存在してもリーク電流と耐圧劣化を抑制することができる。また、Ａｌ−Ｓｉ膜６によりＳｉ基板１と金属電極７の剥離を抑制することができる。
実施の形態２．
図６は、本発明の実施の形態２に係る半導体装置の製造方法を示す断面図である。本実施の形態では、実施の形態１の酸化膜５の代わりに保護膜としてｎ型ドープドポリシリコン８を形成する。この場合、凹部４内のｎ型ドープドポリシリコン８がＡｌ−Ｓｉ膜６から凹部４を介してＳｉ基板１にＡｌが拡散するのを防ぐため、実施の形態１と同様の効果を得ることができる。また、ｎ型ドープドポリシリコン８はｎ型なので、Ｓｉ基板１をｐ型に活性化させるＡｌに対してマージンがあり、凹部４でも通電できる。
実施の形態３．
図７は、本発明の実施の形態３に係る半導体装置の製造方法を示す断面図である。本実施の形態では、実施の形態１の酸化膜５の代わりに保護膜としてリン化酸化膜ガラス９を形成する。この場合でも実施の形態１と同様の効果を得ることができる。また、リン化酸化膜ガラス９はｎ型なので、実施の形態２と同様に、Ｓｉ基板１をｐ型に活性化させるＡｌに対してマージンがあり、凹部４でも通電できる。
実施の形態４．
図８は、本発明の実施の形態４に係る半導体装置の製造方法を示す断面図である。本実施の形態では、実施の形態１の酸化膜５の代わりに保護膜としてシリサイド化しない単体メタル１０（チタン）を形成する。凹部４内の単体メタル１０はＡｌの拡散を防ぐバリアメタルとして作用するため、実施の形態１と同様の効果を得ることができる。また、単体メタル１０はｎ型に対するオーミック性に優れている。
実施の形態５
図９は、本発明の実施の形態５に係る半導体装置の製造方法を示す断面図である。本実施の形態では、ｎ型層３を形成した後に裏面上と凹部４内に金属膜（チタン、コバルト、タングステン、モリブデン）を形成する。その後に、アニールを施すことによって、金属シリサイド１１（チタンシリサイド、コバルトシリサイド、タングステンシリサイド、モリブデンシリサイド）を形成する。次に、スパッタエッチングにより凹部４内の金属シリサイド１１を残しつつ裏面上の金属シリサイド１１を除去する。その後、実施の形態１と同様にＡｌ−Ｓｉ膜６と金属電極７を形成する。
凹部４内の金属シリサイド１１がＡｌ−Ｓｉ膜６から凹部４を介してＳｉ基板１にＡｌが拡散するのを防ぐ保護膜として機能するため、実施の形態１と同様の効果を得ることができる。また、金属シリサイド１１は単体メタル１０よりもｎ型のｎ型層３に対するオーミック性に優れ、Ａｌの拡散を防ぐバリアメタルとして作用する。
実施の形態６
図１０，１１は、本発明の実施の形態６に係る半導体装置の製造方法を示す断面図である。まず、実施の形態１の図１と同様にｎ−型のＳｉ基板１の表面にｐ型不純物を注入してｐ型層２を形成し、裏面にｎ型不純物を注入してｎ型層３を形成する。Ｓｉ基板１の裏面には凹部４が形成されている。次に、図１０に示すように、裏面にレーザーアニールを施して凹部４を残したままで裏面を再結晶化し、ｎ型層３を再形成する。次に、図１１に示すように、裏面上にＡｌ−Ｓｉ膜６を形成する。Ａｌ−Ｓｉ膜６上に金属電極７を形成する。
これによりＡｌ−Ｓｉ膜６から凹部４を介してＳｉ基板１にＡｌが拡散するのを防ぐことができるため、実施の形態１と同様の効果を得ることができる。また、ｎ型層３を再形成することができるため、特性変化を抑制することができる。また、レーザー照射で裏面を溶融させて凹部４を消失させる方法では処理時間が長くなるが、本実施の形態では凹部４を残すことでレーザーアニールの処理時間を短くすることができるため、コストを低減することができる。
図１２は、本発明の実施の形態６に係る半導体装置の製造方法の変型例を示す断面図である。レーザーアニールを凹部４のみに選択的に施す。これにより、凹部４付近を再結晶化することがきるため、実施の形態６の効果を得ることができる。また、レーザーアニールを選択的に施すことで、レーザーアニールの処理時間を更に短縮できるため、コストを低減することができる。
１ Ｓｉ基板、３ ｎ型層、４ 凹部、５ 酸化膜、６ Ａｌ−Ｓｉ膜、７ 金属電極、８ ｎ型ドープドポリシリコン、９ リン化酸化膜ガラス、１０ 単体メタル、１１ 金属シリサイド

Claims (7)

  1. 凹部が形成された裏面を有するＳｉ基板の前記裏面にｎ型不純物を注入してｎ型層を形成する工程と、
    前記ｎ型層を形成した後に前記裏面上と前記凹部内に保護膜を形成する工程と、
    前記凹部内の前記保護膜を残しつつ前記裏面上の前記保護膜を除去する工程と、
    前記保護膜を除去した後に前記裏面上にＡｌ−Ｓｉ膜を形成する工程と、
    前記Ａｌ−Ｓｉ膜上に金属電極を形成する工程とを備え、
    前記凹部内の前記保護膜は、前記Ａｌ−Ｓｉ膜から前記凹部を介して前記Ｓｉ基板にＡｌが拡散するのを防ぐことを特徴とする半導体装置の製造方法。
  2. 前記保護膜は酸化膜であることを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 前記保護膜はｎ型ドープドポリシリコン又はリン化酸化膜ガラスであることを特徴とする請求項１に記載の半導体装置の製造方法。
  4. 前記保護膜はシリサイド化しない金属であることを特徴とする請求項１に記載の半導体装置の製造方法。
  5. 前記保護膜は金属シリサイドであることを特徴とする請求項１に記載の半導体装置の製造方法。
  6. 凹部が形成された裏面を有するＳｉ基板の前記裏面にｎ型不純物を注入してｎ型層を形成する工程と、
    前記裏面にレーザーアニールを施して前記凹部を残したままで前記裏面を再結晶化し、前記ｎ型層を再形成する工程と、
    前記レーザーアニールの後に前記裏面上にＡｌ−Ｓｉ膜を形成する工程と、
    前記Ａｌ−Ｓｉ膜上に金属電極を形成する工程とを備えることを特徴とする半導体装置の製造方法。
  7. 前記レーザーアニールを前記凹部に選択的に施すことを特徴とする請求項６に記載の半導体装置の製造方法。
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