JP6100275B2 - 電気的絶縁層を持つマイクロled構造体及びマイクロled構造体のアレイの形成方法 - Google Patents
電気的絶縁層を持つマイクロled構造体及びマイクロled構造体のアレイの形成方法 Download PDFInfo
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- JP6100275B2 JP6100275B2 JP2014542347A JP2014542347A JP6100275B2 JP 6100275 B2 JP6100275 B2 JP 6100275B2 JP 2014542347 A JP2014542347 A JP 2014542347A JP 2014542347 A JP2014542347 A JP 2014542347A JP 6100275 B2 JP6100275 B2 JP 6100275B2
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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Description
本出願は、2012年2月13日に出願した米国特許出願第13/372,422号の一部継続出願であり、2011年11月18日に出願した米国仮特許出願第61/561,706号、2012年2月3日に出願した米国仮特許出願第61/594,919号、2012年2月9日に出願した米国仮特許出願第61/597,109号、2012年2月10日に出願した米国仮特許出願第61/597,658号に基づく優先権を主張し、これらの出願の全開示を参照により本願明細書に引用する。
P=[εo/2][Vεr/d]2−−−−−(1)
ここで、εo=8.85.10-12、Vはボルト(V)単位の電極−基板間の電圧、εrは誘電定数、dはメートル(m)単位の誘電体の厚さを示す。2つのグリップ電極を使用する2極型グリッパでは、上記式の電圧(V)は、電極Aと電極Bとの間の半分の電圧になる[VA−VB]/2。基板の電位は、平均電位[VA=VB]/2が中心となる。この平均値は、通常VA=[−VB]の場合はゼロになる。
P=[εo/2][Vεr/(d+εrg)]2−−−−−(2)
sqrt(P*2/εo)=Vεr/d−−−−−(3)
Claims (15)
- マイクロLEDアレイの形成方法であって、
接合層により第1の基板スタックを第2の基板スタックに接合する工程と、
第1の基板を除去する工程と、
p−nダイオード層をエッチング処理し、貫通し、複数の分離反射金属スタック上に複数のマイクロp−nダイオードを形成し、前記複数のマイクロp−nダイオード間に横方向に、パターン形成された電気的絶縁層を露出させる工程と、
前記p−nダイオード層のエッチング処理工程の後に、前記パターン形成された電気的絶縁層をエッチング処理して、前記複数のマイクロp−nダイオードそれぞれの底面の下から前記パターン形成された電気的絶縁層を除去する工程と、を含み、
前記第1の基板スタックは、前記第1の基板上に形成されたp−nダイオード層と、前記p−nダイオード層上の複数の分離反射金属化スタックと、前記p−nダイオード層上の前記複数の分離反射金属スタック間の横方向のパターン形成された電気的絶縁層と、を備えるものであり、
接合層により第1の基板スタックを第2の基板スタックに接合する前記工程は、前記パターン形成された電気的絶縁層の形状を前記接合層に組み込むことを含むものである、マイクロLEDアレイの形成方法。 - 前記第1の基板スタックは、前記パターン形成された電気的絶縁層上の第1の導電接合層と、前記複数の分離反射金属スタックと、を含み、前記第2の基板スタックは、第2の導電接合層を含み、
前記第1の基板スタックを、前記第2の基板スタックに接合する工程は、前記第1の導電接合層を前記第2の導電接合層に接合して、合金接合層を形成することを、更に含む、請求項1に記載の方法。 - 前記第の導電接合層及び前記第2の導電接合層のうちの1つが、350℃よりも低い液相線温度を有し、前記合金接合層は350℃よりも低い液相線温度を有し、又は、
前記第1の導電接合層及び前記第2の導電接合層のうちの1つが、200℃よりも低い液相線温度を有し、前記合金接合層は200℃よりも低い液相線温度を有する、又は請求項2に記載の方法。 - 前記第1の導電接合層及び前記第2の導電接合層のうちの1つは、インジウムと錫とからなるグループから選択された材料を含む、請求項3に記載の方法。
- 前記第1の導電接合層及び前記第2の導電接合層のうちの1つは、前記第1の導電接合層及び前記第2の導電接合層のうちの他の1つの厚さの5%以下の厚さを持つ、請求項4に記載の方法。
- 前記p−nダイオード層上で反射金属スタック層をパターン形成して、前記p−nダイオード層上に、前記複数の分離反射金属スタックを形成する工程を更に含む、請求項1に記載の方法。
- 前記複数の分離反射金属スタック上に前記電気的絶縁層を成膜させる工程を更に含む、請求項6に記載の方法。
- 前記電気的絶縁層をパターン形成して、前記複数の分離反射金属スタックを露出する、複数の開口部を形成する工程を更に含む、請求項7に記載の方法。
- 第1の導電接合層を、前記パターン形成された電気的絶縁層と、前記複数の分離反射金属スタックと、の上に成膜させる工程を更に含む、請求項8に記載の方法。
- 前記複数のマイクロp−nダイオードそれぞれの側面と前記底面上に共形誘電バリア層を成膜させる工程を更に含む、請求項1に記載の方法。
- 前記共形誘電バリア層は、前記マイクロp−nダイオード内の量子井戸層の側面を覆う、請求項10に記載の方法。
- 前記p−nダイオード層をエッチング処理して前記複数のマイクロp−nダイオードを形成する工程は、プラズマエッチングを含む、請求項1に記載の方法。
- 前記接合層は、高分子化合物、金属、又は金属合金を含む、請求項1に記載の方法。
- 前記複数の分離反射金属スタックの上に、前記電気的絶縁層を成膜し、前記電気的絶縁層をパターン形成して、前記複数の分離反射金属スタックを露出させる複数の開口部を含む、前記パターン形成した電気的絶縁層を形成する工程を更に含む、請求項1に記載の方法。
- 前記複数の分離反射金属スタックが、前記複数の分離反射金属スタックを露出させる前記複数の開口部よりも広い、請求項14に記載の方法。
Applications Claiming Priority (15)
Application Number | Priority Date | Filing Date | Title |
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US201161561706P | 2011-11-18 | 2011-11-18 | |
US61/561,706 | 2011-11-18 | ||
US201261594919P | 2012-02-03 | 2012-02-03 | |
US61/594,919 | 2012-02-03 | ||
US201261597109P | 2012-02-09 | 2012-02-09 | |
US61/597,109 | 2012-02-09 | ||
US201261597658P | 2012-02-10 | 2012-02-10 | |
US61/597,658 | 2012-02-10 | ||
US13/372,422 US8349116B1 (en) | 2011-11-18 | 2012-02-13 | Micro device transfer head heater assembly and method of transferring a micro device |
US13/372,422 | 2012-02-13 | ||
US13/436,260 | 2012-03-30 | ||
US13/436,314 US8518204B2 (en) | 2011-11-18 | 2012-03-30 | Method of fabricating and transferring a micro device and an array of micro devices utilizing an intermediate electrically conductive bonding layer |
US13/436,314 | 2012-03-30 | ||
US13/436,260 US8573469B2 (en) | 2011-11-18 | 2012-03-30 | Method of forming a micro LED structure and array of micro LED structures with an electrically insulating layer |
PCT/US2012/064215 WO2013074370A1 (en) | 2011-11-18 | 2012-11-08 | Method of forming a micro led structure and array of micro led structures with an electrically insulating layer |
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JP6100275B2 true JP6100275B2 (ja) | 2017-03-22 |
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JP2014542347A Active JP6100275B2 (ja) | 2011-11-18 | 2012-11-08 | 電気的絶縁層を持つマイクロled構造体及びマイクロled構造体のアレイの形成方法 |
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JP (1) | JP6100275B2 (ja) |
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MX (1) | MX336453B (ja) |
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BR112014011807A2 (pt) | 2017-05-16 |
WO2013074372A1 (en) | 2013-05-23 |
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TWI559572B (zh) | 2016-11-21 |
JP2014533890A (ja) | 2014-12-15 |
AU2012339938B2 (en) | 2015-02-19 |
AU2012339938A1 (en) | 2014-06-05 |
IN2014CN03711A (ja) | 2015-10-09 |
WO2013074370A1 (en) | 2013-05-23 |
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TWI568021B (zh) | 2017-01-21 |
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