GB2544335A - A method and apparatus for use in the manufacture of a display element - Google Patents

A method and apparatus for use in the manufacture of a display element Download PDF

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Publication number
GB2544335A
GB2544335A GB1520072.8A GB201520072A GB2544335A GB 2544335 A GB2544335 A GB 2544335A GB 201520072 A GB201520072 A GB 201520072A GB 2544335 A GB2544335 A GB 2544335A
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United Kingdom
Prior art keywords
electronic devices
handle layer
devices
led
subset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB1520072.8A
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GB201520072D0 (en
Inventor
Henry William
Joseph Hughes Patrick
O'keeffe Joseph
Pourchet Alain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Starboard Acquisitions Sub LLC
Meta Platforms Technologies LLC
Original Assignee
Oculus VR Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oculus VR Inc filed Critical Oculus VR Inc
Priority to GB1520072.8A priority Critical patent/GB2544335A/en
Publication of GB201520072D0 publication Critical patent/GB201520072D0/en
Priority to JP2018521246A priority patent/JP2018536987A/en
Priority to CN202110102259.7A priority patent/CN112928047A/en
Priority to EP16865140.4A priority patent/EP3375255A4/en
Priority to US15/349,760 priority patent/US10070568B2/en
Priority to KR1020187013730A priority patent/KR20180069039A/en
Priority to PCT/US2016/061645 priority patent/WO2017083731A1/en
Priority to CN201680066300.7A priority patent/CN108353481B/en
Publication of GB2544335A publication Critical patent/GB2544335A/en
Priority to US16/027,180 priority patent/US10863658B2/en
Priority to JP2021081612A priority patent/JP7106714B2/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/0404—Pick-and-place heads or apparatus, e.g. with jaws
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
    • B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
    • B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
    • B07C5/34—Sorting according to other particular properties
    • B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages

Abstract

In a micro-assembly method of manufacture of a display element, a pickup tool (PUT) is used for selective picking of a subset of LED dies from a handle layer. The strength of adhesion of the subset of devices to be picked from the handle layer has been modified, so that the strength of adhesion of the dies to the handle layer is less than the force applied by the pickup tool. The handle layer may be UV tape which is selectively irradiated with a UV light only below the subset of devices to be picked; a thermal release tape; or a multiple layer tape. The devices may be micron scale directional parabolic inorganic LED devices. The subset of devices may be transferred to a substrate of a display element. A computer program may comprise instructions for executing the method.

Description

A Method and Apparatus for Use in the Manufacture of a Display Element
Technical Field
The invention relates to methods and apparatus for use in the manufacture of a display element. The invention finds particular application in enabling selective picking of LED dies from a handle layer.
Background
Displays are ubiquitous and are a core component of many wearable electronic devices, smart phones, tablets, laptops, desktops, TVs and display systems. Common display technologies today range from Liquid Crystal Displays (LCD’s) to more recent Organic Light Emitting Diode Displays (OLEDs).
The display architectures include passive and active matrix displays depending on whether each pixel is driven separately or not. Active drive circuitry uses thin film transistor (TFT) technology where transistors based on amphorous, oxide or polysilicon technology are manufactured on glass panels which may have glass substrate sizes from the 1st generation of 30 cm x 40 cm to the 10th generation (known as GEN 10) of 2.88 m x 3.15m.
However, in most portable devices (i.e. battery powered devices) the display uses the majority of the available battery power. Additionally, the most common user issue for portable devices is insufficient display brightness. To extend battery life and improve brightness levels, it is necessary to develop new display technologies that reduce power consumption and produce higher luminance emission from the light source. I LED Display (Inorganic LED Displays) are emerging as the next generation of flat display image generators providing superior battery performance and enhanced brightness. The ILED Display is, at a basic level, a variation of the OLED (organic LED) display. The OLED concept is based on passing current through organic or polymer materials that are sandwiched between two glass planes to produce light. The proposed ILED Display concept essentially replaces the organic LED material with a discrete standard LED (which is made of inorganic materials) at each pixel of the display (each pixel consists of three individual Red, Green and Blue LEDs for colour displays).
Standard (i.e. inorganic) LED devices have been around for many years and their performance (efficiency, brightness, reliability and lifetime) has been optimised over many years as the LED industry has pursued many commercial opportunities -especially the challenge of developing LED technology to enable it to replace the standard incandescent bulbs for general light applications, i.e. inorganic LEDs are significantly more efficient, bright and reliable than the new and less developed OLED materials.
The concept of individually switchable standard LEDs (R, G & B) at each pixel in a display is well known. This approach is in widespread use for large information displays. However, to-date it has not been possible to scale this approach down to smaller displays as standard LEDs are typically planar chips which are inefficient for light direction control. Additionally, the assembly of the many millions of pixels needed for a laptop or smart phone display is not feasible using standard assembly manufacturing techniques.
Summary of the Invention
Disclosed herein is a manufacturing assembly method for ILED Displays, i.e. assembling millions of inorganic LED dies in a matrix array to produce an LED Display.
Exemplary embodiments relate to a method of patterning a handle layer in order to selectively release dies for picking, and to enable what is known as a selectable pick up tool (PUT) to be used in a micro-assembly method.
The handle layer may optionally be UV tape. This UV tape is selectively irradiated (patterned) with a UV light only below the LEDs (this is termed a corresponding section of the handle layer, in that it corresponds to the location of an LED device) which need to be picked. The adhesion between these LEDs and the tape is decreased, which allows a picking of the selected chips by a PUT during the pick action of a microassembly pick and place cycle.
The UV light can be from any UV source that can be used for patterning, such as UV laser, UV LED Array or UV light and mask.
Other handle layers such as thermal release tape, multiple layer tape or any adhesion switchable layer can be alternatively used.
This method enables the selective: removal of known bad dies from a wafer/handle layer or substrate picking of dies for the placement of only known good die during the transfer print operation picking of a reduced (subset) of the full LED array on a PUT during a transfer print cycle
An alternative of this approach can be the irradiated (patterned) treatment of the handle layer to enhance rather than reduce the adhesion of specific die in order to manage and control the picking of die.
In accordance with a first aspect of the invention, there is provided a method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer. The method comprises modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT, thereby enabling selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.
The one or more electronic devices may comprise the subset of electronic devices. The level of adhesion of the one or more electronic devices may be reduced.
The method may further comprise picking up the subset of the plurality of electronic devices from the handle layer using the PUT.
The PUT may apply the force to the subset of the plurality of electronic devices by adhesion. The method may further comprise contacting the PUT with the subset of the plurality of electronic devices.
The PUT may be a non-selective PUT.
The step of modifying the level of adhesion between the one or more electronic devices of the plurality of electronic devices and the handle layer may comprise one or more of: heating the one or more electronic devices and/or corresponding portions of the handle layer; and applying a liquid stimulus to the one or more devices and/or corresponding portions of the handle layer.
The step of modifying the level of adhesion between the one or more electronic devices of the plurality of devices and the handle layer may comprise irradiating a corresponding portion of the handle layer with light.
The light may comprise ultraviolet, UV, light.
The UV light may originate from one or more of: a UV laser; a UV LED array; and a UV light source passed through a photolithography mask.
The plurality of electronic devices adhered to a handle layer may comprise light emitting diode, LED, devices.
The plurality of LED devices may be inorganic LED devices.
The plurality of LED devices may be micro-LED, pLED, devices comprising a pLED emitter comprising: a substantially parabolic mesa structure; a light emitting source within the mesa structure; and a primary emission surface on a side of the device opposed to a top of the mesa structure.
The handle layer may comprise any one of: a semiconductor wafer; a UV tape; a thermal release tape; a multiple layer tape; or any other adhesion adjustable layer.
The method may further comprise transferring, using the PUT, the subset of the plurality of electronic devices to a substrate of a display element.
In accordance with a second aspect of the invention, there is provided a computer program comprising instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to the first aspect of the invention.
The carrier may be one of an electronic signal, optical signal, radio signal, or non-transitory computer readable storage medium.
Brief Description of the Drawings
Figure 1 illustrates schematically a pLED device.
Figure 2 illustrates a beam profile output from a commercial planar LED device, a beam profile output from a pLED device and an image of a single pixel beam.
Figure 3 illustrates schematically an overview of an eLED assembly process flow.
Figures 4A-4E illustrates schematically an overview of an exemplary “pick and place” process.
Detailed Description
Generally disclosed herein is a way of achieving a selectable pick up tool (PUT) for micro-assembly. pLED technology in this invention refers to micron size I LED devices which directionalise the light output and maximise the brightness level observed by the user. The pLED as disclosed in US7518149 is a next generation LED technology developed specifically to deliver directionalised light, i.e. only to where it is required.
The pLED is typically < 20pm in diameter with a parabolic structure etched directly onto the LED die during the wafer processing steps to form a quasi-collimated light beam emerging from the chip (Figure 2, Figure 1). The micro I LED emitters shows a micro ILED structure 100 similar to that proposed in WO 2004/097947 (US 7,518,149) with a high extraction efficiency and outputting quasi-collimated light because of its shape. Such a micro ILED 300 is shown in Figure 1, wherein a substrate 302 has a semiconductor epitaxial layer 304 located on it. The epitaxial layer 104 is shaped into a mesa 306. An active (or light emitting) layer 308 is enclosed in the mesa structure 306. The mesa 306 has a truncated top, on a side opposed to a light transmitting or emitting face 310. The mesa 306 also has a near-parabolic shape to form a reflective enclosure for light generated or detected within the device. The arrows 312 show how light emitted from the active layer 308 is reflected off the walls of the mesa 306 toward the light exiting surface 310 at an angle sufficient for it to escape the LED device 300 (i.e. within the angle of total internal reflection). The electrical contact pad of the device are not shown in Figure 1 but are located on the opposite surface to the emitting face 310.
This shaped structure results in a significant increase in the efficiency into low illumination angles when compared to unshaped or standard LED chips, see Figure 2. This increased efficiency and collimated output of the pLED is such that it can produce light visible to the human eye with only nano-amps of drive current. A “pAssembly ready” process flow is disclosed in Figure 3, based on GaN on sapphire material system for blue and green emitting pLEDs. It should be appreciated that this invention is not restricted to this material system nor the sequence of process flow proposed in this disclosure.
The process starts with a GaN on sapphire wafer with epi-layer and/or template plus the substrate which is tailored for ILED chip manufacture and assembly readiness.
An initial step in the process is the manufacture of the pLED device and together with p and n contact pads. After pLED fabrication the chips are partially singulated on the wafer by a combination of photolithography to define a hard mask and dry etch methods (e.g. DRIE or ICP etch tools) which etches a typical 2pm wide, 3-5pm deep trench in the GaN epilayer/template between neighbouring devices. As an example, a SiOx hard mask is deposited and patterned using deep UV resist &amp; photolith tools to transfer the defined pattern into the SiOx using CF4/CHF3 ICP etch chemistry. This is followed by a second chlorine based etch chemistry to etch the GaN. The hard mask is left on the devices for isolation purposes.
After the partial singulation, a mechanical (or handle) layer (ie tape) is applied to the top surface which acts as a handle layer for subsequent processing steps. Once the handle layer is applied a laser lift-off process is applied which removes the sapphire substrate using a laser beam. Laser lift-off processing is a technique to detach the sapphire substrate from the GaN epilayers using excimer laser photons. The technology is of interest for high throughput and superior quality in the manufacture of HB-LEDs (high brightness) and flexible displays.
Once the sapphire substrate is detached the structure is ready for assembly. Assembly may be undertaken using pick and place techniques and the modification of the adherence of each electronic device to the handle layer, as disclosed herein. A manufacturing processes is disclosed herein which addresses the assembly of semiconductor chips to form an electrical circuit. One embodiment can be an ILED image generator for display products.
It is therefore an objective of the methods and apparatus disclosed to provide an image generator and associated method of manufacture using a plurality of ILED chips which are especially designed to enable their contact and conformance to a pick up tool (PUT) for handling and manipulation onto a glass panel which may include thin film transistor (TFT) circuitry.
Specifically, disclosed herein is a method that enables the selective picking of ILED die (devices) from a handle layer using a pick up tool (PUT) by manipulating the adhesion properties of the handle layer on which the dies are mounted. This method is particularly suited to situations where micro-assembly is used to transfer LED dies from a wafer or alternative substrate (the handle layer) to a glass panel or similar substrate.
The handle layer adhesion is sensitised and adapted selectively and locally by an external stimulus. This stimulus can for example be light activated, thermally activated, liquid activated or alternatively by structuring the handle layer with microstructures which control the adhesion properties of the handle layer. The stimulus may applied to the specific die that are to be picked by the PUT (or alternatively to the die that are not to be picked up by the PUT) prior to the PUT coming in contact with the LED wafer during the pick action of the transfer cycle.
This method facilitates the selective pick of known good die as a result of defect or parametric failures from the handle wafer, or alternatively picking a subset of a full array of I LED die if a subset such is required to complete the assembly of the full image generator. The method can also be applied to pick bad die from a wafer or substrate as part of a repair or replacement cycle.
Normally a PUT, structured to pick up a 2D array of dies, will pick a die in all locations on contacting the source of the dies (that may be located on a wafer or alternative substrate) due to the pick forces applied by the PUT. In designing such a system, one has to ensure that the pick forces of the PUT exceed the adhesiveness between the LED die and the handle wafer/substrate. However, in this basic situation it is not possible to selectively change the equilibrium of these forces to enable some specified die to remain unpicked. The methods and apparatus disclosed herein enable such a selection. This is achieved by modifying the adhesiveness between the LED die and the handle wafer/substrate prior to the pick action to ensure only some dies (the selected ones) have an adhesiveness force (level of adhesion) < pick forces provided by the PUT - ensure that these are picked. This same method can be used to selectively remove known bad dies from a substrate.
In order to build a display, a first set of ILEDs is picked from the handle layer with a PUT and placed on glass panel (optionally containing TFT circuits to control the ILEDs). That sequence is repeated with a second set of LEDs, and subsequently, until the display is fully populated. Each set of LEDs can consist of thousands of LEDs.
The success of the picking and placing steps is based on the control of the adhesion cascade between the different steps of the process.
Indeed, for a successful picking of an LED by the PUT, the adhesion PUT/LED must be stronger than the adhesion LED/handle. Similarly, for a successful placing of an LED, the adhesion receiving substrate/LED must be stronger than the adhesion PUT/LED.
Alternatively, it might also be possible to switch off the PUT/LED adhesion during the placement cycle.
This invention consists in a method of patterning a LED handle layer in areas corresponding to particular LEDs in order to control its adhesion and selectively release the selected LEDs for picking.
Initially the adhesion LED/handle is stronger than the adhesion PUT/LED. This invention allows to selectively decrease the adhesion LED/handle under a selected LED such that it becomes smaller than the adhesion PUT/LED. In that case, the selected LEDs are picked by the PUT while the others stay on the handle layer.
The handle layer is, in exemplary arrangement, UV tape. This UV tape is irradiated with patterned UV light only below the LEDs which need to be picked. The adhesion between these LEDs and the tape is decreased which allows a picking of the chips by the PUT.
The UV light can be from any UV source that can be used for patterning:
Examples are given below: - UV laser or UV pLED Array (maskless photolithography) - Standard UV light source shined through a standard photolithography mask.
An overview of the overall pick and place process in the case of UV tape is given in Figures 4A-4E.
Other handle layers can be used instead of UV tape. Some examples are given below: - thermal release tape: The area below the selected LED is heated via a laser or any selective heat source. - Multiple layer tape: the layer(s) underneath the selected LEDs are vaporized by a laser or any selective vaporizing source. - Substrate covered with an adhesion switchable layer (UV glue, wax, etc.)
The PUT can be of any type and material as long as it meets the adhesion requirements. UV tape can even be used as a PUT. That approach is interesting as the adhesion PUT/LED can be decreased by UV irradiation after the picking step, which makes the placing easier. That approach requires the use of a fresh UV tape for every pick and place sequence.
On a commercial ILED display, all LEDs have to be functional. In a typical LED manufacturing environment all LEDs on a wafer are tested. This is generally achieved by using specialist LED testing equipment that makes electrical contact with the P &amp; N contacts of each LED on the wafer. However, when LEDs are manufactured for ILED displays, the LED die is many orders of magnitude smaller than those produced for other lighting applications. There may be 100 million separate LED dies on a 4” wafer. This makes it difficult if not impossible to test each die and to create a known good die (KGD) map.
One use of a selectable pick-up method, such as those disclosed herein, is to enable a manufacturing flow that enables the production of high yielding ILED displays using a selectable PUT using untested LED wafers. In such a flow, the PUT picks a LED in every location during a first pick and place cycle. The LEDs are then tested in the glass panel. A second pick and place cycle will pick LEDs only on the PUT locations that match the locations on the glass panel where defective or missing LEDs were detected during the test cycle. This selectable picking is enabled by the proposed methods and apparatus. Multiple such additional pick and place cycles can be used to ensure that a working LED is located at each location (100% working display pixels) on the glass substrate using the selectable pick-up methods outlined herein, i.e. whereby a non-selectable PUT only picks LEDs in the locations on the PUT to match the locations on the glass panel were defective or missing LEDs were detected during the last test cycle.
Another use of the proposed selectable pick-up methods relates to a situation where a KGD map is available for a LED wafer - assuming that an appropriate test methodology can be used to create a wafer KGD map. This is a modification to the process described above. The selectable pick-up methods can be used to eliminate/prevent the pick-up of defective die during the pick and place cycle thereby ensuring that no bad die are placed onto the glass substrate. The subsequent pick and place cycles described above will backfill any locations on the glass substrate that did not receive a LED in a previous pick and place cycle for this reason.
Another use of the proposed selectable pick-up methods is to ‘repair’ an LED wafer before using it for the above proposed I LED display manufacturing process. A selectable pick-up method could be used to selectably remove (and dump) an array of defective LEDs from a wafer or the handle layer described above - assuming that an appropriate test methodology can be used to create a wafer KGD map. Replacement die can then be picked from another wafer and put into the first wafer locations in which the bad die were removed. Multiple such replacement cycles may be required to backfill all the positions from which defective dies were removed. This approach will create a LED wafer/handle layer with a 100% LED yield. Such a wafer/handle layer as the input to the above described manufacturing process will produce 100% yielding ILED Displays. A computer program may be configured to provide any of the above described methods. The computer program may be provided on a computer readable medium. The computer program may be a computer program product. The product may comprise a non-transitory computer usable storage medium. The computer program product may have computer-readable program code embodied in the medium configured to perform the method. The computer program product may be configured to cause at least one processor to perform some or all of the method.
Various methods and apparatus are described herein with reference to block diagrams or flowchart illustrations of computer-implemented methods, apparatus (systems and/or devices) and/or computer program products. It is understood that a block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions that are performed by one or more computer circuits. These computer program instructions may be provided to a processor circuit of a general purpose computer circuit, special purpose computer circuit, and/or other programmable data processing circuit to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, transform and control transistors, values stored in memory locations, and other hardware components within such circuitry to implement the functions/acts specified in the block diagrams and/or flowchart block or blocks, and thereby create means (functionality) and/or structure for implementing the functions/acts specified in the block diagrams and/or flowchart block(s).
Computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions which implement the functions/acts specified in the block diagrams and/or flowchart block or blocks. A tangible, non-transitory computer-readable medium may include an electronic, magnetic, optical, electromagnetic, or semiconductor data storage system, apparatus, or device. More specific examples of the computer-readable medium would include the following: a portable computer diskette, a random access memory (RAM) circuit, a read-only memory (ROM) circuit, an erasable programmable read-only memory (EPROM or Flash memory) circuit, a portable compact disc read-only memory (CD-ROM), and a portable digital video disc read-only memory (DVD/Blu-ray).
The computer program instructions may also be loaded onto a computer and/or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer and/or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the invention may be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.) that runs on a processor, which may collectively be referred to as "circuitry," "a module" or variants thereof.
It should also be noted that in some alternate implementations, the functions/acts noted in the blocks may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated.
The skilled person will be able to envisage other embodiments without departing from the scope of the appended claims.

Claims (16)

CLAIMS:
1. A method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer, the method comprising: modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT, thereby enabling selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.
2. The method of claim 1, wherein the one or more electronic devices comprises the subset of electronic devices, and wherein the level of adhesion of the one or more electronic devices is reduced.
3. The method of claim 1 or 2 further comprising: picking up the subset of the plurality of electronic devices from the handle layer using the PUT.
4. The method of claim 3, wherein the PUT applies the force to the subset of the plurality of electronic devices by adhesion, the method further comprising contacting the PUT with the subset of the plurality of electronic devices.
5. The method of any preceding claim, wherein the PUT is a non-selective PUT.
6. The method of any preceding claim, wherein the step of modifying the level of adhesion between the one or more electronic devices of the plurality of electronic devices and the handle layer comprises one or more of: heating the one or more electronic devices and/or corresponding portions of the handle layer; and applying a liquid stimulus to the one or more devices and/or corresponding portions of the handle layer.
7. The method of any preceding claim, wherein the step of modifying the level of adhesion between the one or more electronic devices of the plurality of devices and the handle layer comprises irradiating a corresponding portion of the handle layer with light.
8. The method of claim 7, wherein the light comprises ultraviolet, UV, light.
9. The method of claim 8, wherein the UV light originates from one or more of: a UV laser; a UV LED array; and a UV light source passed through a photolithography mask.
10. The method of any preceding claim, wherein the plurality of electronic devices adhered to a handle layer comprise light emitting diode, LED, devices.
11. The method of claim 10, wherein the plurality of LED devices are inorganic LED devices.
12. The method of claim 10 or 11, wherein the plurality of LED devices are micro-LED, pLED, devices comprising a pLED emitter comprising: a substantially parabolic mesa structure; a light emitting source within the mesa structure; and a primary emission surface on a side of the device opposed to a top of the mesa structure.
13. The method of any preceding claim, wherein the handle layer comprises any one of: a semiconductor wafer; a UV tape; a thermal release tape; a multiple layer tape; or any other adhesion adjustable layer.
14. The method of any one of claims 3 to 13, further comprising: transferring, using the PUT, the subset of the plurality of electronic devices to a substrate of a display element.
15. A computer program comprising instructions which, when executed on at least one processor, cause the at least one processor to carry out the method according to any one of claims 1 to 14.
16. A carrier containing the computer program of claim 15, wherein the carrier is one of an electronic signal, optical signal, radio signal, or non-transitory computer readable storage medium.
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GB1520072.8A GB2544335A (en) 2015-11-13 2015-11-13 A method and apparatus for use in the manufacture of a display element
CN201680066300.7A CN108353481B (en) 2015-11-13 2016-11-11 Method and apparatus for manufacturing display element
US15/349,760 US10070568B2 (en) 2015-11-13 2016-11-11 Method and apparatus for use in the manufacture of a display element
CN202110102259.7A CN112928047A (en) 2015-11-13 2016-11-11 Method and apparatus for manufacturing display element
EP16865140.4A EP3375255A4 (en) 2015-11-13 2016-11-11 A method and apparatus for use in the manufacture of a display element
JP2018521246A JP2018536987A (en) 2015-11-13 2016-11-11 Method and apparatus for use in the manufacture of display elements
KR1020187013730A KR20180069039A (en) 2015-11-13 2016-11-11 Method and apparatus for use in manufacturing a display device
PCT/US2016/061645 WO2017083731A1 (en) 2015-11-13 2016-11-11 A method and apparatus for use in the manufacture of a display element
US16/027,180 US10863658B2 (en) 2015-11-13 2018-07-03 Method and apparatus for use in the manufacture of a display element
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