JP6028793B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6028793B2 JP6028793B2 JP2014504743A JP2014504743A JP6028793B2 JP 6028793 B2 JP6028793 B2 JP 6028793B2 JP 2014504743 A JP2014504743 A JP 2014504743A JP 2014504743 A JP2014504743 A JP 2014504743A JP 6028793 B2 JP6028793 B2 JP 6028793B2
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- 239000004065 semiconductor Substances 0.000 title claims description 68
- 239000000758 substrate Substances 0.000 claims description 70
- 239000011347 resin Substances 0.000 claims description 35
- 229920005989 resin Polymers 0.000 claims description 35
- 238000007789 sealing Methods 0.000 claims description 20
- 238000005553 drilling Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 230000007423 decrease Effects 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 description 89
- 239000010949 copper Substances 0.000 description 89
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 87
- 230000000694 effects Effects 0.000 description 12
- 239000000919 ceramic Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Description
前記導電ブロックが固着した箇所の周囲の前記導電パターンに、該導電ブロックから外に向って単位長さあたりの本数が増加する環状の穿設溝を配置して、前記導電パターンの前記導電ブロックが固着した箇所の周囲全体が、該導電ブロックの端部から外に向って単位面積あたりの平均の導電膜の体積を減少するような断面形状を有している構成とする。
<実施例1>
図1は、本発明の第1実施例における半導体装置の要部断面図である。
図1において、半導体装置である半導体パワーモジュールは、絶縁基板1とこの絶縁基板1の表裏に形成される銅回路パターン2a,2bで構成される導電パターン付絶縁基板であるDCB(Direct Copper Bonding)基板4を備える。また、この半導体パワーモジュールは、DCB基板4の銅回路パターン2aに拡散接合等で固着する銅ブロック3aと、DCB基板4の銅回路パターン2bに拡散接合等で固着する銅ブロック3bを備える。さらに、この半導体パワーモジュールは、銅ブロック3a上に半田などの接合材5で裏面が固着する半導体チップ6と、半導体チップ6の上面電極に半田などの接合材7で固着する導電ポスト8と、この導電ポスト8を有するプリント基板9とを備える。さらにまた、この半導体パワーモジュールにおいて、銅ブロック3aとプリント基板9にはそれぞれ、外部導出端子10が、図示しない接合材により固着されている。さらにまた、この半導体パワーモジュールは、前記の半導体チップ6およびDCB基板4およびプリント基板9を封止する封止樹脂11を備える。封止樹脂11からは、外部導出端子10の端部と銅ブロック3bの一の主面が露出している。
<実施例2>
図4は、本発明の第2実施例における半導体装置の要部平面図である。この図は半導体装置を構成するDCB基板4の要部平面図である。この平面図は図2に相当する平面図である。
<実施例3>
図6は、本発明の第3実施例における半導体装置の要部平面図である。この図は半導体装置を構成するDCB基板4の要部平面図である。この平面図は図2に相当する平面図である。
<実施例4>
図9は、本発明の第4実施例における半導体装置のDCB基板の要部平面図(a)および要部断面図(b)である。図2との違いは、穿設穴を形成するのではなく、銅回路パターン2aの厚さを変えた点である。厚さを外に向って一定の割合で徐々に薄くしたスロープ状銅回路パターン14により、同様の効果が得られる。また、図10のようにスロープ状でなく階段状に薄くした階段状銅回路パターン15にしても同様の効果が得られる。また、図示しないが、この構造に穿設穴もしくは環状の穿設溝を均一に配置すると、アンカー効果が発生するため、樹脂11の密着性はさらに向上する。
2a,2b 銅回路パターン
3a,3b 銅ブロック
4 DCB基板
5,7 接合材
6 半導体チップ
8 導電ポスト
9 プリント基板
10 外部導出端子
11 封止樹脂
12a,b,c 穿設穴
12d,12e 環状の穿設溝
12h 底面がある穿設穴
12j 底面がある環状の穿設溝
13 底部
14 スロープ状銅回路パターン
15 階段状銅回路パターン
Claims (7)
- 導電パターン付絶縁基板と、該導電パターン付絶縁基板の導電パターン上に固着された導電ブロックと、該導電ブロック上に固着された半導体チップと、該半導体チップ上に固着された導電ポストを備えるプリント基板と、これらを封止する樹脂とを備えている半導体装置において、
前記導電ブロックが固着した箇所の周囲の前記導電パターンに、該導電ブロックから外に向って単位面積あたりの個数が増加するように穿設穴を配置して、前記導電パターンの前記導電ブロックが固着した箇所の周囲全体が、該導電ブロックの端部から外に向って単位面積あたりの平均の導電膜の体積を減少するような断面形状を有している半導体装置。 - 導電パターン付絶縁基板と、該導電パターン付絶縁基板の導電パターン上に固着された導電ブロックと、該導電ブロック上に固着された半導体チップと、該半導体チップ上に固着された導電ポストを備えるプリント基板と、これらを封止する樹脂とを備えている半導体装置において、
前記導電ブロックが固着した箇所の周囲の前記導電パターンに、該導電ブロックから外に向って単位長さあたりの本数が増加する環状の穿設溝を配置して、前記導電パターンの前記導電ブロックが固着した箇所の周囲全体が、該導電ブロックの端部から外に向って単位面積あたりの平均の導電膜の体積を減少するような断面形状を有している半導体装置。 - 前記穿設穴の底部が、前記導電膜により塞がれていることを特徴とする請求項1に記載の半導体装置。
- 前記環状の穿設溝の底部が、前記導電膜により塞がれていることを特徴とする請求項2に記載の半導体装置。
- 前記導電パターン付絶縁基板の表面側に前記導電パターンが接合され、該導電パターン上に前記導電ブロックおよび前記半導体チップが順に固着されており、かつ、前記導電パターン付絶縁基板の裏面側に他の導電パターンが接合され、該他の導電パターン上に他の導電ブロックが固着されており、
前記他の導電ブロックの一の主面が前記樹脂から露出していることを特徴とする請求項1に記載の半導体装置。 - 前記導電パターンおよび他の導電パターンが金属膜であり、前記導電ブロックおよび他の導電ブロックが金属ブロックであることを特徴とする請求項5に記載の半導体装置。
- 前記他の導電パターンに穿設穴が形成されている請求項5に記載の半導体装置。
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