JP5995518B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5995518B2 JP5995518B2 JP2012109950A JP2012109950A JP5995518B2 JP 5995518 B2 JP5995518 B2 JP 5995518B2 JP 2012109950 A JP2012109950 A JP 2012109950A JP 2012109950 A JP2012109950 A JP 2012109950A JP 5995518 B2 JP5995518 B2 JP 5995518B2
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- 229920005591 polysilicon Polymers 0.000 claims description 90
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- 238000000151 deposition Methods 0.000 claims description 25
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
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Description
この構成によれば、凹凸緩和層が形成されているため、半導体層の最表面(凹凸形状)に金属材料を直接堆積させて表面電極を形成する場合に比べて、表面電極の表面を滑らかもしくは平坦にすることができる。これにより、表面電極にワイヤを接続するときに、表面電極の表面に対するワイヤの引っ掛かりをなくして、ワイヤ接合部を表面電極の表面全体に広げることができる。その結果、表面電極に対するワイヤの接触面積を増やすことができるので、ワイヤの密着性を向上させることができる。その結果、ワイヤの剥がれ頻度を減らすことができるので、半導体装置を組み立てる際の歩留まりを向上させ、コストを低減することができる。また、ワイヤの密着性の向上により、ワイヤ接合部の信頼性を向上させることができる。
前記凹凸緩和層は、ポリシリコン層を含むことが好ましい。
前記ポリシリコン層の厚さTは、前記凹凸形状の窪みの最大幅Wの2/3以上であることが好ましい。
前記半導体層が、第1導電型不純物領域が選択的に形成されたSiC層である場合、前記ポリシリコン層は、前記第1導電型不純物領域に接する第1導電型部分を選択的に含むことが好ましい。
前記SiC層が、選択的に形成された第2導電型不純物領域をさらに含む場合、前記ポリシリコン層は、前記第2導電型不純物領域に接する第2導電型部分を選択的にさらに含むことが好ましい。
本発明の第2の局面に係る半導体装置は、第1導電型のSiCからなる半導体層と、前記半導体層の表面に露出するように形成された第1導電型のソース層と、前記ソース層に対して前記半導体層の裏面側に前記ソース層に接するように形成された第2導電型のチャネル層と、前記チャネル層に対して前記半導体層の前記裏面側に前記チャネル層に接するように形成された第1導電型のドリフト層とを含み、前記半導体層の前記表面に形成され、前記ソース層を選択的に露出させるコンタクトホールを有する層間膜と、前記層間膜上に形成され、前記コンタクトホールを介して前記ソース層に選択的に接するポリシリコン層であって、前記層間膜の表面と、前記コンタクトホールに露出する前記半導体層の前記表面との高低差に基づいて形成された凹凸形状に比べて滑らかな表面を有するポリシリコン層と、前記ポリシリコン層上に形成された金属材料からなるソース電極とを含む。
前記ポリシリコン層は、前記ソース層に接する第1導電型部分を選択的に含むことが好ましい。
前記チャネル層は、前記半導体層の前記表面に露出し、当該チャネル層の他の部分よりも高濃度な第2導電型のチャネルコンタクト層を含み、前記ポリシリコン層は、前記チャネルコンタクト層に接する第2導電型部分をさらに含むことが好ましい。
前記半導体装置は、前記半導体層の前記表面から前記ソース層および前記チャネル層を貫通して前記ドリフト層に達するゲートトレンチと、前記ゲートトレンチの側面および底面に形成されたゲート絶縁膜と、前記ゲートトレンチに埋め込まれたゲート電極とを含むトレンチゲート型構造を有していてもよい。また、前記半導体装置は、前記半導体層の前記表面に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極とを含むプレーナゲート型構造を有していてもよい。
前記表面電極を形成する工程は、前記ポリシリコン層の前記堆積面の平坦化処理を行わずに、堆積後のままの状態の前記ポリシリコン層に前記金属材料を堆積させる工程を含むことが好ましい。
前記ポリシリコン層を形成する工程は、LPCVD法でポリシリコンを堆積させる工程を含むことが好ましい。
図1は、本発明の第1実施形態に係る半導体装置の模式的な断面図である。
半導体装置1は、SiC(炭化シリコン)を用いたパワーMOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)素子(半導体素子)を含み、半導体層の一例としての、SiC基板2、およびSiC基板2上に形成されたSiCエピタキシャル層3を含む。SiC基板2およびSiCエピタキシャル層3の導電型は、いずれも第1導電型としてのn型である。具体的には、SiC基板2は、n+型(たとえば、濃度が1×1018〜1×1021cm−3)であり、SiCエピタキシャル層3は、SiC基板2よりも低濃度のn−型(たとえば、濃度が1×1015〜1×1017cm−3)である。SiCエピタキシャル層3は、電界効果トランジスタのドレイン領域(ドリフト層)として機能する。
個々のp型ウェル4内には、第1導電型不純物領域およびソース層の一例としてのn+型ソース領域6と、このn+型ソース領域6に取り囲まれた、第2導電型不純物領域およびチャネルコンタクト層の一例としてのp+型ウェルコンタクト領域7とが形成されている。n+型ソース領域6およびp+型ウェルコンタクト領域7は共にSiCエピタキシャル層3の表面31に露出している。そして、隣接するp型ウェル4に跨るようにゲート電極8が形成されており、このゲート電極8とSiCエピタキシャル層3との間にゲート絶縁膜9が介在されている。ゲート電極8は、n+型ソース領域6とドレイン領域としてのSiCエピタキシャル層3(p型ウェル4の間の領域)との間に跨っていて、p型ウェル4の表面における反転層(チャネル)の形成を制御する。すなわち、この半導体装置1は、いわゆるプレーナゲート型構造のMISFET(Metal Insulator Semiconductor Field Effect Transistor)を有している。
半導体パッケージ14は、端子フレーム15と、半導体装置1と、ショットキーバリアダイオード16と、樹脂パッケージ17とを含む。
ベース部18には、半導体装置1およびショットキーバリアダイオード16が互いに間隔を空けて配置されている。半導体装置1は、前記最表面が上方に向く姿勢でベース部18に設置されている。設置状態において、半導体装置1の最表面には、ソース電極13と、ゲート電極8に電気的に接続されたゲートパッド23とが露出している。一方、ショットキーバリアダイオード16の最表面には、アノード電極24が露出している。
そして、半導体装置1のドレイン電極5およびショットキーバリアダイオード16のカソード電極(図示せず)は、ベース部18に接してドレイン端子19に電気的に接続されている。半導体装置1のソース電極13およびショットキーバリアダイオード16のアノード電極24は、共通のワイヤ25を用いて、ソース端子20に電気的に接続されている。また、半導体装置1のゲートパッド23は、ワイヤ26を用いて、ゲート端子21に電気的に接続されている。
図3は、前記半導体装置の製造方法を説明するためのフロー図である。
その後、堆積したポリシリコンの全体に、マスクを介さずにn型不純物を注入する。これにより、n+型のポリシリコン層12が形成される。
また、この実施形態の方法では、ポリシリコンの堆積後、平坦化処理を省略することができるので、製造工程を簡略化することができる。しかも、ポリシリコンに対してエッチバック等の平坦化処理を行うと、結晶性によってエッチバック面に凹凸が発生するおそれがあるが、そのような凹凸の発生を防止することもできる。なお、CMPによる平坦化処理は、ポリシリコン層12に凹凸を発生させるおそれが低いので、適切な程度で行ってもよい。
半導体装置51は、SiCを用いたパワーMOSFET素子(半導体素子)を含み、半導体層の一例としての、SiC基板52、およびSiC基板52上に形成されたSiCエピタキシャル層53を含む。SiC基板52およびSiCエピタキシャル層53の導電型は、いずれも第1導電型としてのn型である。具体的には、SiC基板52は、n+型(たとえば、濃度が1×1018〜1×1021cm−3)であり、SiCエピタキシャル層53は、SiC基板52よりも低濃度のn−型(たとえば、濃度が1×1015〜1×1017cm−3)である。SiCエピタキシャル層53は、電界効果トランジスタのドレイン領域(ドリフト層)として機能する。
p型チャネル層54内には、第1導電型領域の一例としてのn+型ソース層56と、このn+型ソース層56に取り囲まれた、第2導電型不純物領域の一例としてのp+型チャネルコンタクト層57とが形成されている。n+型ソース層56およびp+型チャネルコンタクト層57は共にSiCエピタキシャル層53の表面531に露出している。
図5は、本発明の第3実施形態に係る半導体装置の模式的な断面図である。図5において、前述の図4に示された各部と対応する部分には同一の参照符号を付して示す。
この半導体装置71では、ゲートトレンチ64で区画された各p型チャネル層54の中央部に、n+型ソース層56およびp型チャネル層54を貫通してドリフト層に達するソーストレンチ72が形成されている。これにより、半導体装置71の最表面には、高低差H2に基づく凹凸形状に加えて、SiCエピタキシャル層53の表面531と、ソーストレンチ72の底面との高低差H3に基づく凹凸形状がさらに形成されている。また、n+型ソース層56およびp型チャネル層54は、ソーストレンチ72の側面に露出している。
図6〜図9は、本発明の第4〜第7実施形態に係る半導体装置の模式的な断面図である。図6および図7において、前述の図1に示された各部と対応する部分には同一の参照符号を付して示す。また、図8および図9において、前述の図5に示された各部と対応する部分には同一の参照符号を付して示す。
たとえば、プレーナゲート型構造のMISFETを有する図6および図7の半導体装置81,91では、ポリシリコン層12は、p+型ウェルコンタクト領域7の内方領域にp+型部分83,93を有し、残りの主体部がn+型部分82,92であってもよい。n型のポリシリコンはn型のSiCに対して低いコンタクト抵抗で接触でき、p型のポリシリコンはp型のSiCに対して低いコンタクト抵抗で接触できる物質である。そのため、RTA(Rapid Thermal Anneal)等の処理を行ってSiCエピタキシャル層3(n+型ソース領域6およびp+型ウェルコンタクト領域7)の表面にシリサイドを形成しなくても、n+型ソース領域6およびp+型ウェルコンタクト領域7の両方に対して、ポリシリコン層12を簡単にオーミック接触させることができる。
たとえば、前述の半導体装置1,51,71,81,91,101,201の各半導体部分の導電型を反転した構成が採用されてもよい。たとえば、半導体装置1において、p型の部分がn型であり、n型の部分がp型であってもよい。
また、層間膜10,60のコンタクトホール11,61は、SiCエピタキシャル層3,53の表面31,531に対して垂直に開口する必要はなく、たとえば、層間膜10,60の表面に向かって広がるテーパ状、もしくは狭まるテーパ状に開口してもよい。
また、前述の実施形態では、本発明をパワーMOSFETに適用した例について説明したが、本発明は、IGBT(Insulated Gate Bipolar Transistor)、JFET(Junction Field Effect Transistor)、その他の構造の半導体デバイスにも同様に適用することができる。
2 SiC基板
3 SiCエピタキシャル層
31 表面
4 p型ウェル
6 n+型ソース領域
7 p+型ウェルコンタクト領域
8 ゲート電極
9 ゲート絶縁膜
10 層間膜
11 コンタクトホール
12 ポリシリコン層
121 表面
13 ソース電極
51 半導体装置
52 SiC基板
53 SiCエピタキシャル層
531 表面
54 p型チャネル層
56 n+型ソース層
57 p+型チャネルコンタクト層
58 ゲート電極
59 ゲート絶縁膜
60 層間膜
61 コンタクトホール
62 ポリシリコン層
621 表面
63 ソース電極
71 半導体装置
72 ソーストレンチ
81 半導体装置
82 n+型部分
83 p+型部分
91 半導体装置
92 n+型部分
93 p+型部分
101 半導体装置
102 n+型部分
103 p+型部分
201 半導体装置
202 n+型部分
203 p+型部分
Claims (6)
- 第1導電型のSiCからなる半導体層と、
前記半導体層の表面に露出するように形成された第1導電型のソース層と、
前記ソース層に対して前記半導体層の裏面側に前記ソース層に接するように形成された第2導電型のチャネル層と、
前記チャネル層に対して前記半導体層の前記裏面側に前記チャネル層に接するように形成された第1導電型のドリフト層とを含み、
前記半導体層の前記表面に形成され、前記ソース層を選択的に露出させるコンタクトホールを有する層間膜と、
前記層間膜上に形成され、前記コンタクトホールを介して前記ソース層に選択的に接するポリシリコン層であって、前記層間膜の表面と、前記コンタクトホールに露出する前記半導体層の前記表面との高低差に基づいて形成された凹凸形状に比べて滑らかな表面を有するポリシリコン層と、
前記ポリシリコン層上に形成された金属材料からなるソース電極とを含み、
前記ポリシリコン層は、前記ソース層に接する第1導電型部分を選択的に含み、
前記チャネル層は、前記半導体層の前記表面に露出し、当該チャネル層の他の部分よりも高濃度な第2導電型のチャネルコンタクト層を含み、
前記ポリシリコン層は、前記チャネルコンタクト層に接する第2導電型部分をさらに含む、半導体装置。 - 前記半導体装置は、
前記半導体層の前記表面から前記ソース層および前記チャネル層を貫通して前記ドリフト層に達するゲートトレンチと、前記ゲートトレンチの側面および底面に形成されたゲート絶縁膜と、前記ゲートトレンチに埋め込まれたゲート電極とを含むトレンチゲート型構造を有する、請求項1に記載の半導体装置。 - 前記半導体装置は、
前記半導体層の前記表面に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極とを含むプレーナゲート型構造を有する、請求項1または2に記載の半導体装置。 - 前記半導体装置は、前記半導体層の前記表面から前記ソース層および前記チャネル層を貫通して前記ドリフト層に達するソーストレンチをさらに含み、
前記凹凸形状は、前記ソーストレンチの底面と、前記半導体層の前記表面との高低差に基づいて形成された凹凸を含む、請求項1〜3のいずれか一項に記載の半導体装置。 - 半導体層の表面に所定の不純物層を選択的に形成することによって、半導体素子を形成する工程と、
前記半導体層の前記表面に絶縁膜を形成する工程と、
前記絶縁膜を選択的に除去することによって、前記不純物層を露出させるコンタクトホールを形成する工程と、
前記コンタクトホールを埋め戻し、その堆積面が、前記絶縁膜の表面と、前記コンタクトホールに露出する前記半導体層の前記表面との高低差に基づいて形成された凹凸形状に比べて滑らかになるまでポリシリコンを堆積させることによって、ポリシリコン層を形成する工程と、
前記ポリシリコン層上に金属材料を堆積させることによって、表面電極を形成する工程とを含み、
前記表面電極を形成する工程は、前記ポリシリコン層の前記堆積面の平坦化処理を行わずに、堆積後のままの状態の前記ポリシリコン層に前記金属材料を堆積させる工程を含む、半導体装置の製造方法。 - 前記ポリシリコン層を形成する工程は、LPCVD法でポリシリコンを堆積させる工程を含む、請求項5に記載の半導体装置の製造方法。
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