JP5989329B2 - プリント回路基板の製造方法 - Google Patents
プリント回路基板の製造方法 Download PDFInfo
- Publication number
- JP5989329B2 JP5989329B2 JP2011254743A JP2011254743A JP5989329B2 JP 5989329 B2 JP5989329 B2 JP 5989329B2 JP 2011254743 A JP2011254743 A JP 2011254743A JP 2011254743 A JP2011254743 A JP 2011254743A JP 5989329 B2 JP5989329 B2 JP 5989329B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit board
- printed circuit
- insulating material
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
図1は、本発明の一実施例によるプリント回路基板の構造を示す断面図であり、図2は、本発明の一実施例によるプリント回路基板の半導体チップ実装用キャビティに半導体チップが挿入された状態を示す断面図である。
図3〜図8は、本発明の一実施例によるプリント回路基板の製造方法を順に説明するための工程断面図である。
110 絶縁層
110a 第1絶縁材
110b 第2絶縁材
115 銅箔層(めっき層)
117 めっき層
120 回路パターン
120a 内層回路パターン
120b 外層回路パターン
121a ワイヤボンディング用パッド
121b バンプ形成用パッド
122 キャビティ形成用ストッパー層
124a 第1ビアホール
124b 第2ビアホール
125 ビア
130a、130b 表面処理層
140 半導体チップ挿入用キャビティ
150 ソルダレジスト層
200 半導体チップ
210 ワイヤ
Claims (5)
- 第1絶縁材及び前記第1絶縁材上に形成された第2絶縁材を含む絶縁層と、
前記絶縁層の内層及び外層に形成された回路パターンと、
前記第1絶縁材又は第2絶縁材に複数個形成された半導体チップ挿入用キャビティと、を含むプリント回路基板を製造する方法であり、
前記半導体チップ挿入用キャビティの内部底面は、前記第1絶縁材上に形成されたキャビティ形成用ストッパー層が除去されて、前記第1絶縁材が露出されるように形成される段階を含む、プリント回路基板の製造方法。 - 前記回路パターンは、三層からなる請求項1に記載のプリント回路基板の製造方法。
- 前記絶縁層上に形成され、前記外層に形成された回路パターンのうち一部を露出させる開口部を有するソルダレジスト層をさらに含む請求項1に記載のプリント回路基板の製造方法。
- 前記外層に形成された回路パターンは、ワイヤボンディング用パッド及びバンプ形成用パッドを含む請求項1に記載のプリント回路基板の製造方法。
- 前記ワイヤボンディング用パッド及びバンプ形成用パッドの上に形成された表面処理層をさらに含む請求項4に記載のプリント回路基板の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020110096174A KR20130032529A (ko) | 2011-09-23 | 2011-09-23 | 인쇄회로기판 및 그 제조방법 |
KR10-2011-0096174 | 2011-09-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013070009A JP2013070009A (ja) | 2013-04-18 |
JP5989329B2 true JP5989329B2 (ja) | 2016-09-07 |
Family
ID=48435292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011254743A Active JP5989329B2 (ja) | 2011-09-23 | 2011-11-22 | プリント回路基板の製造方法 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5989329B2 (ja) |
KR (1) | KR20130032529A (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101522780B1 (ko) * | 2013-10-07 | 2015-05-26 | 삼성전기주식회사 | 전자부품 내장 인쇄회로기판 및 그 제조방법 |
KR102171021B1 (ko) | 2014-03-14 | 2020-10-28 | 삼성전자주식회사 | 회로기판 및 반도체 패키지 제조방법 |
JP6076431B2 (ja) * | 2014-09-25 | 2017-02-08 | 株式会社イースタン | 半導体パッケージ基板の製造方法 |
KR101726568B1 (ko) * | 2016-02-24 | 2017-04-27 | 대덕전자 주식회사 | 회로기판 제조방법 |
CN107305849B (zh) * | 2016-04-22 | 2020-05-19 | 碁鼎科技秦皇岛有限公司 | 封装结构及其制作方法 |
KR20210077372A (ko) | 2019-12-17 | 2021-06-25 | 삼성전기주식회사 | 전자부품 내장기판 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH098175A (ja) * | 1995-06-14 | 1997-01-10 | Fuji Kiko Denshi Kk | 多層プリント基板のボンディング用棚形成方法 |
JP3563577B2 (ja) * | 1997-10-31 | 2004-09-08 | 京セラ株式会社 | 電子部品表面実装用基板 |
JP2001110928A (ja) * | 1999-10-04 | 2001-04-20 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
JP2002353633A (ja) * | 2001-05-25 | 2002-12-06 | Shin Kobe Electric Mach Co Ltd | 多層プリント配線板の製造法及び多層プリント配線板 |
JP4493923B2 (ja) * | 2003-02-26 | 2010-06-30 | イビデン株式会社 | プリント配線板 |
KR100645643B1 (ko) * | 2004-07-14 | 2006-11-15 | 삼성전기주식회사 | 수동소자칩 내장형의 인쇄회로기판의 제조방법 |
JP5395360B2 (ja) * | 2008-02-25 | 2014-01-22 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
-
2011
- 2011-09-23 KR KR1020110096174A patent/KR20130032529A/ko not_active Application Discontinuation
- 2011-11-22 JP JP2011254743A patent/JP5989329B2/ja active Active
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Publication number | Publication date |
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KR20130032529A (ko) | 2013-04-02 |
JP2013070009A (ja) | 2013-04-18 |
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