JP5982748B2 - SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE Download PDF

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JP5982748B2
JP5982748B2 JP2011168021A JP2011168021A JP5982748B2 JP 5982748 B2 JP5982748 B2 JP 5982748B2 JP 2011168021 A JP2011168021 A JP 2011168021A JP 2011168021 A JP2011168021 A JP 2011168021A JP 5982748 B2 JP5982748 B2 JP 5982748B2
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electrode
insulating film
substrate
semiconductor device
bonding surface
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JP2013033786A5 (en
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青柳　健一
健一 青柳
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Sony Corp
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Priority to US13/533,526 priority patent/US8896125B2/en
Priority to KR1020120069684A priority patent/KR102030852B1/en
Priority to CN201210233277.XA priority patent/CN102867847B/en
Publication of JP2013033786A publication Critical patent/JP2013033786A/en
Priority to US14/467,852 priority patent/US9111763B2/en
Publication of JP2013033786A5 publication Critical patent/JP2013033786A5/en
Priority to US14/718,942 priority patent/US9443802B2/en
Priority to US15/228,860 priority patent/US10038024B2/en
Priority to US15/228,894 priority patent/US9911778B2/en
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Priority to US15/992,908 priority patent/US10431621B2/en
Priority to US16/410,877 priority patent/US10985102B2/en
Priority to KR1020190069266A priority patent/KR20190071647A/en
Priority to KR1020200069977A priority patent/KR102298787B1/en
Priority to US17/194,641 priority patent/US11569123B2/en
Priority to KR1020210112763A priority patent/KR102439964B1/en
Priority to KR1020220109225A priority patent/KR20220126271A/en
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08137—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
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    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
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    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers

Description

本技術は、半導体装置、半導体装置の製造方法、および電子機器に関し、特には２枚の基板を貼り合わせることによって電極間接合がなされた半導体装置、およびこのような半導体装置の製造方法、さらにはこの半導体装置を用いた電子機器に関する。 The present technology relates to a semiconductor device , a method for manufacturing a semiconductor device , and an electronic device , and more particularly, a semiconductor device in which interelectrode bonding is performed by bonding two substrates, a method for manufacturing such a semiconductor device , and The present invention relates to an electronic device using the semiconductor device .

半導体装置のさらなる高集積化を達成するための構造の一つとして、それぞれに素子や配線が形成された２枚の基板を積層させて貼り合わせた三次元構造が提案されている。このような三次元構造の半導体装置を製造する場合、先ず、それぞれに素子が形成された2枚の基板を用意し、それぞれの基板の貼合せ面側に、接合用の電極（ボンディングパッド）を引き出した状態とする。この際、例えば埋込配線技術（いわゆるダマシン処理）を適用することにより、銅（Ｃｕ）からなる接合用の電極が絶縁膜で囲まれた構成の貼合せ面を形成する。その後、貼合せ面を対向させて２枚の基板を配置し、さらに各貼合せ面に設けた電極同士を対応させて２枚の基板を積層させ、この状態で熱処理を施す。これにより、電極間を接合させた基板同士の貼り合わせを行なう（以上、例えば下記特許文献１参照）。   As one of the structures for achieving further high integration of semiconductor devices, a three-dimensional structure in which two substrates each having an element and wiring formed thereon are stacked and bonded has been proposed. When manufacturing a semiconductor device having such a three-dimensional structure, first, two substrates each having an element formed thereon are prepared, and bonding electrodes (bonding pads) are provided on the bonding surface side of each substrate. Pulled out. At this time, for example, by applying an embedded wiring technique (so-called damascene processing), a bonding surface having a configuration in which an electrode for bonding made of copper (Cu) is surrounded by an insulating film is formed. Thereafter, the two substrates are arranged with the bonding surfaces facing each other, and the two substrates are laminated by causing the electrodes provided on each bonding surface to correspond to each other, and heat treatment is performed in this state. Thereby, the substrates having the electrodes joined together are bonded together (for example, see Patent Document 1 below).

ここで、一般的な埋込配線技術による電極の形成は、例えば次のように行われる。先ず、基板の表面を覆う絶縁膜に溝パターンを形成し、次いで溝パターンの内壁を覆う状態で、銅（Ｃｕ）に対してバリア性を有する導電性の下地層（バリアメタル層）を絶縁膜上に成膜する。次に、バリアメタル層の上部に、溝パターンを埋め込む状態で銅（Ｃｕ）を用いた電極膜を成膜した後、バリアメタル層が露出するまで電極膜を研磨し、さらに絶縁膜が露出するまでバリアメタル層と電極膜とを研磨する。これにより、絶縁膜に形成した溝パターン内にバリアメタル層を介して電極膜が埋め込まれた埋込電極が形成される。   Here, the electrode is formed by a general embedded wiring technique, for example, as follows. First, a groove pattern is formed in an insulating film covering the surface of the substrate, and then a conductive base layer (barrier metal layer) having a barrier property against copper (Cu) is covered with the insulating film while covering the inner wall of the groove pattern. A film is formed on top. Next, after an electrode film using copper (Cu) is formed on the barrier metal layer with the groove pattern embedded, the electrode film is polished until the barrier metal layer is exposed, and the insulating film is exposed. Polish the barrier metal layer and electrode film. Thereby, a buried electrode is formed in which the electrode film is buried in the groove pattern formed in the insulating film via the barrier metal layer.

以上の埋込配線技術においては、電極膜を研磨してバリアメタル層が露出した時点で電極膜の研磨を自動的に停止できるものの、続いて行われる電極膜とバリアメタル層との研磨においては絶縁膜が露出した時点で電極膜の研磨を自動的に停止することができない。このため、研磨面内においては、溝パターン内の電極膜が過剰に研磨されるディッシングや、電極レイアウトに依存して溝パターン内の電極膜が過剰に研磨されるエロージョンが発生し易く、平坦な研磨面を得ることが困難である。そこで、電極膜を成膜する前に、絶縁膜上のバリアメタル層を除去して溝パターンの内壁のみにバリアメタル層を残し、この上部に電極膜を成膜して研磨を行う方法が提案されている（以上、下記特許文献２参照）。   In the above embedded wiring technology, the polishing of the electrode film can be automatically stopped when the electrode film is polished and the barrier metal layer is exposed, but in the subsequent polishing of the electrode film and the barrier metal layer, The polishing of the electrode film cannot be stopped automatically when the insulating film is exposed. Therefore, in the polished surface, dishing in which the electrode film in the groove pattern is excessively polished and erosion in which the electrode film in the groove pattern is excessively polished depending on the electrode layout are likely to occur and are flat. It is difficult to obtain a polished surface. Therefore, before the electrode film is formed, a method is proposed in which the barrier metal layer on the insulating film is removed, leaving the barrier metal layer only on the inner wall of the groove pattern, and the electrode film is formed on the upper portion and polished. (See Patent Document 2 below).

特開２００６−１９１０８１号公報JP 2006-191081 A 特開２０００−１２５４０号公報JP 2000-12540 A

ところで上述したような貼り合わせによって得られる三次元構造の半導体装置においては、絶縁膜中への電極材料の拡散を防止しつつ、２枚の基板同士の貼り合わせ強度、および電極間の接合強度が確保された構造が望まれている。しかしながら、上記特許文献１に示された半導体装置の製造方法では、絶縁膜中への電極材料の拡散を防止することができない。   By the way, in the semiconductor device having a three-dimensional structure obtained by bonding as described above, the bonding strength between two substrates and the bonding strength between the electrodes are prevented while preventing the diffusion of the electrode material into the insulating film. A secured structure is desired. However, the semiconductor device manufacturing method disclosed in Patent Document 1 cannot prevent the electrode material from diffusing into the insulating film.

一方、上記特許文献２に示された埋込配線技術では、バリアメタル層（下地層）を介して電極膜を設けたことにより、絶縁膜中への電極材料の拡散は防止できる。しかしながら、この埋込配線技術は、基板同士の貼り合わせを考慮したものではなく、研磨によって得られた平坦化面に電極および絶縁膜と共にバリアメタル層が露出した状態になる。このため、平坦化面の全面において十分な貼り合わせ強度を確保することは困難である。   On the other hand, in the embedded wiring technique disclosed in Patent Document 2, diffusion of the electrode material into the insulating film can be prevented by providing the electrode film via the barrier metal layer (underlying layer). However, this embedded wiring technique does not consider bonding between substrates, and the barrier metal layer is exposed together with the electrode and the insulating film on the planarized surface obtained by polishing. For this reason, it is difficult to ensure sufficient bonding strength over the entire planarized surface.

そこで本技術は、２枚の基板の貼り合わせによって電極間接合がなされた構成において、絶縁膜中への電極材料の拡散を防止しつつも貼り合わせ強度が確保され、これによって信頼性の向上が図られた三次元構造の半導体装置を提供することを目的とする。また本技術はこのような半導体装置の製造方法を提供することを目的とする。   Therefore, in the present technology, the bonding strength is ensured while preventing the diffusion of the electrode material into the insulating film in the configuration in which the electrodes are bonded by bonding the two substrates, thereby improving the reliability. An object of the present invention is to provide a semiconductor device having the three-dimensional structure shown. It is another object of the present technology to provide a method for manufacturing such a semiconductor device.

以上のような目的を達成するための本技術の半導体装置は、第１基板と、この第１基板に貼り合わせて設けられた第２基板とを備えている。そして特に、第１基板は、第１電極、および当該第１電極の拡散防止材料で構成され当該第１電極の周囲を覆う第１絶縁膜を含む。また第１基板は、第１電極と第１絶縁膜とで貼合せ面が構成されたものである。一方第２基板は、第１電極に接合された第２電極、および当該第２電極の拡散防止材料で構成され当該第２電極の周囲を覆う第２絶縁膜を含む。また第２基板は、第２電極と第２絶縁膜とで、第１基板に対する貼合せ面が構成されたものである。   In order to achieve the above object, a semiconductor device of the present technology includes a first substrate and a second substrate provided to be bonded to the first substrate. In particular, the first substrate includes a first electrode and a first insulating film that is made of a diffusion preventing material for the first electrode and covers the periphery of the first electrode. The first substrate has a bonding surface composed of the first electrode and the first insulating film. On the other hand, the second substrate includes a second electrode bonded to the first electrode and a second insulating film that is made of a diffusion preventing material for the second electrode and covers the periphery of the second electrode. In addition, the second substrate is configured such that the second electrode and the second insulating film constitute a bonding surface for the first substrate.

以上のような本技術によれば、電極に対する拡散防止材料で構成された絶縁膜によって電極の周囲を覆った構造であるため、絶縁膜と電極との間にバリアメタル層を設ける必要はない。このため、２枚の基板（第１基板と第２基板）の貼合せ面を、絶縁膜と電極のみで構成して接合強度を確保しつつも、電極材料の絶縁膜への拡散を防止することができる。   According to the present technology as described above, since the periphery of the electrode is covered with the insulating film made of a diffusion preventing material for the electrode, it is not necessary to provide a barrier metal layer between the insulating film and the electrode. For this reason, the bonding surface of the two substrates (the first substrate and the second substrate) is composed only of the insulating film and the electrode to ensure the bonding strength, and prevent the electrode material from diffusing into the insulating film. be able to.

さらに本技術は、上述した本技術の半導体装置の製造方法でもあり、次の手順を含む。先ず、電極材料に対する拡散防止材料で構成された絶縁膜を基板上に成膜し、当該絶縁膜に溝パターンを形成する。次に、絶縁膜に形成された溝パターンを埋め込む状態で、電極材料によって構成された電極膜を絶縁膜上に成膜する。さらに、絶縁膜が露出するまで電極膜を研磨し、溝パターン内に電極膜が埋め込まれた電極をパターン形成する。その後、以上のようにして電極が形成された２枚の基板を、当該電極同士を接合させる状態で貼り合わせる。   Furthermore, the present technology is also a manufacturing method of the semiconductor device of the present technology described above, and includes the following procedure. First, an insulating film made of a diffusion preventing material for the electrode material is formed on the substrate, and a groove pattern is formed in the insulating film. Next, an electrode film made of an electrode material is formed on the insulating film in a state where the groove pattern formed in the insulating film is embedded. Further, the electrode film is polished until the insulating film is exposed, and an electrode in which the electrode film is embedded in the groove pattern is patterned. Thereafter, the two substrates on which the electrodes are formed as described above are bonded together in a state where the electrodes are joined together.

以上説明したように本技術によれば、２枚の基板の貼り合わせによって電極間接合がなされた構成において、電極材料の拡散を防止しつつも貼り合わせ強度が確保され、これによって信頼性の向上が図られた三次元構造の半導体装置を得ることが可能になる。   As described above, according to the present technology, in the configuration in which the electrodes are bonded by bonding the two substrates, the bonding strength is ensured while preventing the diffusion of the electrode material, thereby improving the reliability. Thus, it is possible to obtain a semiconductor device having a three-dimensional structure.

本技術が適用される半導体装置の一例を示す概略構成図である。It is a schematic structure figure showing an example of a semiconductor device to which this art is applied. 実施形態の半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device of embodiment. 実施形態の半導体装置の製造におけるセンサ基板の作製手順（その１）を示す断面工程図である。It is sectional process drawing which shows the manufacture procedure (the 1) of the sensor substrate in manufacture of the semiconductor device of embodiment. 実施形態の半導体装置の製造におけるセンサ基板の作製手順（その２）を示す断面工程図である。It is sectional process drawing which shows the manufacture procedure (the 2) of the sensor substrate in manufacture of the semiconductor device of embodiment. 実施形態の半導体装置の製造における回路基板の作製手順（その１）を示す断面工程図である。It is a cross-sectional process drawing which shows the manufacturing procedure (the 1) of the circuit board in manufacture of the semiconductor device of embodiment. 実施形態の半導体装置の製造における回路基板の作製手順（その２）を示す断面工程図である。It is sectional process drawing which shows the preparation procedure (the 2) of the circuit board in manufacture of the semiconductor device of embodiment. 実施形態の半導体装置の製造における貼り合わせを示す断面図（その１）である。It is sectional drawing (the 1) which shows bonding in manufacture of the semiconductor device of embodiment. 実施形態の半導体装置の製造における貼り合わせを示す断面図（その２）である。It is sectional drawing (the 2) which shows bonding in manufacture of the semiconductor device of embodiment. 本技術の比較となる半導体装置の製造方法の一例を示す要部断面図である。It is principal part sectional drawing which shows an example of the manufacturing method of the semiconductor device used as the comparison of this technique. 本技術の変形例となる半導体装置の構成を示す要部断面図である。It is principal part sectional drawing which shows the structure of the semiconductor device used as the modification of this technique. 本技術を適用して得られた半導体装置を用いた電子機器の構成図である。It is a block diagram of the electronic device using the semiconductor device obtained by applying this technique.

以下、本技術の実施の形態を、図面に基づいて次に示す順に説明する。
１．実施形態の半導体装置の概略構成例
２．実施形態の半導体装置の構成
３．実施形態の半導体装置の製造におけるセンサ基板の作製手順
４．実施形態の半導体装置の製造における回路基板の作製手順
５．実施形態の半導体装置の製造における基板の貼り合わせ
６．実施形態の半導体装置の変形例
７．実施形態の半導体装置を用いた電子機器の一例 Hereinafter, embodiments of the present technology will be described in the following order based on the drawings.
1. 1. Example of schematic configuration of semiconductor device of embodiment 2. Configuration of Semiconductor Device of Embodiment 3. Production procedure of sensor substrate in production of semiconductor device of embodiment 4. Manufacturing procedure of circuit board in manufacturing of semiconductor device of embodiment 5. Bonding of substrates in manufacture of semiconductor device of embodiment Modification Example of Semiconductor Device of Embodiment 7 Example of electronic apparatus using semiconductor device of embodiment

≪１．実施形態の半導体装置の概略構成例≫
図１に、本技術が適用される三次元構造の半導体装置の一例として、固体撮像装置の概略構成を示す。この図に示す半導体装置１は、第１基板としてのセンサ基板２と、第２基板としての回路基板７とを含み、このセンサ基板２に対して積層させた状態で貼り合わされた第２基板としての回路基板７とを備えた、いわゆる３次元構造の半導体装置（固体撮像装置）である。以下、第１基板としてのセンサ基板２を単にセンサ基板２と称し、第２基板としての回路基板７を単に回路基板７と称する。 << 1. Example of schematic configuration of semiconductor device of embodiment >>
FIG. 1 shows a schematic configuration of a solid-state imaging device as an example of a three-dimensional structure semiconductor device to which the present technology is applied. A semiconductor device 1 shown in this figure includes a sensor substrate 2 as a first substrate and a circuit substrate 7 as a second substrate, and is attached as a second substrate laminated to the sensor substrate 2. This is a so-called three-dimensional structure semiconductor device (solid-state imaging device). Hereinafter, the sensor substrate 2 as the first substrate is simply referred to as the sensor substrate 2, and the circuit substrate 7 as the second substrate is simply referred to as the circuit substrate 7.

センサ基板２の一面側には、光電変換部を含む複数の画素３が規則的に２次元的に配列された画素領域４が設けられている。画素領域４には、複数の画素駆動線５が行方向に配線され、複数の垂直信号線６が列方向に配線されており、１つの画素３が１本の画素駆動線５と１本の垂直信号線６とに接続される状態で配置されている。これらの各画素３には、光電変換部と、電荷蓄積部と、複数のトランジスタ（いわゆるＭＯＳトランジスタ）および容量素子等で構成された画素回路とが設けられている。尚、複数の画素で画素回路の一部を共有している場合もある。   On one surface side of the sensor substrate 2, a pixel region 4 in which a plurality of pixels 3 including a photoelectric conversion unit are regularly arranged in a two-dimensional manner is provided. In the pixel region 4, a plurality of pixel drive lines 5 are wired in the row direction, and a plurality of vertical signal lines 6 are wired in the column direction. One pixel 3 has one pixel drive line 5 and one line. It is arranged in a state of being connected to the vertical signal line 6. Each of these pixels 3 is provided with a photoelectric conversion unit, a charge storage unit, and a pixel circuit composed of a plurality of transistors (so-called MOS transistors) and a capacitor element. In some cases, a plurality of pixels share a part of the pixel circuit.

また回路基板７の一面側には、センサ基板２に設けられた各画素３を駆動するための垂直駆動回路８、カラム信号処理回路９、水平駆動回路１０、およびシステム制御回路１１などの周辺回路が設けられている。   On one surface side of the circuit board 7, peripheral circuits such as a vertical drive circuit 8, a column signal processing circuit 9, a horizontal drive circuit 10, and a system control circuit 11 for driving each pixel 3 provided on the sensor board 2. Is provided.

≪２．実施形態の半導体装置の構成≫
図２は、実施形態の半導体装置の構成を示す要部断面図であり、図１における３画素分の断面図である。以下、この要部断面図に基づいて実施形態の半導体装置の詳細な構成を説明する。 ≪2. Configuration of Semiconductor Device of Embodiment >>
FIG. 2 is a cross-sectional view of a main part showing the configuration of the semiconductor device of the embodiment, and is a cross-sectional view of three pixels in FIG. Hereinafter, a detailed configuration of the semiconductor device of the embodiment will be described based on the cross-sectional view of the main part.

図２に示す半導体装置１は、上述したようにセンサ基板２と回路基板７とを積層させた状態で貼り合わせた３次元構造の固体撮像装置である。センサ基板２は、半導体層２ａと、半導体層２ａにおける回路基板７側の面上に配置された配線層２ｂおよび電極層２ｃとで構成されている。回路基板７は、半導体層７ａと、半導体層７ａにおけるセンサ基板２側の面上に配置された第１配線層７ｂ、第２配線層７ｃ、および電極層７ｄとで構成されている。   The semiconductor device 1 shown in FIG. 2 is a solid-state imaging device having a three-dimensional structure in which the sensor substrate 2 and the circuit substrate 7 are bonded together as described above. The sensor substrate 2 includes a semiconductor layer 2a, and a wiring layer 2b and an electrode layer 2c disposed on the surface of the semiconductor layer 2a on the circuit board 7 side. The circuit board 7 includes a semiconductor layer 7a, and a first wiring layer 7b, a second wiring layer 7c, and an electrode layer 7d arranged on the surface of the semiconductor layer 7a on the sensor substrate 2 side.

以上のようなセンサ基板２と回路基板７とは、電極層２ｃの表面と電極層７ｄの表面とを貼合せ面として貼り合わせられており、本実施形態においては以降に詳細に説明するように、これらの電極層２ｃおよび電極層７ｄの構成が特徴的である。   The sensor substrate 2 and the circuit substrate 7 as described above are bonded together with the surface of the electrode layer 2c and the surface of the electrode layer 7d as a bonding surface. In the present embodiment, as will be described later in detail. The structures of the electrode layer 2c and the electrode layer 7d are characteristic.

またセンサ基板２における回路基板７と反対側の面には、保護膜１５、カラーフィルタ層１７、およびオンチップレンズ１９がこの順に積層されている。   A protective film 15, a color filter layer 17, and an on-chip lens 19 are laminated in this order on the surface of the sensor substrate 2 opposite to the circuit board 7.

次に、センサ基板２および回路基板７を構成する各層の詳細な構成を順次説明し、さらに保護膜１５、カラーフィルタ層１７、およびオンチップレンズ１９の構成を順に説明する。   Next, detailed configurations of the respective layers constituting the sensor substrate 2 and the circuit substrate 7 will be sequentially described, and further, the configurations of the protective film 15, the color filter layer 17, and the on-chip lens 19 will be sequentially described.

［半導体層２ａ（センサ基板２側）］
センサ基板２側の半導体層２ａは、例えば単結晶シリコンからなる半導体基板を薄膜化したものである。この半導体層２ａにおいて、カラーフィルタ層１７やオンチップレンズ１９等が配置されている第１面側には、例えばｎ型不純物層（またはｐ型不純物層）からなる光電変換部２１が画素毎に設けられている。また、半導体層２ａの第２面側には、ｎ＋型不純物層からなるフローティングディフュージョンＦＤおよびトランジスタＴｒのソース／ドレイン２３、さらにはここでの図示を省略した他の不純物層などが設けられている。 [Semiconductor layer 2a (sensor substrate 2 side)]
The semiconductor layer 2a on the sensor substrate 2 side is obtained by thinning a semiconductor substrate made of, for example, single crystal silicon. In the semiconductor layer 2a, on the first surface side where the color filter layer 17, the on-chip lens 19 and the like are arranged, a photoelectric conversion unit 21 made of, for example, an n-type impurity layer (or a p-type impurity layer) is provided for each pixel. Is provided. On the second surface side of the semiconductor layer 2a, there are provided a floating diffusion FD composed of an n + type impurity layer, a source / drain 23 of the transistor Tr, and other impurity layers not shown here. .

[配線層２ｂ（センサ基板２側）］
センサ基板２において半導体層２ａ上に設けられた配線層２ｂは、半導体層２ａとの界面側に、ゲート絶縁膜２５を介して設けられた転送ゲートＴＧおよびトランジスタＴｒのゲート電極２７、さらにはここでの図示を省略した他の電極を有している。またこれらの転送ゲートＴＧおよびゲート電極２７は、層間絶縁膜２９で覆われており、この層間絶縁膜２９に設けられた溝パターン内にはたとえば銅（Ｃｕ）を用いた埋込配線３１が設けられている。 [Wiring layer 2b (sensor substrate 2 side)]
The wiring layer 2b provided on the semiconductor layer 2a in the sensor substrate 2 is provided on the interface side with the semiconductor layer 2a via the gate insulating film 25, the transfer gate TG and the gate electrode 27 of the transistor Tr. The other electrodes which are not shown in FIG. The transfer gate TG and the gate electrode 27 are covered with an interlayer insulating film 29, and a buried wiring 31 using, for example, copper (Cu) is provided in a groove pattern provided in the interlayer insulating film 29. It has been.

この場合、層間絶縁膜２９は、例えば酸化シリコンを用いて構成される。また、埋込配線３１のレイアウトが密である場合、埋込配線３１間の容量を低減するために酸化シリコンよりも誘電率の低い材料を用いて構成されていても良い。このような層間絶縁膜２９には、回路基板７側に開口する溝パターンが形成され、溝パターンの一部が転送ゲートＴＧやゲート電極２７に達する構成となっている。   In this case, the interlayer insulating film 29 is configured using, for example, silicon oxide. Further, when the layout of the embedded wiring 31 is dense, it may be configured using a material having a dielectric constant lower than that of silicon oxide in order to reduce the capacitance between the embedded wirings 31. In such an interlayer insulating film 29, a groove pattern that opens to the circuit board 7 side is formed, and a part of the groove pattern reaches the transfer gate TG and the gate electrode 27.

このような溝パターン内に、バリアメタル層３１ａを介して銅（Ｃｕ）からなる配線層３１ｂが設けられ、これらの２層によって埋込配線３１が構成されている。ここでバリアメタル層３１ａは、酸化シリコンやこれよりも誘電率の低い材料からなる層間絶縁膜２９に対する銅（Ｃｕ）の拡散を防止するための層であり、例えばタンタル（Ｔａ）や窒化タンタル（ＴａＮ）を用いて構成される。   In such a groove pattern, a wiring layer 31b made of copper (Cu) is provided via a barrier metal layer 31a, and the embedded wiring 31 is constituted by these two layers. Here, the barrier metal layer 31a is a layer for preventing the diffusion of copper (Cu) into the interlayer insulating film 29 made of silicon oxide or a material having a lower dielectric constant than this, for example, tantalum (Ta) or tantalum nitride ( TaN).

尚、以上のような配線層２ｂは、さらに積層された多層配線層として構成されていても良い。   The wiring layer 2b as described above may be configured as a multilayer wiring layer that is further laminated.

［電極層２ｃ（センサ基板２側）］
配線層２ｂ上に設けられたセンサ基板２側の電極層２ｃは、センサ基板２において、回路基板７側の表面に引き出された第１電極３３と、第１電極３３の周囲を覆う第１絶縁膜３５とを有している。これらの第１電極３３および第１絶縁膜３５は、センサ基板２において回路基板７に対する貼合せ面４１を構成している。 [Electrode layer 2c (sensor substrate 2 side)]
The electrode layer 2c on the sensor substrate 2 side provided on the wiring layer 2b is a first insulating layer that covers the periphery of the first electrode 33 and the first electrode 33 drawn to the surface on the circuit substrate 7 side in the sensor substrate 2. And a film 35. The first electrode 33 and the first insulating film 35 constitute a bonding surface 41 for the circuit board 7 in the sensor substrate 2.

このうち第１電極３３は、単一の材料層で構成されたもので、例えば銅（Ｃｕ）を用いて構成されている。このような第１電極３３は、第１絶縁膜３５に埋め込まれた埋込配線として構成されている。   Among these, the 1st electrode 33 is comprised by the single material layer, for example, is comprised using copper (Cu). Such a first electrode 33 is configured as an embedded wiring embedded in the first insulating film 35.

また第１絶縁膜３５は、配線層２ｂを覆う状態で設けられており、回路基板７側に開口する溝パターン３５ａを備え、この溝パターン３５ａ内に第１電極３３が埋め込まれている。つまり、第１絶縁膜３５は、第１電極３３の周囲に接して設けられている。尚、ここでの図示は省略したが、第１絶縁膜３５に設けられた溝パターン３５ａの一部は、配線層２ｂに設けた埋込配線３１に達しており、この内部に埋め込まれた第１電極３３が必要に応じて埋込配線３１に接続された状態となっている。   The first insulating film 35 is provided so as to cover the wiring layer 2b. The first insulating film 35 includes a groove pattern 35a opening on the circuit board 7 side, and the first electrode 33 is embedded in the groove pattern 35a. That is, the first insulating film 35 is provided in contact with the periphery of the first electrode 33. Although illustration is omitted here, a part of the groove pattern 35a provided in the first insulating film 35 reaches the embedded wiring 31 provided in the wiring layer 2b, and the first embedded in this inside. One electrode 33 is connected to the embedded wiring 31 as necessary.

以上のような第１絶縁膜３５は、第１電極３５を構成する材料に対する拡散防止材料で構成されている。このような拡散防止材料としては、第１電極３５を構成する材料に対する拡散係数が小さいものが用いられる。特に本実施形態においては、拡散防止材料を用いた単一の材料層として第１絶縁膜３５が構成されている。また本実施形態において、第１絶縁膜３５は、第１電極３３に対する拡散防止材料であると共に、回路基板７においてセンサ基板２側の表面に引き出された第２電極６７を構成する材料に対する拡散防止材料で構成されている。   The first insulating film 35 as described above is made of a diffusion preventing material for the material constituting the first electrode 35. As such a diffusion preventing material, a material having a small diffusion coefficient with respect to the material constituting the first electrode 35 is used. In particular, in the present embodiment, the first insulating film 35 is configured as a single material layer using a diffusion preventing material. In the present embodiment, the first insulating film 35 is a diffusion preventing material for the first electrode 33 and also prevents diffusion for the material constituting the second electrode 67 drawn to the surface of the circuit board 7 on the sensor substrate 2 side. Consists of materials.

例えば第１電極３３および第２電極６７が銅（Ｃｕ）を用いて構成されたものである場合、第１絶縁膜３５を構成する拡散防止材料としては、酸化シリコンよりも分子構造が密な無機絶縁性材料または有機絶縁性材料が用いられる。このような無機絶縁性材料としては、窒化シリコン（ＳｉＮ）、炭窒化シリコン（ＳｉＣＮ）、酸窒化シリコン（ＳｉＯＮ）、炭化シリコン（ＳｉＣ）が例示される。また有機絶縁性材料としては、ベンゾシクロブテン（ＢＣＢ）、ポリベンゾオキサゾール（ＰＢＯ）、ポリイミド、ポリアリルエーテル（ＰＡＥ）が例示される。尚、電極層２ｃは、センサ基板２側の最上層であるため、第1電極３３のレイアウトもラフである。このため、第1電極３３間に容量が付き難く、第1絶縁膜３５に対して低誘電率が求められることはない。   For example, when the first electrode 33 and the second electrode 67 are made of copper (Cu), the diffusion preventing material constituting the first insulating film 35 is an inorganic material having a molecular structure denser than that of silicon oxide. An insulating material or an organic insulating material is used. Examples of such an inorganic insulating material include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon carbide (SiC). Examples of the organic insulating material include benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide, and polyallyl ether (PAE). Since the electrode layer 2c is the uppermost layer on the sensor substrate 2 side, the layout of the first electrode 33 is also rough. For this reason, it is difficult to attach a capacitance between the first electrodes 33 and a low dielectric constant is not required for the first insulating film 35.

以上のように、センサ基板２における回路基板７側の表面は、回路基板７との貼合せ面４１として構成され、第１電極３３および第１絶縁膜３５のみで構成された状態となっている。この貼合せ面４１は、平坦化された面として構成されている。   As described above, the surface of the sensor substrate 2 on the side of the circuit board 7 is configured as the bonding surface 41 with the circuit board 7 and is configured by only the first electrode 33 and the first insulating film 35. . This bonding surface 41 is configured as a flattened surface.

［半導体層７ａ（回路基板７側）］
回路基板７側の半導体層７ａは、例えば単結晶シリコンからなる半導体基板を薄膜化したものである。この半導体層７ａにおいて、センサ基板２側の表面層には、トランジスタＴｒのソース／ドレイン５１、さらにはここでの図示を省略した不純物層などが設けられている。 [Semiconductor layer 7a (circuit board 7 side)]
The semiconductor layer 7a on the circuit board 7 side is formed by thinning a semiconductor substrate made of, for example, single crystal silicon. In the semiconductor layer 7a, the source / drain 51 of the transistor Tr, an impurity layer not shown here, and the like are provided on the surface layer on the sensor substrate 2 side.

[第１配線層７ｂ（回路基板７側）］
回路基板７側の第１配線層７ｂは、半導体層７ａとの界面側に、ゲート絶縁膜５３を介して設けられたゲート電極５５、さらにはここでの図示を省略した他の電極を有している。これらのゲート電極５５および他の電極は、層間絶縁膜５７で覆われており、この層間絶縁膜５７に設けられた溝パターン内にはたとえば銅（Ｃｕ）を用いた埋込配線５９が設けられている。 [First wiring layer 7b (circuit board 7 side)]
The first wiring layer 7b on the circuit board 7 side has a gate electrode 55 provided via a gate insulating film 53 on the interface side with the semiconductor layer 7a, and other electrodes not shown here. ing. These gate electrodes 55 and other electrodes are covered with an interlayer insulating film 57, and a buried wiring 59 using, for example, copper (Cu) is provided in a groove pattern provided in the interlayer insulating film 57. ing.

層間絶縁膜５７および埋込配線５９の構成は、センサ基板２側の配線層２ｂと同様である。すなわち、層間絶縁膜５７には、センサ基板２側に開口する溝パターンが形成され、溝パターンの一部がゲート電極５５やソース／ドレイン５１に達する構成となっている。また、このような溝パターン内に、バリアメタル層５９ａを介して銅（Ｃｕ）からなる配線層５９ｂが設けられ、これらの２層によって埋込配線５９が構成されている。   The configurations of the interlayer insulating film 57 and the embedded wiring 59 are the same as those of the wiring layer 2b on the sensor substrate 2 side. That is, in the interlayer insulating film 57, a groove pattern that opens to the sensor substrate 2 side is formed, and a part of the groove pattern reaches the gate electrode 55 and the source / drain 51. Further, in such a groove pattern, a wiring layer 59b made of copper (Cu) is provided via a barrier metal layer 59a, and the embedded wiring 59 is constituted by these two layers.

[第２配線層７ｃ（回路基板７側）］
回路基板７側の第２配線層７ｃは、第１配線層７ｂとの界面側に、拡散防止絶縁膜６１を介して積層された層間絶縁膜６３を備えている。これらの拡散防止絶縁膜６１および層間絶縁膜６３に設けられた溝パターン内にはたとえば銅（Ｃｕ）を用いた埋込配線６５が設けられている。 [Second wiring layer 7c (circuit board 7 side)]
The second wiring layer 7c on the circuit board 7 side includes an interlayer insulating film 63 laminated via a diffusion preventing insulating film 61 on the interface side with the first wiring layer 7b. An embedded wiring 65 using, for example, copper (Cu) is provided in the groove pattern provided in the diffusion preventing insulating film 61 and the interlayer insulating film 63.

拡散防止絶縁膜６１は、第１配線層７ｂに設けられた埋込配線５９を構成する材料に対する拡散防止材料で構成されている。このような拡散防止絶縁膜６１は、例えば窒化シリコン（ＳｉＮ）、炭窒化シリコン（ＳｉＣＮ）、酸窒化シリコン（ＳｉＯＮ）、炭化シリコン（ＳｉＣ）からなる。   The diffusion prevention insulating film 61 is made of a diffusion prevention material for the material constituting the embedded wiring 59 provided in the first wiring layer 7b. Such a diffusion preventing insulating film 61 is made of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon carbide (SiC).

層間絶縁膜６３および埋込配線６５の構成は、センサ基板２側の配線層２ｂと同様である。すなわち、層間絶縁膜６３には、センサ基板２側に開口する溝パターンが形成され、溝パターンの一部が第１配線層７ｂの埋込配線５９に達する構成となっている。また、このような溝パターン内に、バリアメタル層６５ａ介して銅（Ｃｕ）からなる配線層６５ｂが設けられ、これらの２層によって埋込配線６５が構成されている。   The configuration of the interlayer insulating film 63 and the embedded wiring 65 is the same as that of the wiring layer 2b on the sensor substrate 2 side. That is, the interlayer insulating film 63 is formed with a groove pattern that opens to the sensor substrate 2 side, and a part of the groove pattern reaches the embedded wiring 59 of the first wiring layer 7b. Further, in such a groove pattern, a wiring layer 65b made of copper (Cu) is provided through a barrier metal layer 65a, and the embedded wiring 65 is constituted by these two layers.

尚、以上のような第１配線層７ｂ、第２配線層７ｃは、さらに積層された多層配線層として構成されていても良い。   The first wiring layer 7b and the second wiring layer 7c as described above may be configured as a multilayer wiring layer that is further laminated.

［電極層７ｄ（回路基板７側）］
第２基板である回路基板７側の電極層７ｄは、回路基板７において、センサ基板２側の表面に引き出されて第１電極３３に接合された第２電極６７と、第２電極６７の周囲を覆う第２絶縁膜６９とを有している。これらの第２電極６７および第２絶縁膜６９は、回路基板７においてセンサ基板２に対する貼合せ面７１を構成しており、以下に説明するようにセンサ基板２側の電極層２ｃと同様に構成されている。 [Electrode layer 7d (circuit board 7 side)]
The electrode layer 7d on the circuit board 7 side, which is the second substrate, is formed on the circuit board 7 with the second electrode 67 drawn to the surface on the sensor board 2 side and joined to the first electrode 33, and the periphery of the second electrode 67. And a second insulating film 69 covering the substrate. The second electrode 67 and the second insulating film 69 constitute a bonding surface 71 for the sensor substrate 2 in the circuit substrate 7, and are configured in the same manner as the electrode layer 2c on the sensor substrate 2 side as described below. Has been.

すなわち第２電極６７は、単一の材料層で構成されたもので、センサ基板２側に設けた第１電極３３と良好な接合性が保たれる材料で構成されている。このため、第２電極６７は、第１電極３３と同一材料で構成されていて良く、例えば銅（Ｃｕ）を用いて構成されている。このような第２電極６７は、第２絶縁膜６９に埋め込まれた埋込配線として構成されている。   That is, the second electrode 67 is composed of a single material layer, and is composed of a material that maintains good bonding properties with the first electrode 33 provided on the sensor substrate 2 side. For this reason, the second electrode 67 may be made of the same material as the first electrode 33, and is made of, for example, copper (Cu). Such a second electrode 67 is configured as an embedded wiring embedded in the second insulating film 69.

また第２絶縁膜６９は、第２配線層７ｃを覆う状態で設けられており、センサ基板２側に開口する溝パターン６９ａを備え、この溝パターン６９ａ内に第２電極６７が埋め込まれている。つまり、第２絶縁膜６９は、第２電極６７の周囲に接して設けられている。尚、ここでの図示は省略したが、第２絶縁膜６９に設けられた溝パターン６９ａの一部は、下層の埋込配線６５に達しており、この内部に埋め込まれた第２電極６７が必要に応じて埋込配線６５に接続された状態となっている。   The second insulating film 69 is provided so as to cover the second wiring layer 7c, and includes a groove pattern 69a that opens to the sensor substrate 2, and the second electrode 67 is embedded in the groove pattern 69a. . That is, the second insulating film 69 is provided in contact with the periphery of the second electrode 67. Although illustration is omitted here, a part of the groove pattern 69a provided in the second insulating film 69 reaches the buried wiring 65 in the lower layer, and the second electrode 67 buried therein is formed. It is in a state of being connected to the embedded wiring 65 as necessary.

以上のような第２絶縁膜６９は、第２電極６７を構成する材料に対する拡散防止材料で構成されている。特に本実施形態においては、拡散防止材料を用いた単一の材料層として第２絶縁膜６９が構成されている。また本実施形態において、第２絶縁膜６９は、第２電極６７と共に、センサ基板２において回路基板７との貼合せ面に引き出された第１電極３３を構成する材料に対する拡散防止材料で構成されていて良い。   The second insulating film 69 as described above is made of a diffusion preventing material for the material constituting the second electrode 67. In particular, in the present embodiment, the second insulating film 69 is configured as a single material layer using a diffusion preventing material. In the present embodiment, the second insulating film 69 is made of a diffusion preventing material for the material constituting the first electrode 33 drawn to the bonding surface of the sensor substrate 2 with the circuit board 7 together with the second electrode 67. It is good.

このような第２絶縁膜６９は、センサ基板２側に設けた第１絶縁膜３５として例示した材料の中から選択した材料を用いることができる。尚、第２絶縁膜６９は、センサ基板２側における第１絶縁膜３５と良好な接合性が保たれる材料で構成されている。このため、第２絶縁膜６９は、第１絶縁膜３５と同一材料で構成されていて良い。また、電極層７ｄは、回路基板７側の最上層であるため、第２電極６７のレイアウトもラフである。このため、第２電極６７間に容量が付き難く、第２絶縁膜６９に対して低誘電率が求められることはない。   The second insulating film 69 can be made of a material selected from the materials exemplified as the first insulating film 35 provided on the sensor substrate 2 side. The second insulating film 69 is made of a material that maintains good bonding properties with the first insulating film 35 on the sensor substrate 2 side. For this reason, the second insulating film 69 may be made of the same material as the first insulating film 35. Further, since the electrode layer 7d is the uppermost layer on the circuit board 7 side, the layout of the second electrode 67 is also rough. For this reason, it is difficult to attach a capacitance between the second electrodes 67, and a low dielectric constant is not required for the second insulating film 69.

以上のように、回路基板７におけるセンサ基板２側の表面は、センサ側基板２との貼合せ面７１として構成され、第２電極６７および第２絶縁膜６９のみで構成された状態となっている。この貼合せ面７１は、平坦化された面として構成されている。   As described above, the surface on the sensor substrate 2 side of the circuit board 7 is configured as the bonding surface 71 with the sensor-side substrate 2 and is configured by only the second electrode 67 and the second insulating film 69. Yes. The bonding surface 71 is configured as a flattened surface.

［保護膜１５］
センサ基板２の光電変換部２１を覆う保護膜１５は、パッシベーション性を有する材料膜で構成され、例えば酸化シリコン膜、窒化シリコン膜、または酸窒化シリコン膜などが用いられる。 [Protective film 15]
The protective film 15 covering the photoelectric conversion portion 21 of the sensor substrate 2 is formed of a material film having passivation properties, and for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used.

［カラーフィルタ層１７］
カラーフィルタ層１７は、各光電変換部２１に対応して１：１で設けられた各色のカラーフィルタで構成されている。各色のカラーフィルタの配列が限定されることはない。 [Color filter layer 17]
The color filter layer 17 is composed of color filters of respective colors provided in a ratio of 1: 1 corresponding to the photoelectric conversion units 21. The arrangement of the color filters for each color is not limited.

［オンチップレンズ１９］
オンチップレンズ１９は、各光電変換部２１およびカラーフィルタ層１７を構成する各色のカラーフィルタに対応して１：１で設けられ、各光電変換部２１に入射光が集光されるように構成されている。 [On-chip lens 19]
The on-chip lens 19 is provided in a ratio of 1: 1 corresponding to each color filter constituting each photoelectric conversion unit 21 and the color filter layer 17, and is configured so that incident light is condensed on each photoelectric conversion unit 21. Has been.

［実施形態の半導体装置の作用効果］
以上のように構成された半導体装置１によれば、第１電極３３に対する拡散防止材料で構成された第１絶縁膜３５によって第１電極３３の周囲を覆った構造であるため、第１電極３３と第１絶縁膜３５との間にバリアメタル層を設ける必要はない。同様に、第２電極６７に対する拡散防止材料で構成された第２絶縁膜６９によって第２電極６７の周囲を覆った構造であるため、第２電極６７と第２絶縁膜６９との間にバリアメタル層を設ける必要はない。 [Operation and Effect of Semiconductor Device of Embodiment]
According to the semiconductor device 1 configured as described above, the first electrode 33 has a structure in which the first electrode 33 is covered with the first insulating film 35 made of a diffusion preventing material for the first electrode 33. There is no need to provide a barrier metal layer between the first insulating film 35 and the first insulating film 35. Similarly, since the second electrode 67 is covered with a second insulating film 69 made of a diffusion preventing material for the second electrode 67, a barrier is provided between the second electrode 67 and the second insulating film 69. There is no need to provide a metal layer.

このため、センサ基板２の貼合せ面４１と、回路基板７の貼合せ面７１とのそれぞれを、絶縁膜３５，６９と電極３３，６７のみで構成して接合強度を確保しつつ、電極３３，６７を構成する材料の絶縁膜３５，６９への拡散を防止することができる。   For this reason, each of the bonding surface 41 of the sensor substrate 2 and the bonding surface 71 of the circuit board 7 is composed of only the insulating films 35 and 69 and the electrodes 33 and 67 to ensure the bonding strength, while ensuring the bonding strength. , 67 can be prevented from diffusing into the insulating films 35, 69.

この結果、センサ基板２と回路基板７との貼り合わせによって電極３３−６７間接合がなされた三次元構造の半導体装置１において、電極材料の絶縁膜３５，６９中への拡散を防止しつつも貼り合わせ強度が確保され、信頼性の向上を図ることが可能になる。   As a result, in the semiconductor device 1 having a three-dimensional structure in which the electrodes 33 and 67 are bonded to each other by bonding the sensor substrate 2 and the circuit substrate 7, while preventing diffusion of the electrode material into the insulating films 35 and 69. The bonding strength is ensured and the reliability can be improved.

≪３．実施形態の半導体装置の製造におけるセンサ基板の作製手順≫
図３は、実施形態で説明した構成の半導体装置の製造に用いるセンサ基板の作製手順を説明するための断面工程図（その１）であり、図４は断面工程図（その２）である。以下、これらの図に基づいて実施形態に用いるセンサ基板の作製手順を説明する。 ≪3. Manufacturing Procedure of Sensor Substrate in Manufacturing Semiconductor Device of Embodiment >>
FIG. 3 is a cross-sectional process diagram (part 1) for explaining a manufacturing procedure of a sensor substrate used for manufacturing the semiconductor device having the configuration described in the embodiment, and FIG. 4 is a cross-sectional process diagram (part 2). Hereinafter, a procedure for producing a sensor substrate used in the embodiment will be described with reference to these drawings.

［図３Ａ］
先ず、図３Ａに示すように、例えば単結晶シリコンからなる半導体基板２０を用意する。この半導体基板２０の所定深さにｎ型不純物層からなる光電変換部２１を形成し、さらに光電変換部２１の表面層に、ｎ＋型不純物層からなる電荷転送部やｐ＋型不純物層からなる正孔用の電荷蓄積部を形成する。また半導体基板２０の表面層に、ｎ＋型不純物層からなるフローティングディユージョンＦＤ、およびソース／ドレイン２３、さらにはここでの図示を省略した他の不純物層を形成する。 [FIG. 3A]
First, as shown in FIG. 3A, a semiconductor substrate 20 made of, for example, single crystal silicon is prepared. A photoelectric conversion portion 21 made of an n-type impurity layer is formed at a predetermined depth of the semiconductor substrate 20, and a positive charge transfer portion made of an n + -type impurity layer and a positive electrode made of a p + -type impurity layer are further formed on the surface layer of the photoelectric conversion portion 21. A hole charge storage portion is formed. Further, on the surface layer of the semiconductor substrate 20, a floating diffusion FD composed of an n + -type impurity layer, a source / drain 23, and other impurity layers not shown here are formed.

また半導体基板２０の表面上に、ゲート絶縁膜２５を成膜し、さらにこの上部に転送ゲートＴＧおよびゲート電極２７を形成する。転送ゲートＴＧはフローティングディユージョンＦＤと光電変換部２１との間に形成され、ゲート電極２７は、ソース／ドレイン２３間に形成される。またこれと同一工程で、ここでの図示を省略した他の電極を形成する。   Further, a gate insulating film 25 is formed on the surface of the semiconductor substrate 20, and a transfer gate TG and a gate electrode 27 are further formed thereon. The transfer gate TG is formed between the floating version FD and the photoelectric conversion unit 21, and the gate electrode 27 is formed between the source / drain 23. In the same process, another electrode not shown here is formed.

その後、半導体基板２０上に、転送ゲートＴＧおよびゲート電極２７を覆う状態で、例えば酸化シリコンからなる層間絶縁膜２９を成膜する。   Thereafter, an interlayer insulating film 29 made of, for example, silicon oxide is formed on the semiconductor substrate 20 so as to cover the transfer gate TG and the gate electrode 27.

［図３Ｂ］
次に図３Ｂに示すように、層間絶縁膜２９に溝パターン２９ａを形成する。この溝パターン２９ａは、必要に応じた箇所で転送ゲートＴＧに達する形状で形成される。またここでの図示は省略したが、層間絶縁膜２９およびゲート絶縁膜２５には、必要箇所においてソース／ドレイン２３に達する溝パターンを形成する。 [FIG. 3B]
Next, as shown in FIG. 3B, a groove pattern 29 a is formed in the interlayer insulating film 29. The groove pattern 29a is formed in a shape that reaches the transfer gate TG at a location as necessary. Although not shown here, a groove pattern reaching the source / drain 23 is formed in the interlayer insulating film 29 and the gate insulating film 25 at necessary portions.

次に溝パターン２９ａの内壁を覆う状態で、バリアメタル層３１ａを成膜し、この上部に溝パターン２９ａを埋め込む状態で銅（Ｃｕ）からなる配線層３１ｂを成膜する。   Next, a barrier metal layer 31a is formed in a state of covering the inner wall of the groove pattern 29a, and a wiring layer 31b made of copper (Cu) is formed in a state of embedding the groove pattern 29a in the upper portion.

［図３Ｃ］
その後図３Ｃに示すように、化学的機械研磨（chemical mechanical polishing：以下ＣＭＰ）法によって、バリアメタル層３１ａが露出するまで配線層３１ｂを平坦化除去し、さらに、層間絶縁膜２９が露出するまでバリアメタル層３１ａを平坦化除去する。これにより、溝パターン２９ａ内にバリアメタル層３１ａを介して配線層３１ｂを埋め込んでなる埋込配線３１を形成し、埋込配線３１を備えた配線層２ｂを得る。 [FIG. 3C]
Thereafter, as shown in FIG. 3C, the wiring layer 31b is planarized and removed by a chemical mechanical polishing (CMP) method until the barrier metal layer 31a is exposed, and further until the interlayer insulating film 29 is exposed. The barrier metal layer 31a is planarized and removed. Thereby, the embedded wiring 31 is formed by embedding the wiring layer 31b in the groove pattern 29a via the barrier metal layer 31a, and the wiring layer 2b including the embedded wiring 31 is obtained.

以上までの工程は、特に工程手順が限定されることはなく、適宜選択された通常の工程手順で行えば良い。本技術では、次の工程からが特徴的な工程となる。   The steps described above are not particularly limited in the process procedure, and may be performed according to an appropriately selected normal process procedure. In the present technology, the following steps are characteristic steps.

［図４Ａ］
すなわち先ず、図４Ａに示すように、配線層２ｂ上に、第１絶縁膜３５を成膜する。第１絶縁膜３５は、次に成膜する第１電極膜を構成する材料に対する拡散防止材料を用いて成膜される。例えば第１電極膜が銅（Ｃｕ）からなる場合、第１絶縁膜３５は、酸化シリコンよりも分子構造が密な無機絶縁性材料または有機絶縁性材料が用いられる。このような無機絶縁性材料としては、窒化シリコン（ＳｉＮ）、炭窒化シリコン（ＳｉＣＮ）、酸窒化シリコン（ＳｉＯＮ）、炭化シリコン（ＳｉＣ）が例示される。また有機絶縁性材料としては、ベンゾシクロブテン（ＢＣＢ）、ポリベンゾオキサゾール（ＰＢＯ）、ポリイミド、ポリアリルエーテル（ＰＡＥ）が例示される。 [FIG. 4A]
That is, first, as shown in FIG. 4A, a first insulating film 35 is formed on the wiring layer 2b. The first insulating film 35 is formed using a diffusion preventing material for the material constituting the first electrode film to be formed next. For example, when the first electrode film is made of copper (Cu), the first insulating film 35 is made of an inorganic insulating material or an organic insulating material having a molecular structure denser than that of silicon oxide. Examples of such an inorganic insulating material include silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon carbide (SiC). Examples of the organic insulating material include benzocyclobutene (BCB), polybenzoxazole (PBO), polyimide, and polyallyl ether (PAE).

以上のような各材料からなる第１絶縁膜３５は、それぞれの材料に適する成膜方法で成膜される。例えば、無機絶縁性材料であれば、化学気相成長法（chemical vapor deposition：ＣＶＤ）が適用され、有機絶縁性材料であればＣＶＤ法や塗布法が適用される。   The first insulating film 35 made of each material as described above is formed by a film formation method suitable for each material. For example, chemical vapor deposition (CVD) is applied to inorganic insulating materials, and CVD and coating methods are applied to organic insulating materials.

次に、第１絶縁膜３５に、溝パターン３５ａを形成する。この溝パターン３５ａは、電極パッドが埋め込まれる形状を有し、ここでは図示されない必要箇所において下層の埋込配線３１に達している。   Next, a groove pattern 35 a is formed in the first insulating film 35. The groove pattern 35a has a shape in which the electrode pad is embedded, and reaches the embedded wiring 31 in the lower layer at a necessary portion (not shown).

このような溝パターン３５ａは、次のようにして形成する。例えば第１絶縁膜３５が無機絶縁材料からなるものであれば、先ずフォトリソグラフィー法によって第１絶縁膜３５上にレジストパターンを形成し、これをマスクにして第１絶縁膜３５をエッチングする。これにより溝パターン３５ａを形成する。一方、第１絶縁膜３５が有機絶縁材料からなるものであれば、先ず第１絶縁膜３５上に無機材料層を形成し、この上部にレジストパターンを形成する。次に、レジストパターンをマスクにして無機材料層をエッチングして無機マスクを形成した後、無機マスク上から第１絶縁膜３５をエッチングする。これによって溝パターン３５ａを形成し、溝パターン３５ａを形成した後に、第１絶縁膜３５上から無機マスクを除去する。   Such a groove pattern 35a is formed as follows. For example, if the first insulating film 35 is made of an inorganic insulating material, first, a resist pattern is formed on the first insulating film 35 by photolithography, and the first insulating film 35 is etched using this as a mask. Thereby, the groove pattern 35a is formed. On the other hand, if the first insulating film 35 is made of an organic insulating material, an inorganic material layer is first formed on the first insulating film 35, and a resist pattern is formed thereon. Next, the inorganic material layer is etched using the resist pattern as a mask to form an inorganic mask, and then the first insulating film 35 is etched from above the inorganic mask. Thus, the groove pattern 35a is formed. After the groove pattern 35a is formed, the inorganic mask is removed from the first insulating film 35.

［図４Ｂ］
次に図４Ｂに示すように、第１絶縁膜３５上に、溝パターン３５ａを埋め込む状態で、第１電極膜３３ａを直接成膜する。第１電極膜３３ａは、第１絶縁膜３５に対しての拡散が防止された材料からなり、例えば銅（Ｃｕ）を用いて構成される。このような第１電極膜３３ａの成膜は、例えばスパッタ法によって薄いシード層を成膜した後、このシード層を電極としたメッキ法によって行われる。 [FIG. 4B]
Next, as shown in FIG. 4B, the first electrode film 33a is directly formed on the first insulating film 35 in a state where the groove pattern 35a is embedded. The first electrode film 33a is made of a material that is prevented from diffusing into the first insulating film 35, and is made of, for example, copper (Cu). The first electrode film 33a is formed by, for example, a plating method using a seed layer as an electrode after forming a thin seed layer by sputtering.

［図４Ｃ］
次いで図４Ｃに示すように、ＣＭＰ法によって、第１絶縁膜３５が露出するまで第１絶縁膜３５上に直接成膜された第１電極膜３３ａを平坦化除去する。この際、第１絶縁膜３５を研磨ストッパとし、研磨面内において周囲に第１絶縁膜３５が露出した第１電極膜３３ａ部分から順に、研磨が自動的に停止するようなＣＭＰを行う。このようなＣＭＰは、第１電極膜３３ａが銅（Ｃｕ）に代表される化学的に活性な材料であれば良く、次のような様々な方法が例示される。 [FIG. 4C]
Next, as shown in FIG. 4C, the first electrode film 33a directly formed on the first insulating film 35 is planarized and removed by CMP until the first insulating film 35 is exposed. At this time, the first insulating film 35 is used as a polishing stopper, and CMP is performed so that polishing automatically stops in order from the first electrode film 33a portion where the first insulating film 35 is exposed in the periphery of the polishing surface. For such CMP, the first electrode film 33a may be a chemically active material typified by copper (Cu), and the following various methods are exemplified.

例えば、第１電極膜３３ａのＣＭＰによる研磨の進行によって周囲に第１絶縁膜３５が露出した部分では、研磨スラリーの局所的な温度変化や、研磨面における第１絶縁膜３３ａの占有率の局所的な変化が発生する。そこで、これらの局所的な変化を利用した化学的作用により、周囲に第１絶縁膜３５が露出した第１電極膜３３ａ部分において、局所的にＣＭＰによる研磨の進行を自動的に停止させる方法が例示される。   For example, in a portion where the first insulating film 35 is exposed to the periphery due to the progress of polishing by CMP of the first electrode film 33a, the local temperature change of the polishing slurry and the local occupation ratio of the first insulating film 33a on the polishing surface Changes occur. Therefore, there is a method of automatically stopping the progress of polishing by CMP locally in the portion of the first electrode film 33a where the first insulating film 35 is exposed by a chemical action utilizing these local changes. Illustrated.

また電極膜３３ａの表面だけを変質させ、化学的なエッチング作用を用いず、研磨パッドが接触する部分でのみ研磨を進行させる方法が例示される。この場合、第１電極膜３３ａのＣＭＰによる研磨の進行によって周囲に第１絶縁膜３５が露出した第１電極膜３３ａ部分では、第１絶縁膜３５の表面が基準面となり、それ以上研磨が進むことはない。このため、周囲に第１絶縁膜３５が露出した第１電極膜３３部分から順に、研磨が自動手に停止する。具体的には、研磨スラリーとして砥粒レスCu用研磨スラリー「HS-C430」(日立化成工業社製商品名)を用いることにより、このようなＣＭＰが行われる。   Further, there is exemplified a method in which only the surface of the electrode film 33a is denatured and the polishing is advanced only at the portion in contact with the polishing pad without using the chemical etching action. In this case, in the portion of the first electrode film 33a where the first insulating film 35 is exposed to the periphery by the progress of polishing of the first electrode film 33a by CMP, the surface of the first insulating film 35 becomes the reference surface, and polishing further proceeds. There is nothing. For this reason, the polishing is automatically stopped in order from the first electrode film 33 portion where the first insulating film 35 is exposed to the periphery. Specifically, such CMP is performed by using an abrasive-less Cu polishing slurry “HS-C430” (trade name, manufactured by Hitachi Chemical Co., Ltd.) as the polishing slurry.

以上により、溝パターン３５ａ内に第１電極膜３３ａを埋め込んでなる第１電極３３を埋込電極として形成し、第１電極３３を備えた電極層２ｃを得る。またこれにより、第１電極３３と第１絶縁膜３５とで構成された平坦な貼合せ面４１を有するセンサ基板２が、第１基板として作製される。   As described above, the first electrode 33 formed by embedding the first electrode film 33a in the groove pattern 35a is formed as an embedded electrode, and the electrode layer 2c including the first electrode 33 is obtained. Thereby, the sensor substrate 2 having the flat bonding surface 41 composed of the first electrode 33 and the first insulating film 35 is manufactured as the first substrate.

≪４．実施形態の半導体装置の製造における回路基板の作製手順≫
図５は、実施形態で説明した構成の半導体装置の製造に用いる回路基板の作製手順を説明するための断面工程図（その１）であり、図６は断面工程図（その２）である。以下、これらの図に基づいて実施形態に用いる回路基板の作製手順を説明する。 << 4. Circuit Board Manufacturing Procedure in Manufacturing Semiconductor Device of Embodiment >>
FIG. 5 is a cross-sectional process diagram (part 1) for explaining a manufacturing procedure of a circuit board used for manufacturing the semiconductor device having the configuration described in the embodiment, and FIG. 6 is a cross-sectional process diagram (part 2). A procedure for manufacturing a circuit board used in the embodiment will be described below based on these drawings.

［図５Ａ］
先ず、図５Ａに示すように、例えば単結晶シリコンからなる半導体基板５０を用意する。この半導体基板５０の表面層に、各導電型のソース／ドレイン５１、およびここでの図示を省略した他の不純物層を形成する。また半導体基板５０の表面上に、ゲート絶縁膜５３を成膜し、さらにこの上部にゲート電極５５を形成する。ゲート電極５５は、ソース／ドレイン５１間に形成される。またこれと同一工程で、ここでの図示を省略した他の電極を形成する。 [FIG. 5A]
First, as shown in FIG. 5A, a semiconductor substrate 50 made of, for example, single crystal silicon is prepared. On the surface layer of the semiconductor substrate 50, the source / drain 51 of each conductivity type and other impurity layers not shown here are formed. Further, a gate insulating film 53 is formed on the surface of the semiconductor substrate 50, and a gate electrode 55 is formed thereon. The gate electrode 55 is formed between the source / drain 51. In the same process, another electrode not shown here is formed.

その後、半導体基板５０上に、ゲート電極５５を覆う状態で、例えば酸化シリコンからなる層間絶縁膜５７を成膜する。   Thereafter, an interlayer insulating film 57 made of, for example, silicon oxide is formed on the semiconductor substrate 50 so as to cover the gate electrode 55.

次に、層間絶縁膜５７に溝パターン５７ａを形成する。この溝パターン５７ａは、必要に応じた箇所でゲート電極５５に達する形状で形成される。またここでの図示は省略したが、層間絶縁膜５７およびゲート絶縁膜５３には、必要箇所においてソース／ドレイン５１に達する溝パターンを形成する。次に溝パターン５７ａの内壁を覆う状態で、バリアメタル層５９ａを成膜し、この上部に溝パターン５７ａを埋め込む状態で銅（Ｃｕ）からなる配線層５９ｂを成膜した後、ＣＭＰによって配線層５９ｂおよびバリアメタル層５９ａを順次平坦化除去する。これにより、溝パターン５７ａ内にバリアメタル層５９ａを介して配線層５９ｂを埋め込んでなる埋込配線５９を形成し、埋込配線５９を備えた第１配線層７ｂを得る。   Next, a groove pattern 57 a is formed in the interlayer insulating film 57. The groove pattern 57a is formed in a shape that reaches the gate electrode 55 at a required position. Although illustration is omitted here, a groove pattern reaching the source / drain 51 is formed in the interlayer insulating film 57 and the gate insulating film 53 at necessary portions. Next, a barrier metal layer 59a is formed in a state in which the inner wall of the groove pattern 57a is covered, and a wiring layer 59b made of copper (Cu) is formed in a state in which the groove pattern 57a is embedded thereon, and then the wiring layer is formed by CMP. 59b and the barrier metal layer 59a are sequentially planarized and removed. Thus, an embedded wiring 59 is formed by embedding the wiring layer 59b in the groove pattern 57a via the barrier metal layer 59a, and the first wiring layer 7b having the embedded wiring 59 is obtained.

［図５Ｂ］
次に、図５Ｂに示すように、第１配線層７ｂ上に拡散防止絶縁膜６１を介して層間絶縁膜６３を積層させて成膜し、この層間絶縁膜６３および拡散防止絶縁膜６１に溝パターン６３ａする。この溝パターン６３ａは、必要に応じた箇所で下層の埋込配線５９に達して形成される。その後は、第１配線層７ｂの形成手順と同様にして、溝パターン６３ａ内にバリアメタル層６５ａを介して配線層６５ｂを埋め込んでなる埋込配線６５を形成し、第２配線層７ｃを得る。 [FIG. 5B]
Next, as shown in FIG. 5B, an interlayer insulating film 63 is deposited on the first wiring layer 7b via the diffusion preventing insulating film 61, and a groove is formed in the interlayer insulating film 63 and the diffusion preventing insulating film 61. Pattern 63a. This groove pattern 63a is formed so as to reach the buried wiring 59 in the lower layer at a place as necessary. Thereafter, in the same manner as the formation procedure of the first wiring layer 7b, an embedded wiring 65 is formed by embedding the wiring layer 65b in the groove pattern 63a through the barrier metal layer 65a, thereby obtaining the second wiring layer 7c. .

以上までの工程は、通常の工程手順で行えばよく、また特に工程手順が限定されることはなく、適宜の手順で行うことができる。本技術では、次の工程からが特徴的な工程となる。   The steps up to the above may be performed by a normal process procedure, and the process procedure is not particularly limited, and can be performed by an appropriate procedure. In the present technology, the following steps are characteristic steps.

［図５Ｃ］
すなわち先ず、図５Ｃに示すように、第２配線層７ｃ上に、第２絶縁膜６９を成膜する。第２絶縁膜６９は、次に成膜する第２電極膜を構成する材料に対する拡散防止材料を用いて成膜される。例えば第２電極膜が銅（Ｃｕ）からなる場合、第２絶縁膜６９は、先に説明したセンサ基板（２）側の第１絶縁膜（３５）と同様の材料が用いられ、同様に成膜される。 [FIG. 5C]
That is, first, as shown in FIG. 5C, a second insulating film 69 is formed on the second wiring layer 7c. The second insulating film 69 is formed using a diffusion preventing material for the material constituting the second electrode film to be formed next. For example, when the second electrode film is made of copper (Cu), the second insulating film 69 is made of the same material as the first insulating film (35) on the sensor substrate (2) side described above, and is formed in the same manner. Be filmed.

次に、第２絶縁膜６９に、溝パターン６９ａを形成する。この溝パターン６９ａは、電極パッドが埋め込まれる形状を有し、必要箇所において第２配線層７ｃに形成された埋込配線６５に達している。このような溝パターン６９ａの形成は、先に説明したセンサ基板（２）側の第１絶縁膜（３５）に形成した溝パターン３５ａと同様に形成される。   Next, a groove pattern 69 a is formed in the second insulating film 69. The groove pattern 69a has a shape in which the electrode pad is embedded, and reaches the embedded wiring 65 formed in the second wiring layer 7c at a necessary position. The groove pattern 69a is formed in the same manner as the groove pattern 35a formed in the first insulating film (35) on the sensor substrate (2) side described above.

［図６Ａ］
次に図６Ａに示すように、第２絶縁膜６９上に、溝パターン６９ａを埋め込む状態で、第２電極膜６７ａを直接成膜する。第２電極膜６７ａは、第２絶縁膜６９に対しての拡散が防止された材料からなり、例えば銅（Ｃｕ）を用いて構成される。このような第２電極膜６７ａの成膜は、例えばスパッタ法によって薄いシード層を成膜した後、このシード層を電極としたメッキ法によって行われる。 [FIG. 6A]
Next, as shown in FIG. 6A, the second electrode film 67a is directly formed on the second insulating film 69 in a state where the groove pattern 69a is embedded. The second electrode film 67a is made of a material that is prevented from diffusing into the second insulating film 69, and is made of, for example, copper (Cu). The second electrode film 67a is formed by, for example, a plating method using a seed layer as an electrode after forming a thin seed layer by sputtering.

［図６Ｂ］
次いで図６Ｂに示すように、ＣＭＰ法によって、第２絶縁膜６９が露出するまで第２電極膜６７ａを平坦化除去する。第２電極膜６７ａの平坦化は、図４Ｃを用いて説明した第１電極膜３３ａの平坦化と同様に、第２絶縁膜６９を研磨ストッパとし、研磨面内において周囲に第２絶縁膜６９が露出した第２電極膜６７ａ部分から順に、研磨が自動的に停止するようなＣＭＰによって行う。 [FIG. 6B]
Next, as shown in FIG. 6B, the second electrode film 67a is planarized and removed by CMP until the second insulating film 69 is exposed. Similar to the planarization of the first electrode film 33a described with reference to FIG. 4C, the second electrode film 67a is planarized by using the second insulating film 69 as a polishing stopper and surrounding the second insulating film 69 in the polishing surface. In order from the exposed second electrode film 67a, polishing is performed by CMP so that polishing automatically stops.

以上により、溝パターン６９ａ内に第２電極膜６７ａを埋め込んでなる第２電極６７を形成し、埋込電極としての第２電極６７を備えた電極層７ｄを得る。またこれにより、第２電極６７と第２絶縁膜６９とで構成された平坦な貼合せ面７１を有する回路基板７が、第２基板として作製される。   Thus, the second electrode 67 is formed by embedding the second electrode film 67a in the groove pattern 69a, and the electrode layer 7d provided with the second electrode 67 as the embedded electrode is obtained. Thereby, the circuit board 7 having the flat bonding surface 71 composed of the second electrode 67 and the second insulating film 69 is manufactured as the second substrate.

≪５．実施形態の半導体装置の製造における基板の貼り合わせ≫
次に図７および図８を用いて、平坦な貼合せ面４１が形成されたセンサ基板２と、平坦な貼合せ面７１が形成された回路基板７との貼り合わせ手順を説明する。 ≪5. Bonding of substrates in manufacturing of semiconductor device of embodiment >>
Next, a bonding procedure between the sensor substrate 2 on which the flat bonding surface 41 is formed and the circuit board 7 on which the flat bonding surface 71 is formed will be described with reference to FIGS. 7 and 8.

［図７］
先ず図７に示すように、上述した手順で作製したセンサ基板２と回路基板７とを、平坦な貼合せ面４１−貼合せ面７１同士を向かい合わせて対向配置する。またさらに、センサ基板２側の第１電極３３と、回路基板７側の第２電極６７とが対応するように、センサ基板２と回路基板７とを位置合わせする。図示した例では、第１電極３３と第２電極６７とが１：１で対応している状態を示したが、対応状態はこれに限定されることはない。 [Fig. 7]
First, as shown in FIG. 7, the sensor substrate 2 and the circuit substrate 7 manufactured by the above-described procedure are arranged to face each other with the flat bonding surface 41 and the bonding surface 71 facing each other. Furthermore, the sensor board 2 and the circuit board 7 are aligned so that the first electrode 33 on the sensor board 2 side corresponds to the second electrode 67 on the circuit board 7 side. In the illustrated example, a state in which the first electrode 33 and the second electrode 67 correspond 1: 1 is shown, but the correspondence state is not limited to this.

尚、センサ基板２の貼合せ面４１、および回路基板７の貼合せ面７１に対しては、必要に応じてウェット処理またはプラズマ処理による貼合せの前処理を施しておく。   Note that the bonding surface 41 of the sensor substrate 2 and the bonding surface 71 of the circuit board 7 are subjected to a pretreatment for bonding by wet treatment or plasma treatment as necessary.

［図８］
次に図８に示すように、センサ基板２と回路基板７とを、貼合せ面４１−貼合せ面７１同士を接触させて積層させる。この状態で熱処理を行うことにより、貼合せ面４１の第１電極３３と、貼合せ面７１の第２電極６７とを接合させる。貼合せ面４１の第１絶縁膜３５と貼合せ面７１の第２絶縁膜６９とを接合させる。このような熱処理は、第１電極３３と第２電極６７とを構成する材料により、センサ基板２および回路基板７に形成された素子や配線に影響のない範囲でこれらの電極３３，６７が十分に接合する温度および時間で行われる。 [Fig. 8]
Next, as shown in FIG. 8, the sensor substrate 2 and the circuit substrate 7 are laminated by bringing the bonding surface 41 and the bonding surface 71 into contact with each other. By performing heat treatment in this state, the first electrode 33 on the bonding surface 41 and the second electrode 67 on the bonding surface 71 are joined. The first insulating film 35 on the bonding surface 41 and the second insulating film 69 on the bonding surface 71 are joined. Such heat treatment is sufficient for the electrodes 33 and 67 within the range that does not affect the elements and wirings formed on the sensor substrate 2 and the circuit substrate 7 by the material constituting the first electrode 33 and the second electrode 67. Is performed at a temperature and a time for bonding.

例えば、第１電極３３および第２電極６７が、銅（Ｃｕ）を主とする材料で構成される場合、２００℃〜６００℃で１〜５時間程度の熱処理が行われる。このような熱処理は、加圧雰囲気下で行っても良く、センサ基板２と回路基板７とを両面側から押し圧した状態で行っても良い。一例として、４００℃で４時間の熱処理を行うことで、Ｃｕ−Ｃｕ接合を行う。   For example, when the 1st electrode 33 and the 2nd electrode 67 are comprised with the material which mainly has copper (Cu), the heat processing for about 1 to 5 hours are performed at 200 to 600 degreeC. Such heat treatment may be performed in a pressurized atmosphere, or may be performed in a state where the sensor substrate 2 and the circuit substrate 7 are pressed from both sides. As an example, Cu—Cu bonding is performed by performing heat treatment at 400 ° C. for 4 hours.

以上のようにしてセンサ基板２と回路基板７とを積層させ、これらの間を接合面４１−７１間で貼り合わせた後、センサ基板２側の半導体基板２０を薄膜化して半導体層２ａとし、光電変換部２１を露出させる。また必要に応じて回路基板７側の半導体基板５０を薄膜化して半導体層７ａとする。   After the sensor substrate 2 and the circuit board 7 are laminated as described above and bonded between the bonding surfaces 41-71, the semiconductor substrate 20 on the sensor substrate 2 side is thinned to form the semiconductor layer 2a. The photoelectric conversion unit 21 is exposed. If necessary, the semiconductor substrate 50 on the circuit board 7 side is thinned to form a semiconductor layer 7a.

［図２］
その後は図２に示したように、センサ基板２における光電変換部２１の露出面上に保護膜１５を成膜し、さらに保護膜１５上にカラーフィルタ層１７およびオンチップレンズ１９を形成し、半導体装置（固体撮像装置）１を完成させる。 [Figure 2]
Thereafter, as shown in FIG. 2, a protective film 15 is formed on the exposed surface of the photoelectric conversion unit 21 in the sensor substrate 2, and a color filter layer 17 and an on-chip lens 19 are formed on the protective film 15, A semiconductor device (solid-state imaging device) 1 is completed.

［実施形態の半導体装置の製造方法の作用効果］
以上説明した実施形態の製造方法によれば、図４Ｃを用いて説明したように、センサ基板２の形成において、第１絶縁膜３５上に直接成膜された第１電極膜３３ａを、第１絶縁膜３５を研磨ストッパとしたＣＭＰによって平坦化除去している。この際、周囲に第１絶縁膜３５が露出した第１電極膜３３ａ部分から順に、研磨を自動的に停止させたＣＭＰを行うことにより、研磨面の全面においてディッシングやエロージョンの発生を防止でき、平坦な研磨面を貼合せ面４１として得ることが可能になる。 [Operational Effects of Semiconductor Device Manufacturing Method of Embodiment]
According to the manufacturing method of the embodiment described above, as described with reference to FIG. 4C, in the formation of the sensor substrate 2, the first electrode film 33 a directly formed on the first insulating film 35 is formed using the first electrode film 33 a. The planarization is removed by CMP using the insulating film 35 as a polishing stopper. At this time, by performing CMP in which the polishing is automatically stopped in order from the first electrode film 33a portion where the first insulating film 35 is exposed in the periphery, it is possible to prevent the occurrence of dishing and erosion on the entire polishing surface, A flat polished surface can be obtained as the bonding surface 41.

また、図６Ｂを用いて説明した工程においても、上述と同様に平坦な研磨面を貼合せ面７１として得ることが可能になる。   Also in the process described with reference to FIG. 6B, a flat polished surface can be obtained as the bonding surface 71 as described above.

したがって、図７および図８を用いて説明した貼合せの工程においては、センサ基板２と回路基板７との貼合せを、互いに平坦な貼合せ面４１と貼合せ面７１との間で行うことができる。これにより、貼合せ面４１−貼合せ面７１の全面間で、良好な電極３３−６７間接合がなされた貼合せが行われ、センサ基板２と回路基板７との貼り合わせ強度を保つことが可能になる。   Therefore, in the bonding process described with reference to FIGS. 7 and 8, the sensor substrate 2 and the circuit board 7 are bonded between the flat bonding surface 41 and the bonding surface 71. Can do. Thereby, the bonding in which the good bonding between the electrodes 33 and 67 is performed between the entire surface of the bonding surface 41 and the bonding surface 71, and the bonding strength between the sensor substrate 2 and the circuit substrate 7 can be maintained. It becomes possible.

さらに、センサ基板２側の貼合せ面４１を構成する第１絶縁膜３５は、第１電極３３に対する拡散防止材料で構成されている。このため、第１絶縁膜３５への第１電極３３の拡散を防止できる。同様に、回路基板７側の貼合せ面７１を構成する第２絶縁膜６９は、第２電極６７に対する拡散防止材料で構成されている。このため、第２電極６７の第２絶縁膜６９への拡散を防止できる。したがって、上述したような電極３３−６７間の接合強度を保った貼り合わせを実現可能な構成となっている。   Furthermore, the first insulating film 35 constituting the bonding surface 41 on the sensor substrate 2 side is made of a diffusion preventing material for the first electrode 33. For this reason, the diffusion of the first electrode 33 into the first insulating film 35 can be prevented. Similarly, the second insulating film 69 constituting the bonding surface 71 on the circuit board 7 side is made of a diffusion preventing material for the second electrode 67. For this reason, the diffusion of the second electrode 67 into the second insulating film 69 can be prevented. Accordingly, it is possible to realize the bonding while maintaining the bonding strength between the electrodes 33-67 as described above.

しかも、回路基板７側の第２電極６７に対する拡散防止材料によってセンサ基板２側の第１絶縁膜３５を構成し、センサ基板２側の第１電極３３に対する拡散防止材料によって回路基板７側の第２絶縁膜６９を構成する。これにより、センサ基板２と回路基板７との間での電極材料の相互拡散をも防止できる。   In addition, the first insulating film 35 on the sensor substrate 2 side is configured by the diffusion preventing material for the second electrode 67 on the circuit board 7 side, and the first insulating film 35 on the circuit board 7 side is formed by the diffusion preventing material for the first electrode 33 on the sensor substrate 2 side. Two insulating films 69 are formed. Thereby, the mutual diffusion of the electrode material between the sensor substrate 2 and the circuit substrate 7 can also be prevented.

加えて、センサ基板２側の貼合せ面４１が第１電極３３と第１絶縁膜３５のみで構成され、回路基板７側の貼合せ面７１が第２電極６７と第２絶縁膜６９のみで構成されている。このため、化学的に不活性で接合強度を保ち難いバリアメタル層によって貼合せ面４１，７１が構成されることはなく、貼合せ面の構成が単純化され、これによっても接合強度を保つことが可能になる。   In addition, the bonding surface 41 on the sensor substrate 2 side includes only the first electrode 33 and the first insulating film 35, and the bonding surface 71 on the circuit substrate 7 side includes only the second electrode 67 and the second insulating film 69. It is configured. For this reason, the bonding surfaces 41 and 71 are not constituted by the barrier metal layer that is chemically inert and does not easily maintain the bonding strength, and the configuration of the bonding surfaces is simplified, and the bonding strength is also maintained by this. Is possible.

ここで図９には、比較例となる半導体装置の製造手順を示す。図９に示した比較例の手順は、次のように行う。   Here, FIG. 9 shows a manufacturing procedure of a semiconductor device as a comparative example. The procedure of the comparative example shown in FIG. 9 is performed as follows.

先ず図９Ａに示すように、一方の基板表面を覆う第１絶縁膜１０１に溝パターン１０１ａを形成し、この溝パターン１０１ａに沿って電極材料に対するバリアメタル層１０２を成膜した後、この上部に銅（Ｃｕ）からなる第１電極膜１０３ａを成膜する。次いで図９Ｂに示すように、第１電極膜１０３ａをＣＭＰによって平坦化除去し、バリアメタル層１０２を露出させる。この際、バリアメタル層１０２を研磨ストッパとしたＣＭＰを行う。またこのＣＭＰにおいては、研磨面内において周囲にバリアメタル層１０２が露出した第１電極膜１０３ａ部分から順に、研磨が自動的に停止するようなＣＭＰを行う。   First, as shown in FIG. 9A, a groove pattern 101a is formed in a first insulating film 101 covering one substrate surface, and a barrier metal layer 102 for an electrode material is formed along the groove pattern 101a. A first electrode film 103a made of copper (Cu) is formed. Next, as shown in FIG. 9B, the first electrode film 103a is planarized and removed by CMP, and the barrier metal layer 102 is exposed. At this time, CMP is performed using the barrier metal layer 102 as a polishing stopper. Further, in this CMP, CMP is performed such that polishing automatically stops in order from the first electrode film 103a portion where the barrier metal layer 102 is exposed in the polishing surface.

その後、図９Ｃに示すように、バリアメタル層１０２を研磨によって平坦化除去し、第１絶縁膜１０１を露出させる。以上により、第１絶縁膜１０１の溝パターン１０１ａ内に、バリアメタル層１０２を介して銅（Ｃｕ）からなる第１電極膜１０３ａが埋め込まれた第１電極１０３を形成する。   Thereafter, as shown in FIG. 9C, the barrier metal layer 102 is planarized and removed by polishing, and the first insulating film 101 is exposed. Thus, the first electrode 103 is formed in which the first electrode film 103a made of copper (Cu) is embedded in the groove pattern 101a of the first insulating film 101 with the barrier metal layer 102 interposed therebetween.

一方、図９Ａ’〜図９Ｃ’に示すように、他方の基板の表面側にも、同様の手順で第２絶縁膜２０１の溝パターン２０１ａ内に、バリアメタル層２０２を介して銅（Ｃｕ）からなる第２電極膜２０３ａが埋め込まれた第２電極２０３を形成する。   On the other hand, as shown in FIGS. 9A ′ to 9C ′, copper (Cu) is also formed on the surface of the other substrate in the groove pattern 201a of the second insulating film 201 through the barrier metal layer 202 in the same procedure. A second electrode 203 in which a second electrode film 203a made of is embedded is formed.

その後は、図９Ｄに示すように、それぞれの研磨面を対向配置し、第１電極１０３と第２電極２０３とを対応させて接合させ、２つの基板の貼合せを行う。   Thereafter, as shown in FIG. 9D, the respective polished surfaces are arranged to face each other, and the first electrode 103 and the second electrode 203 are bonded to each other so as to bond the two substrates.

このような比較例の手順では、図９Ｂから図９Ｃに至るバリアメタル層１０２と第１電極膜１０３ａの研磨において、化学的に活性である銅（Ｃｕ）からなる第１電極膜１０３ａの急激な露出面積の変化が生じることがない。このため、周囲に第１絶縁膜１０１が露出した第１電極膜１０３ａ部分から順に、研磨を自動的に停止させるＣＭＰを行うことはできない。したがって、研磨面内においてのディッシングやエロージョンの発生を防止できず、平坦な研磨面を得ることが困難である。これは、図９Ｃ’に示される工程も同様である。   In the procedure of such a comparative example, in the polishing of the barrier metal layer 102 and the first electrode film 103a from FIG. 9B to FIG. 9C, the first electrode film 103a made of chemically active copper (Cu) is rapidly applied. There is no change in the exposed area. For this reason, it is not possible to perform CMP in which polishing is automatically stopped sequentially from the first electrode film 103a portion where the first insulating film 101 is exposed in the periphery. Therefore, it is difficult to prevent dishing or erosion from occurring on the polished surface, and it is difficult to obtain a flat polished surface. The same applies to the process shown in FIG. 9C '.

しがたって、図９Ｄに示したように、平坦性に劣る研磨面同士を対向させて基板同士貼り合わせても、十分な貼合せ強度を得ることはできず、しかも第１電極１０３と第２電極２０３との接合強度も十分に得ることはできない。   Accordingly, as shown in FIG. 9D, even if the polished surfaces having poor flatness are opposed to each other and the substrates are bonded to each other, sufficient bonding strength cannot be obtained, and the first electrode 103 and the second electrode A sufficient bonding strength with the electrode 203 cannot be obtained.

また、図９Ｃに示した研磨面は、第１絶縁膜１０１、バリアメタル層１０２、および第１電極１０３で構成される。一方、図９Ｃ’に示した研磨面も、第２絶縁膜２０１、バリアメタル層２０２、および第２電極２０３で構成される。このため、研磨面同士の貼合せ界面には、第１絶縁膜１０１および第１電極１０３とバリアメタル層２０２との接合界面、第２絶縁膜２０１および第２電極２０３とバリアメタル層１０２との接合界面も発生する。しかしながら、バリアメタル層１０２，２０２は、化学的に不活性であるため、貼合せ際にしてのプラズマ処理やウェット処理での前処理が困難である。このため貼合せ面においてバリアメタル層１０２，２０２が露出している部分では、接合強度を得ることができず、基板同士の貼合せ強度の低下を招く要因になる。   9C includes the first insulating film 101, the barrier metal layer 102, and the first electrode 103. On the other hand, the polished surface shown in FIG. 9C ′ is also composed of the second insulating film 201, the barrier metal layer 202, and the second electrode 203. For this reason, the bonding interface between the polished surfaces is the bonding interface between the first insulating film 101 and the first electrode 103 and the barrier metal layer 202, and the second insulating film 201 and the second electrode 203 and the barrier metal layer 102. A bonding interface is also generated. However, since the barrier metal layers 102 and 202 are chemically inactive, it is difficult to perform pretreatment by plasma treatment or wet treatment at the time of bonding. For this reason, in the part where the barrier metal layers 102 and 202 are exposed on the bonding surface, the bonding strength cannot be obtained, which causes a decrease in the bonding strength between the substrates.

以上のような比較例に対して、図２に示した本実施形態の半導体装置では、第１電極３３および第１絶縁膜３５、第２電極６７および第２絶縁膜６９の、それぞれ２種類に単純化された平坦な貼合せ面４１と貼合せ面７１との間で貼合せが行われる。そして、第１電極３３−第２電極６７間、第１絶縁膜３５−第２絶縁膜６９間、第１電極３３−第２絶縁膜６９間、および第２電極−第１絶縁膜３５間は、それぞれ十分な接合強度を得ることが可能である。このためセンサ基板（第１基板）２−回路基板（第２基板）７間には、十分な貼合せ強度を得ることが可能なのである。   In contrast to the comparative example as described above, in the semiconductor device of this embodiment shown in FIG. 2, the first electrode 33 and the first insulating film 35, the second electrode 67 and the second insulating film 69 are divided into two types, respectively. Bonding is performed between the simplified flat bonding surface 41 and the bonding surface 71. Between the first electrode 33 and the second electrode 67, between the first insulating film 35 and the second insulating film 69, between the first electrode 33 and the second insulating film 69, and between the second electrode and the first insulating film 35. It is possible to obtain a sufficient bonding strength. For this reason, a sufficient bonding strength can be obtained between the sensor substrate (first substrate) 2 and the circuit substrate (second substrate) 7.

≪６．実施形態の半導体装置の変形例≫
図１０は、実施形態の変形例となる半導体装置の要部断面図である。この図に示すように、第1基板としてのセンサ基板２には、層間絶縁膜３５-1と拡散防止絶縁膜３５-2とを用いた第1絶縁膜３５’を設けても良い。この場合、例えば酸化シリコンや低誘電率材料を用いた層間絶縁膜３５-1に、溝パターン３５ａが設けられ、この溝パターン３５ａの内壁を含む層間絶縁膜３５-1上を覆う状態で、拡散防止絶縁膜３５-2が設けられている。そして、溝パターン３５ａ内に、拡散防止絶縁膜３５-2を介して第１電極３３が設けられている。これにより、第１電極３３の周囲は拡散防止絶縁膜３５-2で囲まれ、第１電極３３と拡散防止絶縁膜３５-2とで貼合せ面４１が構成された状態となっている。 ≪6. Modified Example of Semiconductor Device of Embodiment >>
FIG. 10 is a cross-sectional view of a main part of a semiconductor device which is a modification of the embodiment. As shown in this figure, the sensor substrate 2 as the first substrate may be provided with a first insulating film 35 ′ using an interlayer insulating film 35-1 and a diffusion preventing insulating film 35-2. In this case, for example, a groove pattern 35a is provided in the interlayer insulating film 35-1 using silicon oxide or a low dielectric constant material, and diffusion is performed while covering the interlayer insulating film 35-1 including the inner wall of the groove pattern 35a. A prevention insulating film 35-2 is provided. A first electrode 33 is provided in the groove pattern 35a via a diffusion prevention insulating film 35-2. Thereby, the periphery of the first electrode 33 is surrounded by the diffusion preventing insulating film 35-2, and the bonding surface 41 is configured by the first electrode 33 and the diffusion preventing insulating film 35-2.

また第２基板としての回路基板７にも、同様にして層間絶縁膜６９-1と拡散防止絶縁膜６９-2とを用いた第２絶縁膜６９’を設けても良い。これにより、第２電極６７の周囲は拡散防止絶縁膜６９-2で囲まれ、第２電極６７と拡散防止絶縁膜６９-2とで貼合せ面７１が構成された状態となっている。   Similarly, a second insulating film 69 ′ using the interlayer insulating film 69-1 and the diffusion prevention insulating film 69-2 may be provided on the circuit board 7 as the second substrate. Thereby, the periphery of the second electrode 67 is surrounded by the diffusion preventing insulating film 69-2, and the bonding surface 71 is constituted by the second electrode 67 and the diffusion preventing insulating film 69-2.

このような構成の半導体装置１’であっても、センサ基板２の貼合せ面４１と、回路基板７の貼合せ面７１とを、拡散防止絶縁膜３５-2，６９-2と電極３３，６７のみで構成して接合強度を確保することが可能である。しかも、電極３３，６７を構成する材料の層間絶縁膜３５-1，６９-1への拡散を防止することができる。   Even in the semiconductor device 1 ′ having such a configuration, the bonding surface 41 of the sensor substrate 2 and the bonding surface 71 of the circuit board 7 are connected to the diffusion prevention insulating films 35-2 and 69-2 and the electrode 33. It is possible to ensure the bonding strength by constituting only 67. In addition, it is possible to prevent the material constituting the electrodes 33 and 67 from diffusing into the interlayer insulating films 35-1 and 69-1.

この結果、２枚の基板２−７の貼り合わせによって第１電極３３−第２電極６７間の接合がなされた三次元構造の半導体装置１’において、電極材料の拡散を防止しつつも貼り合わせ強度が確保され、信頼性の向上を図ることが可能になる。   As a result, in the semiconductor device 1 ′ having a three-dimensional structure in which the first electrode 33 and the second electrode 67 are bonded by bonding the two substrates 2-7, bonding is performed while preventing diffusion of the electrode material. Strength is ensured and reliability can be improved.

また以上のような構成の半導体装置1’の製造において、第1基板であるセンサ基板２を作製する場合、拡散防止絶縁膜３５-2をストッパにして第１電極３３を構成する膜をＣＭＰによって研磨すれば良い。このため、拡散防止絶縁膜３５-2が露出した時点を研磨の終点として正確に検出することができ、ディッシングを発生させることなくＣＭＰを終了させて平坦な研磨面を貼合せ面４１として得ることが可能になる。   In the manufacture of the semiconductor device 1 ′ having the above-described configuration, when the sensor substrate 2 as the first substrate is manufactured, the film constituting the first electrode 33 is formed by CMP using the diffusion prevention insulating film 35-2 as a stopper. It only has to be polished. For this reason, it is possible to accurately detect the time when the diffusion preventing insulating film 35-2 is exposed as an end point of polishing, and to finish the CMP without causing dishing to obtain a flat polished surface as the bonding surface 41. Is possible.

また第２基板である回路基板７を作製する場合も同様に、拡散防止絶縁膜６９-2をストッパにして第２電極６７を構成する膜をＣＭＰによって研磨すれば良い。このため、同様に平坦な研磨面を貼合せ面７１として得ることが可能になる。   Similarly, when the circuit board 7 which is the second substrate is manufactured, the film constituting the second electrode 67 may be polished by CMP using the diffusion prevention insulating film 69-2 as a stopper. For this reason, a flat polished surface can be obtained as the bonding surface 71 in the same manner.

この結果、先の実施形態の製造方法と同様に、貼合せ面４１−貼合せ面７１の全面間で接合がなされた貼り合わせが行われ、センサ基板２と回路基板７との貼り合わせ強度を保つことが可能になる。しかも、回路基板７側の第２電極６７に対する拡散防止材料によってセンサ基板２側の拡散防止絶縁膜３５-2を構成し、センサ基板２側の第１電極３３に対する拡散防止材料によって回路基板７側の拡散防止絶縁膜６９-2を構成しても良い。これにより、センサ基板２と回路基板７との間での電極材料の拡散をも防止できる。加えて、センサ基板２側の貼合せ面４１が第１電極３３と拡散防止絶縁膜３５-2のみで構成され、回路基板７側の貼合せ面７１が第２電極６７と拡散防止絶縁膜６９-2のみで構成されている。このため、貼合せ面の構成が単純化され、これによっても接合強度を保つことが可能になる。   As a result, similarly to the manufacturing method of the previous embodiment, bonding is performed between the entire surfaces of the bonding surface 41 and the bonding surface 71, and the bonding strength between the sensor substrate 2 and the circuit substrate 7 is increased. It becomes possible to keep. In addition, the diffusion prevention insulating film 35-2 on the sensor substrate 2 side is configured by the diffusion prevention material for the second electrode 67 on the circuit board 7 side, and the circuit board 7 side is formed by the diffusion prevention material for the first electrode 33 on the sensor board 2 side. The diffusion prevention insulating film 69-2 may be configured. Thereby, diffusion of the electrode material between the sensor substrate 2 and the circuit substrate 7 can also be prevented. In addition, the bonding surface 41 on the sensor substrate 2 side includes only the first electrode 33 and the diffusion preventing insulating film 35-2, and the bonding surface 71 on the circuit board 7 side includes the second electrode 67 and the diffusion preventing insulating film 69. It consists only of -2. For this reason, the structure of a bonding surface is simplified and it becomes possible to maintain joining strength also by this.

≪７．実施形態の半導体装置を用いた電子機器の一例≫
上述の実施形態で説明した本技術に係る半導体装置（固体撮像装置）は、例えばデジタルカメラやビデオカメラ等のカメラシステム、さらには撮像機能を有する携帯電話、あるいは撮像機能を備えた他の機器などの電子機器に適用することができる。 ≪7. Example of Electronic Device Using Semiconductor Device of Embodiment >>
The semiconductor device (solid-state imaging device) according to the present technology described in the above-described embodiments is, for example, a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or other equipment having an imaging function. It can be applied to other electronic devices.

図１１は、本技術に係る電子機器の一例として、固体撮像装置を用いたカメラの構成図を示す。本実施形態例に係るカメラは、静止画像又は動画撮影可能なビデオカメラを例としたものである。このカメラ９０は、固体撮像装置９１と、固体撮像装置９１の受光センサ部に入射光を導く光学系９３と、シャッタ装置９４と、固体撮像装置９１を駆動する駆動回路９５と、固体撮像装置９１の出力信号を処理する信号処理回路９６とを有する。   FIG. 11 is a configuration diagram of a camera using a solid-state imaging device as an example of an electronic apparatus according to the present technology. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 90 includes a solid-state imaging device 91, an optical system 93 that guides incident light to the light receiving sensor unit of the solid-state imaging device 91, a shutter device 94, a drive circuit 95 that drives the solid-state imaging device 91, and the solid-state imaging device 91. And a signal processing circuit 96 for processing the output signal.

固体撮像装置９１は、上述した実施形態および変形例で説明した構成の半導体装置（１，１’）が適用される。光学系（光学レンズ）９３は、被写体からの像光（入射光）を固体撮像装置９１の撮像面上に結像させる。これにより、固体撮像装置９１内に、一定期間信号電荷が蓄積される。このような光学系９３は、複数の光学レンズから構成された光学レンズ系としても良い。シャッタ装置９４は、固体撮像装置９１への光照射期間及び遮光期間を制御する。駆動回路９５は、固体撮像装置９１及びシャッタ装置９４に駆動信号を供給し、供給した駆動信号（タイミング信号）により、固体撮像装置９１の信号処理回路９６への信号出力動作の制御、およびシャッタ装置９４のシャッタ動作を制御する。すなわち、駆動回路９５は、駆動信号（タイミング信号）の供給により、固体撮像装置９１から信号処理回路９６への信号転送動作を行う。信号処理回路９６は、固体撮像装置９１から転送された信号に対して、各種の信号処理を行う。信号処理が行われた映像信号は、メモリなどの記憶媒体に記憶され、或いは、モニタに出力される。   As the solid-state imaging device 91, the semiconductor device (1, 1 ') having the configuration described in the above-described embodiments and modifications is applied. The optical system (optical lens) 93 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 91. Thereby, signal charges are accumulated in the solid-state imaging device 91 for a certain period. Such an optical system 93 may be an optical lens system including a plurality of optical lenses. The shutter device 94 controls the light irradiation period and the light shielding period for the solid-state imaging device 91. The drive circuit 95 supplies drive signals to the solid-state imaging device 91 and the shutter device 94, and controls the signal output operation to the signal processing circuit 96 of the solid-state imaging device 91 and the shutter device by the supplied drive signal (timing signal). 94 shutter operation is controlled. That is, the drive circuit 95 performs a signal transfer operation from the solid-state imaging device 91 to the signal processing circuit 96 by supplying a drive signal (timing signal). The signal processing circuit 96 performs various signal processing on the signal transferred from the solid-state imaging device 91. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

以上説明した本実施形態に係る電子機器によれば、センサ基板と回路基板とを積層させた信頼性の高い３次元構造の半導体装置１を固体撮像装置として用いたことにより、撮像機能を有する電子機器の小型化および信頼性の向上を図ることが可能になる。   According to the electronic device according to the present embodiment described above, an electronic device having an imaging function is obtained by using the highly reliable three-dimensional semiconductor device 1 in which a sensor substrate and a circuit board are stacked as a solid-state imaging device. It becomes possible to reduce the size of the device and improve the reliability.

尚、本技術は以下のような構成も取ることができる。
（１）
第１電極、および当該第１電極の拡散防止材料で構成され当該第１電極の周囲を覆う第１絶縁膜を含むと共に、当該第１電極と当該第１絶縁膜とで貼合せ面が構成された第１基板と、
前記第１基板に貼り合わせて設けられ、前記第１電極に接合された第２電極、および当該第２電極の拡散防止材料で構成され当該第２電極の周囲を覆う第２絶縁膜を含むと共に、当該第２電極と当該第２絶縁膜とで前記第１基板に対する貼合せ面が構成された第２基板とを備えた
半導体装置。 In addition, this technique can also take the following structures.
(1)
The first electrode includes a first insulating film that is made of a diffusion preventing material for the first electrode and covers the periphery of the first electrode, and a bonding surface is formed by the first electrode and the first insulating film. A first substrate,
A second electrode provided on the first substrate and bonded to the first electrode; and a second insulating film made of a diffusion preventing material for the second electrode and covering the periphery of the second electrode. A semiconductor device comprising: a second substrate in which a bonding surface for the first substrate is configured by the second electrode and the second insulating film.

（２）
前記第１電極と前記第２電極とは、それぞれが単一の材料層で構成されている
（１）記載の半導体装置。 (2)
The semiconductor device according to (1), wherein each of the first electrode and the second electrode is formed of a single material layer.

（３）
前記第１基板の貼合せ面と前記第２基板の貼合せ面は、それぞれが平坦化された面として構成されている
（１）または（２）記載の半導体装置。 (3)
The semiconductor device according to (1) or (2), wherein the bonding surface of the first substrate and the bonding surface of the second substrate are configured as flat surfaces.

（４）
前記第１電極は、前記第１絶縁膜に形成された溝パターン内に埋め込まれ、
前記第２電極は、前記第２絶縁膜に形成された溝パターン内に埋め込まれている
（１）〜（３）の何れかに記載の半導体装置。 (4)
The first electrode is embedded in a groove pattern formed in the first insulating film,
The semiconductor device according to any one of (1) to (3), wherein the second electrode is embedded in a groove pattern formed in the second insulating film.

（５）
前記第１基板の貼合せ面は、前記第１電極および前記第１絶縁膜のみで構成され、
前記第２基板の貼合せ面は、前記第２電極および前記第２絶縁膜のみで構成されている
（１）〜（４）の何れかに記載の半導体装置。 (5)
The bonding surface of the first substrate is composed only of the first electrode and the first insulating film,
The bonding surface of the second substrate includes only the second electrode and the second insulating film. The semiconductor device according to any one of (1) to (4).

（６）
前記第１絶縁膜は、前記第１電極と共に前記第２電極を構成する材料に対する拡散防止材料で構成され、
前記第２絶縁膜は、前記第２電極と共に前記第１電極を構成する材料に対する拡散防止材料で構成される
（１）〜（５）の何れかに記載の半導体装置。 (6)
The first insulating film is made of a diffusion preventing material for a material constituting the second electrode together with the first electrode,
The semiconductor device according to any one of (1) to (5), wherein the second insulating film is formed of a diffusion prevention material for a material forming the first electrode together with the second electrode.

（７）
前記第１電極と前記第２電極とは同一材料で構成されている
（１）〜（６）の何れかに記載の半導体装置。 (7)
The semiconductor device according to any one of (1) to (6), wherein the first electrode and the second electrode are made of the same material.

（８）
前記第１絶縁膜と前記第２絶縁膜とは同一材料で構成されている
（１）〜（７）の何れかに記載の半導体装置。 (8)
The semiconductor device according to any one of (1) to (7), wherein the first insulating film and the second insulating film are made of the same material.

（９）
電極材料に対する拡散防止材料で構成された絶縁膜を基板上に成膜し、当該絶縁膜に溝パターンを形成することと、
前記絶縁膜に形成された溝パターンを埋め込む状態で前記電極材料によって構成された電極膜を当該絶縁膜上に成膜することと、
前記絶縁膜が露出するまで前記電極膜を研磨し、前記溝パターン内に当該電極膜が埋め込まれた電極をパターン形成することと、
前記電極が形成された２枚の前記基板を、当該電極同士を接合させる状態で貼り合わせることとを行う
半導体装置の製造方法。 (9)
Forming an insulating film made of a diffusion preventing material for the electrode material on the substrate, and forming a groove pattern in the insulating film;
Forming an electrode film made of the electrode material on the insulating film in a state of embedding the groove pattern formed in the insulating film;
Polishing the electrode film until the insulating film is exposed, patterning an electrode in which the electrode film is embedded in the groove pattern;
A method for manufacturing a semiconductor device, comprising: bonding the two substrates on which the electrodes are formed in a state in which the electrodes are bonded together.

（１０）
前記電極をパターン形成する際には、前記絶縁膜をストッパにした化学的機械研磨を行う
（９）記載の半導体装置の製造方法。 (10)
(9) The method for manufacturing a semiconductor device according to (9), wherein when the electrode is patterned, chemical mechanical polishing is performed using the insulating film as a stopper.

（１１）
前記電極をパターン形成する際には、前記電極膜の研磨によって前記絶縁膜が周囲に露出した当該電極膜部分から順に、研磨が自動的に停止するような化学的機械研磨を行う
（９）または（１０）記載の半導体装置の製造方法。 (11)
When patterning the electrode, chemical mechanical polishing is performed so that polishing automatically stops in order from the electrode film portion where the insulating film is exposed to the surroundings by polishing the electrode film (9) or (10) A method for manufacturing a semiconductor device according to (10).

１，１’…半導体装置、２…センサ基板（第１基板）、７…回路基板（第２基板）、３３…第１電極、３３ａ…第１電極膜、３５，３５’…第１絶縁膜、３５ａ…溝パターン（第１基板側）、３５-1…層間絶縁膜（第１絶縁膜）、３５-2…拡散防止絶縁膜（第1絶縁膜）、４１…貼合せ面（第１基板側）、６７…第２電極、６７ａ…第２電極膜、６９，６９’…第２絶縁膜、６９ａ…溝パターン（第２基板側）、６９-1…層間絶縁膜（第２絶縁膜）、６９-2…拡散防止絶縁膜（第２絶縁膜）、７１…貼合せ面   DESCRIPTION OF SYMBOLS 1,1 '... Semiconductor device, 2 ... Sensor board | substrate (1st board | substrate), 7 ... Circuit board (2nd board | substrate), 33 ... 1st electrode, 33a ... 1st electrode film, 35, 35' ... 1st insulating film , 35a ... groove pattern (first substrate side), 35-1 ... interlayer insulating film (first insulating film), 35-2 ... diffusion preventing insulating film (first insulating film), 41 ... bonding surface (first substrate) Side), 67 ... second electrode, 67a ... second electrode film, 69, 69 '... second insulating film, 69a ... groove pattern (second substrate side), 69-1 ... interlayer insulating film (second insulating film) 69-2 ... Diffusion-preventing insulating film (second insulating film), 71 ... Bonding surface

Claims (13)

第１基板と第２基板とが、それぞれの貼合せ面で貼り合わせられた半導体装置であって、
前記第１基板の貼合せ面は、第１電極と、当該第１電極の拡散防止材料からなり当該貼合せ面から当該第１電極の周囲を連続して覆う第１絶縁膜とで構成され、
前記第２基板の貼合せ面は、前記第１電極に接合された第２電極と、当該第２電極の拡散防止材料からなり当該貼合せ面から当該第２電極の周囲を連続して覆う第２絶縁膜とで構成された
半導体装置。 The first substrate and the second substrate, a semiconductor device canceller Awa attached at each lamination surface,
The bonding surface of the first substrate includes a first electrode and a first insulating film made of a diffusion preventing material for the first electrode and continuously covering the periphery of the first electrode from the bonding surface.
The bonding surface of the second substrate is made of a second electrode joined to the first electrode and a diffusion preventing material for the second electrode, and continuously covers the periphery of the second electrode from the bonding surface. A semiconductor device composed of two insulating films. 前記第１電極と前記第２電極とは、それぞれが単一の材料層で構成されている
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein each of the first electrode and the second electrode is formed of a single material layer. 前記第１基板の貼合せ面と前記第２基板の貼合せ面は、それぞれが平坦化された面として構成されている
請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the bonding surface of the first substrate and the bonding surface of the second substrate are configured as flat surfaces. 前記第１電極は、前記第１絶縁膜に形成された溝パターン内に埋め込まれ、
前記第２電極は、前記第２絶縁膜に形成された溝パターン内に埋め込まれている
請求項１〜３の何れかに記載の半導体装置。 The first electrode is embedded in a groove pattern formed in the first insulating film,
The semiconductor device according to claim 1, wherein the second electrode is embedded in a groove pattern formed in the second insulating film. 前記第１電極が埋め込まれた溝パターンを有する第１層間絶縁膜と、前記第２電極が埋め込まれた溝パターンを有する第２層間絶縁膜とを備え、
前記第１絶縁膜は、前記第１層間絶縁膜の溝パターンの内壁を含む当該第１層間絶縁膜上を覆う状態で設けられ、
前記第２絶縁膜は、前記第２層間絶縁膜の溝パターンの内壁を含む当該第２層間絶縁膜上を覆う状態で設けられた
請求項１〜３の何れかに記載の半導体装置。 A first interlayer insulating film having a groove pattern in which the first electrode is embedded; and a second interlayer insulating film having a groove pattern in which the second electrode is embedded;
The first insulating film is provided in a state of covering the first interlayer insulating film including the inner wall of the groove pattern of the first interlayer insulating film,
The semiconductor device according to claim 1, wherein the second insulating film is provided so as to cover the second interlayer insulating film including an inner wall of a groove pattern of the second interlayer insulating film. 前記第１基板の貼合せ面は、前記第１電極および前記第１絶縁膜のみで構成され、
前記第２基板の貼合せ面は、前記第２電極および前記第２絶縁膜のみで構成されている
請求項１〜５の何れかに記載の半導体装置。 The bonding surface of the first substrate is composed only of the first electrode and the first insulating film,
The semiconductor device according to claim 1, wherein a bonding surface of the second substrate includes only the second electrode and the second insulating film. 前記第１絶縁膜は、前記第１電極と共に前記第２電極を構成する材料に対する拡散防止材料で構成され、
前記第２絶縁膜は、前記第２電極と共に前記第１電極を構成する材料に対する拡散防止材料で構成される
請求項１〜６の何れかに記載の半導体装置。 The first insulating film is made of a diffusion preventing material for a material constituting the second electrode together with the first electrode,
The semiconductor device according to claim 1, wherein the second insulating film is made of a diffusion preventing material with respect to a material constituting the first electrode together with the second electrode. 前記第１電極と前記第２電極とは同一材料で構成されている
請求項１〜７の何れかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the first electrode and the second electrode are made of the same material. 前記第１絶縁膜と前記第２絶縁膜とは同一材料で構成されている
請求項１〜８の何れかに記載の半導体装置。 The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are made of the same material. 電極材料に対する拡散防止材料で構成された絶縁膜を基板上に成膜し、当該絶縁膜に溝パターンを形成することと、
前記絶縁膜に形成された溝パターンを埋め込む状態で前記電極材料によって構成された電極膜を当該絶縁膜上に成膜することと、
前記絶縁膜が露出するまで前記電極膜を研磨し、前記溝パターン内に当該電極膜が埋め込まれた電極をパターン形成することと、
前記電極が形成された２枚の前記基板を、当該電極同士を接合させる状態で貼り合わせることとを行う
半導体装置の製造方法。 Forming an insulating film made of a diffusion preventing material for the electrode material on the substrate, and forming a groove pattern in the insulating film;
Forming an electrode film made of the electrode material on the insulating film in a state of embedding the groove pattern formed in the insulating film;
Polishing the electrode film until the insulating film is exposed, patterning an electrode in which the electrode film is embedded in the groove pattern;
A method for manufacturing a semiconductor device, comprising: bonding the two substrates on which the electrodes are formed in a state in which the electrodes are bonded together. 前記電極をパターン形成する際には、前記絶縁膜をストッパにした化学的機械研磨を行う
請求項１０記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 10, wherein when the electrode is patterned, chemical mechanical polishing is performed using the insulating film as a stopper. 前記電極をパターン形成する際には、前記電極膜の研磨によって前記絶縁膜が周囲に露出した当該電極膜部分から順に、研磨が自動的に停止するような化学的機械研磨を行う
請求項１０または１１に記載の半導体装置の製造方法。 11. When patterning the electrode, chemical mechanical polishing is performed so that polishing automatically stops in order from the electrode film portion where the insulating film is exposed to the surroundings by polishing the electrode film. 11. A method for manufacturing a semiconductor device according to 11. 固体撮像装置と、前記固体撮像装置に入射光を導く光学系と、前記固体撮像装置を駆動する駆動回路とを有し、
前記固体撮像装置は、
第１基板と第２基板とが、それぞれの貼合せ面で貼り合わせられ、
前記第１基板の貼合せ面は、第１電極と、当該第１電極の拡散防止材料からなり当該貼合せ面から当該第１電極の周囲を連続して覆う第１絶縁膜とで構成され、
前記第２基板の貼合せ面は、前記第１電極に接合された第２電極と、当該第２電極の拡散防止材料からなり当該貼合せ面から当該第２電極の周囲を連続して覆う第２絶縁膜とで構成された
電子機器。 A solid-state imaging device; an optical system that guides incident light to the solid-state imaging device; and a drive circuit that drives the solid-state imaging device;
The solid-state imaging device
The first substrate and the second substrate, Serare Awa bonded with each lamination surface,
The bonding surface of the first substrate includes a first electrode and a first insulating film made of a diffusion preventing material for the first electrode and continuously covering the periphery of the first electrode from the bonding surface.
The bonding surface of the second substrate is made of a second electrode joined to the first electrode and a diffusion preventing material for the second electrode, and continuously covers the periphery of the second electrode from the bonding surface. Electronic equipment composed of two insulating films.
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