JP5915194B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5915194B2 JP5915194B2 JP2012007286A JP2012007286A JP5915194B2 JP 5915194 B2 JP5915194 B2 JP 5915194B2 JP 2012007286 A JP2012007286 A JP 2012007286A JP 2012007286 A JP2012007286 A JP 2012007286A JP 5915194 B2 JP5915194 B2 JP 5915194B2
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Description
第1実施形態による半導体装置及びその製造方法を図1乃至図19を用いて説明する。
まず、本実施形態による半導体装置について図1乃至図10を用いて説明する。図1は、本実施形態による半導体装置を示す断面図である。図2は、本実施形態による半導体装置を示す平面図及び断面図である。図2(a)は平面図であり、図2(b)は断面図である。図1及び図2(b)は、図2(a)のA−A′線断面に対応している。図1及び図2は、高耐圧トランジスタが形成される領域(高耐圧トランジスタ形成領域)2を示している。図1及び図2の紙面左側は、Nチャネル型の高耐圧トランジスタが形成される領域(Nチャネル型高耐圧トランジスタ形成領域)2Nを示している。図1及び図2の紙面右側は、Pチャネル型の高耐圧トランジスタが形成される領域(Pチャネル型高耐圧トランジスタ形成領域)2Pを示している。なお、高耐圧トランジスタ形成領域2以外の領域に、コア部や入出力回路に耐圧の低いトランジスタが形成されている場合もあるが、ここでは説明を省略する。
こうして、ゲート電極26aとソース/ドレイン拡散層34a、34bとを有するNチャネル型の高耐圧トランジスタ40Nが形成されている。
こうして、ゲート電極26bとソース/ドレイン拡散層35a、35bとを有するPチャネル型の高耐圧トランジスタ40Pが形成されている。
次に、本実施形態による半導体装置の評価結果について説明する。
次に、本実施形態による半導体装置の製造方法について図11乃至図19を用いて説明する。図11乃至図19は、本実施形態による半導体装置の製造方法を示す工程断面図である。
次に、本実施形態の変形例による半導体装置について図20及び図21を用いて説明する。図20は、本変形例による半導体装置を示す断面図である。図21は、本変形例による半導体装置の一部の回路を示す図である。
第2実施形態による半導体装置及びその製造方法を図22乃至図25を用いて説明する。図1乃至図21に示す第1実施形態による半導体装置及びその製造方法と同一の構成要素には、同一の符号を付して説明を省略または簡潔にする。
まず、本実施形態による半導体装置について図22を用いて説明する。図22は、本実施形態による半導体装置を示す断面図である。
次に、本実施形態による半導体装置の評価結果について図4を用いて説明する。
次に、本実施形態による半導体装置の製造方法について図23乃至図25を用いて説明する。図23乃至図25は、本実施形態による半導体装置の製造方法を示す工程断面図である。
これにより、Pチャネル型高耐圧トランジスタ形成領域2P及びP型のコンタクト領域(ウェルタップ領域)42が形成される領域をそれぞれ露出する開口部138がフォトレジスト膜136に形成される(図24参照)。
上記実施形態に限らず種々の変形が可能である。
2N…Nチャネル型高耐圧トランジスタ形成領域
2P…Pチャネル型高耐圧トランジスタ形成領域
4…内部回路
10…半導体基板
12…素子分離領域
14…P型ウェル
16…N型の拡散層
18…N型の埋め込み拡散層
20…N型ウェル
22…チャネルドープ層
23…チャネルドープ層
24…ゲート絶縁膜
26a、26b…ゲート電極
28a…低濃度ソース領域、低濃度拡散層
28b…低濃度ドレイン領域、低濃度拡散層
29a…低濃度ソース領域、低濃度拡散層
29b…低濃度ドレイン領域、低濃度拡散層
30…サイドウォール絶縁膜、スペーサ
30a…スペーサ
32a…高濃度ソース領域、高濃度拡散層
32b…高濃度ドレイン領域、高濃度拡散層
33a…高濃度ソース領域、高濃度拡散層
33b…高濃度ドレイン領域、高濃度拡散層
34a…ソース拡散層
34b…ドレイン拡散層
35a…ソース拡散層
35b…ドレイン拡散層
38…シリサイド膜
40N…Nチャネル型高耐圧トランジスタ
40P…Pチャネル型高耐圧トランジスタ
42…P型のコンタクト領域
44…N型のコンタクト領域
46…層間絶縁膜
48…コンタクトホール
50…導体プラグ
52…層間絶縁膜
54…溝
56…配線
58…層間絶縁膜
60…層間絶縁膜
62…コンタクトホール
64…溝
66a…導体プラグ
66b…配線
68…層間絶縁膜
70…層間絶縁膜
72…コンタクトホール
74…溝
76a…導体プラグ
76b…配線
78…層間絶縁膜
80…層間絶縁膜
82…コンタクトホール
84…溝
86a…導体プラグ
86b…配線
88…層間絶縁膜
90…コンタクトホール
92a…導体プラグ
92b1〜92b9…配線
94…フォトレジスト膜
96…開口部
98…フォトレジスト膜
100…開口部
102…フォトレジスト膜
104…開口部
106…フォトレジスト膜
108…開口部
110…フォトレジスト膜
112…開口部
114…フォトレジスト膜
116…開口部
118…フォトレジスト膜
120…開口部
122…フォトレジスト膜
124…開口部
126…フォトレジスト膜
128…開口部
130…フォトレジスト膜
132…フォトレジスト膜
134…開口部
136…フォトレジスト膜
138…開口部
202…高耐圧トランジスタ形成領域
210…半導体基板
212…素子分離領域
214…P型ウェル
216…N型の拡散層
218…N型の埋め込み拡散層
220…N型ウェル
224…ゲート絶縁膜
226…ゲート電極
228a…低濃度ソース領域、低濃度拡散層
228b…低濃度ドレイン領域、低濃度拡散層
230…フォトレジスト膜、スペーサ
230a…スペーサ
232a…高濃度ソース領域、高濃度拡散層
232b…高濃度ドレイン領域、高濃度拡散層
234a…ソース拡散層
234b…ドレイン拡散層
238…シリサイド膜
240…高耐圧トランジスタ
242…P型のコンタクト層
244…N型のコンタクト層
294…フォトレジスト膜
296…開口部
298…フォトレジスト膜
300…開口部
302…フォトレジスト膜
304…開口部
303…フォトレジスト膜
305…開口部
310…フォトレジスト膜
312…開口部
314…フォトレジスト膜
316…開口部
322…フォトレジスト膜
324…開口部
326…フォトレジスト膜
328…開口部
330…フォトレジスト膜
Claims (9)
- 第1導電型の半導体基板のうちの第1のトランジスタが形成される領域である第1の領域上に、第1のゲート絶縁膜を介して形成された第1のゲート電極と、
前記第1のゲート電極の一方の側の前記半導体基板内に形成された第1導電型の第1のソース領域と、
前記第1のゲート電極の他方の側の前記半導体基板内の基板領域上に形成された第1導電型の第1のドレイン領域と、
前記第1のソース領域と前記第1のドレイン領域との間の第1のチャネル領域のうちの少なくとも前記第1のソース領域側の領域に形成された第2導電型の第1のチャネルドープ層であって、前記第1のチャネルドープ層のうちの前記第1のドレイン領域側の部分に、前記第1のドレイン領域に向かって第2導電型のドーパント不純物の濃度が低くなる濃度勾配が存在している第1のチャネルドープ層と、
前記第1の領域のうちの前記第1のドレイン領域及び前記基板領域を囲むように形成された第2導電型の第1のウェルであって、前記第1のウェルのうちの前記第1のドレイン領域側の部分に、前記第1のドレイン領域に向かって第2導電型のドーパント不純物の濃度が低くなる濃度勾配が存在している第1のウェルと、
前記第1の領域全体に形成され、前記第1のウェルに接続された、前記第1のウェルの下側に位置する第2導電型の第2のウェルと
を有することを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板のうちの第2のトランジスタが形成される領域である第2の領域上に、第2のゲート絶縁膜を介して形成された第2のゲート電極と、
前記第2のゲート電極の一方の側の前記半導体基板内に形成された第2導電型の第2のソース領域と、
前記第2のゲート電極の他方の側の前記半導体基板内に形成された第2導電型の第2のドレイン領域と、
前記第2のソース領域と前記第2のドレイン領域との間の第2のチャネル領域のうちの少なくとも前記第2のソース領域側の領域に形成された第1導電型の第2のチャネルドープ層であって、前記第2のチャネルドープ層のうちの前記第2のドレイン領域側の部分に、前記第2のドレイン領域に向かって第1導電型のドーパント不純物の濃度が低くなる濃度勾配が存在している第2のチャネルドープ層と、
前記第2の領域のうちの前記第2のドレイン領域を囲むように形成された第1導電型の第3のウェルであって、前記第3のウェルのうちの前記第2のドレイン領域側の部分に、前記第2のドレイン領域に向かって第1導電型のドーパント不純物の濃度が低くなる濃度勾配が存在している第3のウェルとを更に有する
ことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記第1のウェルは、前記第3のウェルの側部を更に囲うように形成されており、
前記第2のウェルは、前記第3のウェルの下側にも更に形成されており、
前記第2のドレイン領域と前記第2のウェルとの間の距離が、前記第2のドレイン領域と前記第3のウェルとの間の距離より大きい
ことを特徴とする半導体装置。 - 請求項1乃至3のいずれか1項に記載の半導体装置において、
前記第1のソース領域は、第1導電型の低濃度ソース領域と、前記低濃度ソース領域より不純物濃度の高い第1の導電型の高濃度ソース領域とを有し、
前記第1のドレイン領域は、第1導電型の低濃度ドレイン領域と、前記低濃度ドレイン領域より不純物濃度の高い第1導電型の高濃度ドレイン領域とを有し、
前記第1のゲート電極と前記高濃度ドレイン領域との間の距離が、前記第1のゲート電極と前記高濃度ソース領域との間の距離より大きい
ことを特徴とする半導体装置。 - 請求項1乃至4のいずれか1項に記載の半導体装置において、
前記第1のドレイン領域と前記第1のチャネルドープ層とが互いに離間している
ことを特徴とする半導体装置。 - 第1導電型の半導体基板のうちの第1のトランジスタが形成される領域である第1の領域内に第2導電型の第1のチャネルドープ層を形成する工程であって、前記第1のトランジスタの第1のドレイン領域を形成するためのドーパント不純物が導入される第1の所定領域を囲む領域に、前記第1の所定領域から離間するように前記第1のチャネルドープ層を形成する工程と、
前記第1の領域のうちの前記第1の所定領域を囲む領域に、前記第1の所定領域から離間するように第2導電型の第1のウェルを形成する工程と、
前記第1のウェルに接続される第2導電型の第2のウェルを前記第1のウェルの下側に位置するように前記第1の領域全体に形成する工程と、
前記第1の領域内における前記半導体基板上に第1のゲート絶縁膜を介して前記第1のトランジスタの第1のゲート電極を形成する工程と、
前記第1のゲート電極の一方の側の前記半導体基板内に前記第1のトランジスタの第1導電型の第1のソース領域を形成し、前記第1のゲート電極の他方の側の前記半導体基板の前記第1の所定領域に第1の導電型の前記第1のドレイン領域を形成する工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記半導体基板のうちの第2のトランジスタが形成される領域である第2の領域内に第1導電型の第2のチャネルドープ層を形成する工程であって、前記第2のトランジスタの第2のドレイン領域を形成するためのドーパント不純物が導入される第2の所定領域を囲む領域に、前記第2の所定領域から離間するように前記第2のチャネルドープ層を形成する工程と、
前記第2の領域のうちの前記第2の所定領域を囲む領域に、前記第2の所定領域から離間するように第1導電型の第3のウェルを形成する工程とを更に有し、
前記第1のゲート電極を形成する工程では、前記第2の領域内における前記半導体基板上に第2のゲート絶縁膜を介して前記第2のトランジスタの第2のゲート電極を更に形成し、
前記第2のゲート電極の一方の側の前記半導体基板内に前記第2のトランジスタの第2のソース領域を形成し、前記第2のゲート電極の他方の側の前記半導体基板の前記第2の所定領域に前記第2のドレイン領域を形成する工程を更にする
ことを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第1のウェルを形成する工程では、前記第3のウェルを更に囲うように前記第1のウェルを形成し、
前記第2のウェルを形成する工程では、前記第2のドレイン領域と前記第2のウェルとの間の距離が、前記第2のドレイン領域と前記第3のウェルとの間の距離より大きくなるように、前記第3のウェルの下側にも前記第2のウェルを更に形成する
ことを特徴とする半導体装置の製造方法。 - 請求項6乃至8のいずれか1項に記載の半導体装置の製造方法において、
前記第1のソース領域を形成する工程は、前記第1のゲート電極をマスクとして前記半導体基板内に第1導電型のドーパント不純物を導入することにより、前記第1のゲート電極の一方の側の前記半導体基板内に低濃度ソース領域を形成し、前記第1のゲート電極の他方の側の前記半導体基板内に低濃度ドレイン領域を形成する工程と;前記第1のゲート電極の前記一方の側の側壁部分に第1のスペーサを形成し、前記第1のゲート電極の前記他方の側の少なくとも側壁部分に第2のスペーサを形成する工程と;前記第1のゲート電極、前記第1のスペーサ及び前記第2のスペーサをマスクとして、前記半導体基板内に第1導電型のドーパント不純物を導入することにより、前記第1のゲート電極の前記一方の側の前記半導体基板内に前記第1の低濃度ソース領域より不純物濃度の高い第1の高濃度ソース領域を、前記第1のゲート電極の前記一方の側の側壁から第1の距離で離間するように形成し、前記第1のゲート電極の前記他方の側の前記半導体基板内に前記第1の低濃度ドレイン領域より不純物濃度の高い第2の高濃度ドレイン領域を、前記第1のゲート電極の前記他方の側の側壁から前記第1の距離より大きい第2の距離で離間するように形成する工程とを有する
ことを特徴とする半導体装置の製造方法。
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JPH07161987A (ja) | 1993-12-08 | 1995-06-23 | Hitachi Ltd | Mis型半導体装置 |
JP3055424B2 (ja) * | 1994-04-28 | 2000-06-26 | 株式会社デンソー | Mis型半導体装置の製造方法 |
JP2000164854A (ja) * | 1998-11-30 | 2000-06-16 | Matsushita Electric Works Ltd | 半導体装置及びその製造方法 |
JP4813757B2 (ja) * | 2003-02-14 | 2011-11-09 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
CN100517711C (zh) * | 2004-05-27 | 2009-07-22 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
JP2007049039A (ja) | 2005-08-11 | 2007-02-22 | Toshiba Corp | 半導体装置 |
CN101226962B (zh) * | 2008-02-22 | 2013-07-17 | 苏州赛芯电子科技有限公司 | Hvmos及集成hvmos与cmos的半导体器件 |
JP2009245998A (ja) * | 2008-03-28 | 2009-10-22 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
JP4645861B2 (ja) * | 2008-07-03 | 2011-03-09 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2010182727A (ja) * | 2009-02-03 | 2010-08-19 | Renesas Electronics Corp | 半導体装置 |
US8030151B2 (en) * | 2009-03-27 | 2011-10-04 | National Semiconductor Corporation | Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length |
US20100244152A1 (en) * | 2009-03-27 | 2010-09-30 | Bahl Sandeep R | Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor |
US8101479B2 (en) * | 2009-03-27 | 2012-01-24 | National Semiconductor Corporation | Fabrication of asymmetric field-effect transistors using L-shaped spacers |
US8273617B2 (en) * | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
JP5560812B2 (ja) * | 2010-03-23 | 2014-07-30 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8252652B2 (en) * | 2010-03-29 | 2012-08-28 | Vanguard International Semiconductor Corporation | Semiconductor structure and fabrication method thereof |
US8664720B2 (en) * | 2010-08-25 | 2014-03-04 | Infineon Technologies Ag | High voltage semiconductor devices |
JP5605241B2 (ja) * | 2011-01-27 | 2014-10-15 | 富士通セミコンダクター株式会社 | Mosトランジスタおよび半導体集積回路装置の製造方法 |
JP5915194B2 (ja) * | 2012-01-17 | 2016-05-11 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
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CN103208494A (zh) | 2013-07-17 |
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