JP5905267B2 - 発光素子パッケージ及びその製造方法 - Google Patents
発光素子パッケージ及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Description
搭載部材10は、リードフレーム11に素子搭載凹部12を有するパッケージ本体13を樹脂で成形して構成されている。この搭載部材10の素子搭載凹部12の底面中央部には、半導体素子であるLED素子14(発光素子)がダイボンディング(接合)されている。素子搭載凹部12の深さ寸法(高さ寸法)は、LED素子14の高さ寸法とほぼ同一に設定され、素子搭載凹部12内に搭載したLED素子14上面の電極部15が搭載部材10上面のリードフレーム11の電極部11aとほぼ同じ高さとなっている。
搭載部材21は、リードフレーム22に素子搭載凹部23を有するパッケージ本体24を樹脂で成形して構成され、該素子搭載凹部23の側面が傾斜状に形成されている。素子搭載凹部23の底面には、リードフレーム22の素子搭載部22a(ダイパッド)が露出し、該素子搭載部22a上に半導体素子であるLED素子25(発光素子)がダイボンド(接合)されている。
Claims (3)
- 搭載部材に形成された素子搭載凹部内に発光素子が搭載され、該発光素子側の電極部と該搭載部材側の電極部との間が配線で接続された発光素子パッケージにおいて、
前記発光素子側の電極部と前記搭載部材側の電極部との間の配線経路の下地樹脂層は、該素子搭載凹部内の該発光素子の周囲の隙間に充填された透明な絶縁性樹脂で形成され、 前記配線経路の下地樹脂層上に前記発光素子側の電極部の一部と前記搭載部材側の電極部の一部とに跨がってガスバリア性を有する絶縁性のインクでガスバリア性を有する中間絶縁層が線状又は帯状に形成され、
前記中間絶縁層上に前記発光素子側の電極部のうちの該中間絶縁層で覆われていない部分と前記搭載部材側の電極部のうちの該中間絶縁層で覆われていない部分とに跨がって導電性のインクで前記配線のパターンが形成され、該発光素子側の電極部と該搭載部材側の電極部との間が該配線で接続されていることを特徴とする発光素子パッケージ。 - 前記中間絶縁層は、前記配線が該中間絶縁層からはみ出さないように該配線の線幅よりも製造ばらつき相当値以上太い線幅に形成されていることを特徴とする請求項1に記載の発光素子パッケージ。
- 搭載部材に形成した素子搭載凹部内に発光素子を搭載し、該発光素子側の電極部と該搭載部材側の電極部との間を配線で接続した発光素子パッケージの製造方法において、
前記素子搭載凹部内に前記発光素子を搭載する工程と、
前記素子搭載凹部内の前記発光素子の周囲の隙間に透明な絶縁性樹脂を充填して該発光素子側の電極部と該搭載部材側の電極部との間の配線経路の下地樹脂層を該絶縁性樹脂で形成する工程と、
前記配線経路の下地樹脂層上に前記発光素子側の電極部の一部と前記搭載部材側の電極部の一部とに跨がってガスバリア性を有する絶縁性のインクを吐出又は印刷してガスバリア性を有する中間絶縁層を線状又は帯状に形成する工程と、
前記中間絶縁層上に前記発光素子側の電極部のうちの該中間絶縁層で覆われていない部分と前記搭載部材側の電極部のうちの該中間絶縁層で覆われていない部分とに跨がって導電性のインクを吐出又は印刷して前記配線のパターンを形成して焼成して該発光素子側の電極部と該搭載部材側の電極部との間を該配線で接続する工程と
を含むことを特徴とする発光素子パッケージの製造方法。
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JP2012006552A JP5905267B2 (ja) | 2012-01-16 | 2012-01-16 | 発光素子パッケージ及びその製造方法 |
CN201280057767.7A CN103959450B (zh) | 2011-11-25 | 2012-10-29 | 半导体封装件及其制造方法 |
PCT/JP2012/077870 WO2013077144A1 (ja) | 2011-11-25 | 2012-10-29 | 半導体パッケージ及びその製造方法 |
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JP6037544B2 (ja) * | 2012-06-19 | 2016-12-07 | 富士機械製造株式会社 | Ledパッケージ及びその製造方法 |
JP6037545B2 (ja) * | 2012-06-19 | 2016-12-07 | 富士機械製造株式会社 | Ledパッケージ及びその製造方法 |
CN108080041B (zh) * | 2016-11-21 | 2023-10-20 | 胡丛余 | 微型流体致动器 |
DE102019104436A1 (de) * | 2019-02-21 | 2020-08-27 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches bauteil und verfahren zur herstellung eines optoelektronischen bauteils |
JP7116327B2 (ja) | 2019-12-27 | 2022-08-10 | 日亜化学工業株式会社 | 発光モジュールおよび発光モジュールの製造方法 |
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