JP5857129B2 - 窓なしのワイヤボンドアセンブリのためのスタブ最小化 - Google Patents
窓なしのワイヤボンドアセンブリのためのスタブ最小化 Download PDFInfo
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- JP5857129B2 JP5857129B2 JP2014534623A JP2014534623A JP5857129B2 JP 5857129 B2 JP5857129 B2 JP 5857129B2 JP 2014534623 A JP2014534623 A JP 2014534623A JP 2014534623 A JP2014534623 A JP 2014534623A JP 5857129 B2 JP5857129 B2 JP 5857129B2
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10159—Memory
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
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Description
本出願は、2012年4月5日に出願された米国特許出願第13/440,313号の継続出願である。この米国特許出願は、2012年2月17日に出願された米国仮特許出願第61/600,271号と、2011年10月3日に出願された同第61/542,488号と、2011年10月3日に出願された同第61/542,553号との出願日の利益を主張する。全ての上記出願の開示内容は、引用することによって本明細書の一部をなすものとする。
Claims (10)
- 超小型電子パッケージであって、
第1の表面と、複数の基板コンタクトと、前記第1の表面の反対側の第2の表面とを有する基板であって、前記第2の表面は、第1の方向及び前記第1の方向を横切る第2の方向に延在する、基板と、
その他の機能よりもメモリ記憶アレイ機能を与える多数のアクティブデバイスを有する超小型電子素子であって、該超小型電子素子は、前記第1の表面を向く後面と、該後面の反対側の前面と、それぞれが前記前面と前記後面との間に延在しかつ前記前面に平行な方向に延在する対向する第1の縁部及び第2の縁部とを有し、該超小型電子素子は、前記前面に沿う前記第1の方向に延在する、素子コンタクトの少なくとも1つの列を有し、前記第1の縁部及び第2の縁部は、前記第1の方向に延在するとともに、前記超小型電子素子の前記後面に垂直な第3の方向にも延在する軸平面を規定しており、該軸平面は、前記第1の縁部及び前記第2の縁部に対して中央に置かれる、超小型電子素子と、
前記素子コンタクトを前記基板コンタクトに電気的に接続する、前記前面の上に延在する導電性構造と、
前記第2の表面において前記基板コンタクトに電気的に接続された、前記第1の方向に延在する端子の複数の平行な列であって、前記端子は、前記基板の前記第2の表面の中央領域内に露出する第1の端子を含み、前記第1の端子は、前記超小型電子素子内のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から、1つのアドレス指定可能メモリ位置を決定するのに該パッケージ内の回路によって使用可能なアドレス情報を運ぶように構成される、端子の複数の平行な列と
を含んでなり、
前記中央領域は、前記第2の方向に幅を有し、前記中央領域の前記幅は、前記端子の前記平行な列の任意の2つの隣接する列間の最小ピッチの3.5倍以下であり、前記軸平面は前記中央領域に交わる、超小型電子パッケージ。 - 前記第1の端子は、前記メモリ記憶アレイ内の前記アドレス指定可能メモリ位置を決定するのに該パッケージ内の前記回路によって使用可能な前記アドレス情報の全てを運ぶように構成される、請求項1に記載の超小型電子パッケージ。
- 前記導電性構造は、前記素子コンタクトから延在し、前記基板コンタクトに電気的に接続されたワイヤボンドを含む、請求項1に記載の超小型電子パッケージ。
- 前記第1の端子は、端子のわずか2つ以下の列に配列される、請求項1に記載の超小型電子パッケージ。
- 前記第1の端子は、端子の単一の列に配列される、請求項1に記載の超小型電子パッケージ。
- 前記第1の端子は、端子の4つ以下の列に配列される、請求項1に記載の超小型電子パッケージ。
- 前記基板は、互いに反対側の前記第1の表面と前記第2の表面との間に対向する第1の縁部及び第2の縁部を有し、前記第1の縁部及び前記第2の縁部は前記第1の方向に延在し、前記第2の表面は、前記第1の縁部及び前記第2の縁部に隣接する第1の周辺領域及び第2の周辺領域をそれぞれ有し、前記中央領域は、前記第1の周辺領域及び前記第2の周辺領域を分離し、
前記端子は、前記第2の表面において前記周辺領域の少なくとも一方の周辺領域内に露出する複数の第2の端子を含み、前記第2の端子のうちの少なくともいくつかは前記アドレス情報以外の情報を運ぶように構成される、請求項1に記載の超小型電子パッケージ。 - 前記第2の端子のうちの少なくともいくつかはデータ信号を運ぶように構成される、請求項7に記載の超小型電子パッケージ。
- 前記第1の端子は、前記超小型電子素子のメモリ記憶アレイの全ての利用可能なアドレス指定可能メモリ位置の中から、1つのアドレス指定可能メモリ位置を決定するのに該パッケージ内の回路によって使用可能なアドレス情報の大部分を運ぶように構成される、請求項1に記載の超小型電子パッケージ。
- 前記超小型電子素子は、第1の超小型電子素子及び第2の超小型電子素子を含み、該第1の超小型電子素子及び第2の超小型電子素子のそれぞれは、その他の機能よりもメモリ記憶アレイ機能を与える多数のアクティブデバイスを実現しており、該第1の超小型電子素子及び該第2の超小型電子素子は、前記第1の表面上で互いから離間し、それぞれが前記第1の方向に延在する平行な第1の縁部を有し、前記軸平面は、前記第1の縁部の間で中央に置かれる、
、請求項1に記載の超小型電子パッケージ。
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US201161542553P | 2011-10-03 | 2011-10-03 | |
US201161542488P | 2011-10-03 | 2011-10-03 | |
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US61/542,488 | 2011-10-03 | ||
US201261600271P | 2012-02-17 | 2012-02-17 | |
US61/600,271 | 2012-02-17 | ||
US13/440,313 US8405207B1 (en) | 2011-10-03 | 2012-04-05 | Stub minimization for wirebond assemblies without windows |
US13/440,313 | 2012-04-05 | ||
PCT/US2012/058273 WO2013052411A1 (en) | 2011-10-03 | 2012-10-01 | Stub minimization for wirebond assemblies without windows |
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