JP5840197B2 - Organic field effect transistor and organic semiconductor material - Google Patents
Organic field effect transistor and organic semiconductor material Download PDFInfo
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- JP5840197B2 JP5840197B2 JP2013502411A JP2013502411A JP5840197B2 JP 5840197 B2 JP5840197 B2 JP 5840197B2 JP 2013502411 A JP2013502411 A JP 2013502411A JP 2013502411 A JP2013502411 A JP 2013502411A JP 5840197 B2 JP5840197 B2 JP 5840197B2
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- effect transistor
- field effect
- semiconductor material
- organic semiconductor
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Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C07—ORGANIC CHEMISTRY
- C07D—HETEROCYCLIC COMPOUNDS
- C07D495/00—Heterocyclic compounds containing in the condensed system at least one hetero ring having sulfur atoms as the only ring hetero atoms
- C07D495/02—Heterocyclic compounds containing in the condensed system at least one hetero ring having sulfur atoms as the only ring hetero atoms in which the condensed system contains two hetero rings
- C07D495/04—Ortho-condensed systems
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09B—ORGANIC DYES OR CLOSELY-RELATED COMPOUNDS FOR PRODUCING DYES, e.g. PIGMENTS; MORDANTS; LAKES
- C09B57/00—Other synthetic dyes of known constitution
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/60—Organic compounds having low molecular weight
- H10K85/649—Aromatic compounds comprising a hetero atom
- H10K85/657—Polycyclic condensed heteroaromatic hydrocarbons
- H10K85/6576—Polycyclic condensed heteroaromatic hydrocarbons comprising only sulfur in the heteroaromatic polycondensed ring system, e.g. benzothiophene
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
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- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
Description
本発明は、有機電界効果トランジスタに関する。詳しくは半導体活性層が特定の構造の有機半導体材料及び前記有機半導体材料とは異なる構造を有する有機半導体材料からなる有機電界効果トランジスタに関する。さらに詳しくは半導体活性層が特定の構造の有機半導体材料を含む層と前記有機半導体材料とは異なる有機半導体材料を含む層との積層構造からなる有機電界効果トランジスタに関する。 The present invention relates to an organic field effect transistor. More specifically, the present invention relates to an organic field effect transistor having a semiconductor active layer made of an organic semiconductor material having a specific structure and an organic semiconductor material having a structure different from that of the organic semiconductor material. More particularly, the present invention relates to an organic field effect transistor in which a semiconductor active layer has a stacked structure of a layer containing an organic semiconductor material having a specific structure and a layer containing an organic semiconductor material different from the organic semiconductor material.
電界効果トランジスタは、一般に、基板上の半導体材料にソース電極、ドレイン電極、及びこれらの電極と絶縁体層を介してゲート電極等を設けた構造を有する。現在、電界効果トランジスタには、シリコンを中心とする無機系の半導体材料、特にアモルファスシリコンが使用されている。ガラスなどの基板上にこれらの半導体材料を使用して作製した薄膜トランジスタをディスプレイ等に使用したり、論理回路素子として集積回路に使用されるほか、スイッチング素子等にも幅広く用いられている。さらに最近は半導体材料に無機系酸化物の半導体を用いる検討が盛んに行なわれている。しかし、このような無機系の半導体材料を用いた場合、電界効果トランジスタの製造時に高温や真空で処理する必要があり、その基板には耐熱性に劣るフィルムやプラスチック等を利用することができず、また高額な設備投資や、製造に多くのエネルギーを要するため、コストが非常に高いものとなり、その応用範囲が非常に制限されている。 A field effect transistor generally has a structure in which a semiconductor material on a substrate is provided with a source electrode, a drain electrode, and a gate electrode or the like via these electrodes and an insulator layer. Currently, inorganic semiconductor materials centered on silicon, particularly amorphous silicon, are used for field effect transistors. Thin film transistors manufactured using these semiconductor materials on a substrate such as glass are used for displays and the like, used as integrated circuits as logic circuit elements, and widely used as switching elements. In recent years, studies have been actively conducted on the use of inorganic oxide semiconductors as semiconductor materials. However, when such an inorganic semiconductor material is used, it is necessary to process it at a high temperature or in vacuum at the time of manufacturing a field effect transistor, and it is not possible to use a film or plastic having poor heat resistance for the substrate. In addition, because of the large capital investment and the production of a large amount of energy, the cost is very high and the application range is very limited.
これに対して、電界効果トランジスタの製造時に高温処理を必要としない有機半導体材料を用いた電界効果トランジスタの開発も行われている。有機半導体材料を用いることができれば、低温プロセスでの製造が可能になり、使用可能な基板材料の範囲が拡大される。その結果、よりフレキシブルで、且つ軽量で、壊れにくい電界効果トランジスタの作製が可能となる。また、電界効果トランジスタの作製工程において、有機半導体材料を含有する溶液の塗布や、インクジェット等による印刷方法等により、大面積の電界効果トランジスタを低コストで製造できる可能性もある。 On the other hand, a field effect transistor using an organic semiconductor material that does not require high-temperature treatment when manufacturing the field effect transistor has been developed. If an organic semiconductor material can be used, manufacturing by a low-temperature process becomes possible, and the range of usable substrate materials is expanded. As a result, it becomes possible to manufacture a field effect transistor that is more flexible, lightweight, and less likely to break. In the field effect transistor manufacturing process, a large-area field effect transistor may be manufactured at low cost by applying a solution containing an organic semiconductor material, a printing method using an inkjet, or the like.
しかし、移動度が高く、耐久性に優れた有機半導体を使用する電界効果トランジスタは実用化されておらず、各適性が向上したトランジスタを得るために多くの検討が現在も盛んに行われている。特に安定性の向上は重要な課題の一つである。有機電界効果トランジスタ用の代表的な有機半導体としてペンタセンが挙げられる。ペンタセンは実用的な移動度を有し、入手も比較的容易であるため盛んに活用されているが、大気中で酸化を受け、電気特性が低下してしまうという問題点が残っている。またその欠点を補うために、大気安定性を向上させた半導体の開発がなされている（非特許文献１、特許文献１、特許文献２）。しかし、大気安定性の向上は、移動度の低下や、電極からの電化注入特性の低下などの問題点をもたらすため、電極への金属酸化物処理や自己組織化単分子膜形成などの検討もなされている（特許文献３、特許文献４、非特許文献２、非特許文献３）。
有機半導体層を積層することによりトランジスタ特性の向上を図る検討がなされている。例えば非特許文献４ではペンタセンをルブレンの結晶性コントロール材料として、また非特許文献５ではペンタセンをベンゾジチオフェンダイマーの結晶性コントロール材料として活用することで結晶性を上げ、ルブレンとベンゾチオフェンダイマーの移動度の向上を図っている。However, a field effect transistor using an organic semiconductor having high mobility and excellent durability has not been put into practical use, and many studies are actively conducted to obtain a transistor with improved suitability. . In particular, improvement of stability is an important issue. A typical organic semiconductor for organic field effect transistors is pentacene. Pentacene has been used extensively because it has practical mobility and is relatively easy to obtain, but the problem remains that it is oxidized in the atmosphere and its electrical properties deteriorate. In addition, in order to compensate for the shortcomings, semiconductors with improved atmospheric stability have been developed (
Studies have been made to improve transistor characteristics by stacking organic semiconductor layers. For example, in Non-Patent
本発明は実用的な安定性を有し、さらにキャリア移動度、ヒステリシスや閾値安定性などの半導体特性に優れた実用的な電界効果トランジスタを提供することを目的とする。 An object of the present invention is to provide a practical field-effect transistor having practical stability and excellent semiconductor characteristics such as carrier mobility, hysteresis and threshold stability.
本発明者等は上記課題を解決すべく鋭意検討の結果、半導体活性層に有用な特定の構造を有する新規な化合物を見出し、また半導体活性層に特定の構造を有する有機半導体材料及び他の構造を有する有機半導体材料を組み合わせることで電荷移動速度が速く、安定性の優れた有機電界効果トランジスタが得られる事を見いだし、本発明を完成させるに至った。 As a result of intensive studies to solve the above problems, the present inventors have found a novel compound having a specific structure useful for a semiconductor active layer, and organic semiconductor materials and other structures having a specific structure for the semiconductor active layer It has been found that an organic field effect transistor having a high charge transfer rate and excellent stability can be obtained by combining organic semiconductor materials having the above, and the present invention has been completed.
すなわち、本発明は、以下の通りである。
［１］一般式（１）で表わされる有機半導体材料（Ａ）と、前記一般式（１）で表わされる有機半導体材料以外の有機半導体材料（Ｂ）とを含む電界効果トランジスタ。
（Ｘ１は置換基を有してもよい脂肪族炭化水素残基又は置換基を有してもよい芳香族残基を表わす。）
［２］有機半導体材料（Ａ）が一般式（２）で表わされる有機半導体材料である、［１］に記載の電界効果トランジスタ。
（Ｒ１は水素原子又は置換基を有してもよい脂肪族炭化水素残基を表わす。）
［３］有機半導体材料（Ｂ）が一般式（３）で表わされる有機半導体材料である、［１］又は［２］に記載の電界効果トランジスタ。
（Ｘ２は置換基を有してもよい脂肪族炭化水素残基又は置換基を有してもよい芳香族残基を表わす。）
［４］一般式（３）で表わされる有機半導体材料が一般式（４）である、［３］に記載の電界効果トランジスタ。
（Ｒ２は水素原子又は置換基を有してもよい脂肪族炭化水素残基を表わす。）
［５］有機半導体材料（Ａ）を含む層と、有機半導体材料（Ｂ）を含む層とが、積層されている構造を有している、［１］〜［４］のいずれか一つに記載の電界効果トランジスタ。
［６］スタガ型のトランジスタ構造である、［５］に記載の電界効果トランジスタ。
［７］ゲート電極上に設けられた絶縁体層上に、有機半導体材料（Ｂ）を含む層及び有機半導体材料（Ａ）を含む層が順に積層され、さらに有機半導体材料（Ａ）を含む層の最上部に接するようにソース電極及びドレイン電極がそれぞれ設けられているトップコンタクトボトムゲート型構造である、［６］に記載の電界効果トランジスタ。
［８］基板上にソース電極及びドレイン電極がそれぞれ設けられており、その上に有機半導体材料（Ａ）を含む層及び有機半導体材料（Ｂ）を含む層が順に積層され、さらに有機半導体材料（Ｂ）を含む層の最上部に接するように設けられた絶縁体層上にゲート電極が設けられているボトムコンタクトトップゲート型構造である、［６］に記載の電界効果トランジスタ。
［９］一般式（５）で表わされるナフトジチオフェン系化合物。
（Ｒ３はＣ１−３アルキル基を表わす。）
［１０］Ｒ３がメチル基である（９）に記載のナフトジチオフェン系化合物。
［１１］式（６）で表わされる化合物。
［１２］［９］〜［１１］のいずれか一つに記載の化合物からなるナフトジチオフェン系有機半導体材料。
［１３］［９］〜［１１］のいずれか一つに記載の化合物からなるナフトジチオフェン系有機トランジスタ材料。
［１４］［１２］に記載の有機半導体材料を含む電界効果トランジスタ。That is, the present invention is as follows.
[1] A field effect transistor comprising an organic semiconductor material (A) represented by the general formula (1) and an organic semiconductor material (B) other than the organic semiconductor material represented by the general formula (1).
(X 1 represents an aliphatic hydrocarbon residue which may have a substituent or an aromatic residue which may have a substituent.)
[2] The field effect transistor according to [1], wherein the organic semiconductor material (A) is an organic semiconductor material represented by the general formula (2).
(R 1 represents a hydrogen atom or an aliphatic hydrocarbon residue which may have a substituent.)
[3] The field effect transistor according to [1] or [2], wherein the organic semiconductor material (B) is an organic semiconductor material represented by the general formula (3).
(X 2 represents an aliphatic hydrocarbon residue which may have a substituent or an aromatic residue which may have a substituent.)
[4] The field effect transistor according to [3], wherein the organic semiconductor material represented by the general formula (3) is the general formula (4).
(R 2 represents a hydrogen atom or an aliphatic hydrocarbon residue which may have a substituent.)
[5] In any one of [1] to [4], the layer including the organic semiconductor material (A) and the layer including the organic semiconductor material (B) have a stacked structure. The field effect transistor as described.
[6] The field effect transistor according to [5], which has a staggered transistor structure.
[7] On the insulator layer provided on the gate electrode, a layer containing the organic semiconductor material (B) and a layer containing the organic semiconductor material (A) are sequentially stacked, and further a layer containing the organic semiconductor material (A) [6] The field effect transistor according to [6], which has a top contact bottom gate structure in which a source electrode and a drain electrode are respectively provided so as to be in contact with the uppermost portion.
[8] A source electrode and a drain electrode are respectively provided on a substrate, and a layer containing an organic semiconductor material (A) and a layer containing an organic semiconductor material (B) are sequentially stacked thereon, and an organic semiconductor material ( [6] The field effect transistor according to [6], which has a bottom contact top gate structure in which a gate electrode is provided on an insulator layer provided so as to be in contact with the top of the layer including B).
[9] A naphthodithiophene compound represented by the general formula (5).
(R 3 represents a C1-3 alkyl group.)
[10] The naphthodithiophene compound according to (9), wherein R 3 is a methyl group.
[11] A compound represented by formula (6).
[12] A naphthodithiophene-based organic semiconductor material comprising the compound according to any one of [9] to [11].
[13] A naphthodithiophene-based organic transistor material comprising the compound according to any one of [9] to [11].
[14] A field effect transistor comprising the organic semiconductor material according to [12].
半導体活性層に特定の構造の有機半導体材料及び有機半導体材料を組み合わせることで電荷移動速度が速く、安定性の優れた有機電界効果トランジスタが得られる。 By combining an organic semiconductor material having a specific structure and an organic semiconductor material with the semiconductor active layer, an organic field effect transistor having a high charge transfer speed and excellent stability can be obtained.
以下において、本発明を詳細に説明する。
本発明は半導体活性層に一般式（１）で表わされるヘテロアセン系Ｐ型有機半導体材料及び前記一般式（１）で表わされるヘテロアセン系Ｐ型有機半導体材料とは異なるＰ型の有機半導体材料を組み合わせることで電荷移動速度が速く、安定性の優れた有機電界効果トランジスタを得ることができる。Hereinafter, the present invention will be described in detail.
The present invention combines a heteroacene P-type organic semiconductor material represented by the general formula (1) and a P-type organic semiconductor material different from the heteroacene P-type organic semiconductor material represented by the general formula (1) in the semiconductor active layer. Thus, an organic field effect transistor having a high charge transfer speed and excellent stability can be obtained.
次に一般式（１）で表わされる有機半導体材料（Ａ）について説明する。一般式（１）の骨格を有する有機半導体材料は置換基（式（１）中、置換基はＸ１で表わす。）を有することができる。具体的なその置換基としては、置換されてもよい脂肪族炭化水素残基又は置換されてもよい芳香族残基が挙げられる。
ここで脂肪族炭化水素基としては飽和又は不飽和の直鎖、分岐鎖又は環状の脂肪族炭化水素基が挙げられ、好ましくは直鎖又は分岐鎖の脂肪族炭化水素基であり、さらに好ましくは直鎖の脂肪族炭化水素基である。炭素数は通常Ｃ１−Ｃ３６であり、好ましくはＣ１−Ｃ２４、さらに好ましくはＣ１−Ｃ２０、最も好ましくはＣ１−Ｃ１２である。この脂肪族炭化水素基はハロゲン原子で置換されていてもよい。
直鎖又は分岐鎖の飽和脂肪族炭化水素基の具体例としては、メチル、エチル、プロピル、ｉｓｏ−プロピル、ｎ−ブチル、ｉｓｏ−ブチル、ｔ−ブチル、ｎ−ペンチル、ｉｓｏ−ペンチル、ｔ−ペンチル、ｓｅｃ−ペンチル、ｎ−ヘキシル、ｉｓｏ−ヘキシル、ｎ−ヘプチル、ｓｅｃ−ヘプチル、ｎ−オクチル、ｎ−ノニル、ｓｅｃ−ノニル、ｎ−デシル、ｎ−ウンデシル、ｎ−ドデシル、ｎ−トリデシル、ｎ−テトラデシル、ｎ−ペンタデシル、ｎ−ヘキサデシル、ｎ−ヘプタデシル、ｎ−オクタデシル、ｎ−ノナデシル、ｎ−エイコシル、ドコシル、ｎ−ペンタコシル、ｎ−オクタコシル、ｎ−トリコンチル、５−（ｎ−ペンチル）デシル、ヘネイコシル、トリコシル、テトラコシル、ヘキサコシル、ヘプタコシル、ノナコシル、ｎ−トリアコンチル、スクアリル、ドトリアコンチル、ヘキサトリアコンチル等が挙げられる。Next, the organic semiconductor material (A) represented by the general formula (1) will be described. The organic semiconductor material having a skeleton of the general formula (1) can have a substituent (in the formula (1), the substituent is represented by X 1 ). Specific examples of the substituent include an aliphatic hydrocarbon residue which may be substituted or an aromatic residue which may be substituted.
Here, examples of the aliphatic hydrocarbon group include a saturated or unsaturated linear, branched or cyclic aliphatic hydrocarbon group, preferably a linear or branched aliphatic hydrocarbon group, and more preferably It is a linear aliphatic hydrocarbon group. The number of carbon atoms is usually C1-C36, preferably C1-C24, more preferably C1-C20, and most preferably C1-C12. This aliphatic hydrocarbon group may be substituted with a halogen atom.
Specific examples of the linear or branched saturated aliphatic hydrocarbon group include methyl, ethyl, propyl, iso-propyl, n-butyl, iso-butyl, t-butyl, n-pentyl, iso-pentyl, t- Pentyl, sec-pentyl, n-hexyl, iso-hexyl, n-heptyl, sec-heptyl, n-octyl, n-nonyl, sec-nonyl, n-decyl, n-undecyl, n-dodecyl, n-tridecyl, n-tetradecyl, n-pentadecyl, n-hexadecyl, n-heptadecyl, n-octadecyl, n-nonadecyl, n-eicosyl, docosyl, n-pentacosyl, n-octacosyl, n-tricontyl, 5- (n-pentyl) decyl , Heneicosyl, tricosyl, tetracosyl, hexacosyl, heptacosyl, nonacosyl, n-to Akonchiru, Sukuariru, dotriacontyl, hexamethylene triacontyl, and the like.
環状の飽和脂肪族炭化水素基の具体例としては、シクロヘキシル、シクロペンチル、アダマンチル、ノルボルニル等が挙げられる。 Specific examples of the cyclic saturated aliphatic hydrocarbon group include cyclohexyl, cyclopentyl, adamantyl, norbornyl and the like.
直鎖又は分岐鎖の不飽和脂肪族炭化水素基の具体例としてはビニル、アリル、エイコサジエニル、１１，１４−エイコサジエニル、ゲラニル（トランス−３，７−ジメチル−２，６−オクタジエン−１−イル）、ファルネシル（トランス、トランス−３，７，１１−トリメチル−２，６，１０−ドデカトリエン−１−イル）、４−ペンテニル、１−プロピニル、１−ヘキシニル、１−オクチニル、１−デシニル、１−ウンデシニル、１−ドデシニル、１−テトラデシニル、１−ヘキサデシニル、１−ノナデシニル等が挙げられる。 Specific examples of the linear or branched unsaturated aliphatic hydrocarbon group include vinyl, allyl, eicosadienyl, 11,14-eicosadienyl, and geranyl (trans-3,7-dimethyl-2,6-octadien-1-yl). Farnesyl (trans, trans-3,7,11-trimethyl-2,6,10-dodecatrien-1-yl), 4-pentenyl, 1-propynyl, 1-hexynyl, 1-octynyl, 1-decynyl, 1 -Undecynyl, 1-dodecynyl, 1-tetradecynyl, 1-hexadecynyl, 1-nonadecynyl and the like.
直鎖、分岐鎖及び環状の脂肪族炭化水素基のうち、好ましいものは直鎖又は分岐鎖の脂肪族炭化水素基であり、さらに好ましくは直鎖の脂肪族炭化水素基である。飽和又は不飽和の脂肪族炭化水素基とは、飽和のアルキル基、炭素−炭素二重結合を含むアルケニル基及び炭素−炭素三重結合を含むアルキニル基が挙げられ、より好ましくはアルキル基又はアルキニル基であり、さらに好ましくはアルキル基である。脂肪族炭化水素残基には、これらの飽和又は不飽和の脂肪族炭化水素基を組み合わせたもの、すなわち脂肪族炭化水素基中の部位に炭素−炭素二重結合及び炭素−炭素三重結合を同時に含む場合も全て含まれる。脂肪族炭化水素残基は、ハロゲン原子で置換されていてもよく、ハロゲン原子としては、フッ素原子、塩素原子、臭素原子、ヨウ素原子が挙げられ、好ましくはフッ素原子、塩素原子、臭素原子、さらに好ましくはフッ素原子及び臭素原子である。 Of the linear, branched and cyclic aliphatic hydrocarbon groups, preferred are linear or branched aliphatic hydrocarbon groups, and more preferred are linear aliphatic hydrocarbon groups. The saturated or unsaturated aliphatic hydrocarbon group includes a saturated alkyl group, an alkenyl group containing a carbon-carbon double bond, and an alkynyl group containing a carbon-carbon triple bond, and more preferably an alkyl group or an alkynyl group. And more preferably an alkyl group. The aliphatic hydrocarbon residue is a combination of these saturated or unsaturated aliphatic hydrocarbon groups, that is, a carbon-carbon double bond and a carbon-carbon triple bond are simultaneously formed at a site in the aliphatic hydrocarbon group. All cases are included. The aliphatic hydrocarbon residue may be substituted with a halogen atom, and examples of the halogen atom include a fluorine atom, a chlorine atom, a bromine atom, and an iodine atom, preferably a fluorine atom, a chlorine atom, a bromine atom, Preferred are a fluorine atom and a bromine atom.
置換されてもよい芳香族残基としては、フェニル基、ナフチル基、アンスリル基、フェナンスリル基、ピレニル基、ベンゾピレニル基などの芳香族炭化水素基や、ピリジル基、ピラジル基、ピリミジル基、キノリル基、イソキノリル基、ピロリル基、インドレニル基、イミダゾリル基、カルバゾリル基、チエニル基、フリル基、ピラニル基、ピリドニル基などの複素環基、ベンゾキノリル基、アントラキノリル基、ベンゾチエニル基、ベンゾフリル基のような縮合系複素環基が挙げられる。これらのうち好ましいものはフェニル基、ナフチル基、ピリジル基及びチエニル基である。 Examples of the aromatic residue that may be substituted include an aromatic hydrocarbon group such as phenyl group, naphthyl group, anthryl group, phenanthryl group, pyrenyl group, benzopyrenyl group, pyridyl group, pyrazyl group, pyrimidyl group, quinolyl group, Heterocyclic groups such as isoquinolyl group, pyrrolyl group, indolenyl group, imidazolyl group, carbazolyl group, thienyl group, furyl group, pyranyl group, pyridonyl group, etc. A cyclic group is mentioned. Of these, preferred are a phenyl group, a naphthyl group, a pyridyl group, and a thienyl group.
この芳香族残基が有することのできる置換基の例としては、特に制限はないが前記の脂肪族炭化水素基や前記のハロゲン原子が挙げられる。中でも脂肪族炭化水素基が好ましく、メチル、エチル、ｉｓｏ−プロピル等のＣ１−Ｃ３の低級アルキル基がさらに好ましく、メチル基が最も好ましい。 Examples of the substituent that the aromatic residue can have include, but are not limited to, the aliphatic hydrocarbon group and the halogen atom. Among them, an aliphatic hydrocarbon group is preferable, a C1-C3 lower alkyl group such as methyl, ethyl, and iso-propyl is more preferable, and a methyl group is most preferable.
一般式（１）で表わされる有機半導体材料（Ａ）として更に好ましくは、一般式（２）に示すジフェニル誘導体が挙げられる。一般式（２）中、Ｒ１は水素原子又は置換基を有してもよい脂肪族炭化水素残基を表わす。脂肪族炭化水素残基としては、先に説明した脂肪族炭化水素残基と同じであることができ、メチル、エチル、ｉｓｏ−プロピル等のＣ１−Ｃ３の低級アルキル基が好ましく、メチル基が最も好ましい。More preferable examples of the organic semiconductor material (A) represented by the general formula (1) include diphenyl derivatives represented by the general formula (2). In general formula (2), R 1 represents a hydrogen atom or an aliphatic hydrocarbon residue which may have a substituent. The aliphatic hydrocarbon residue may be the same as the aliphatic hydrocarbon residue described above, and is preferably a C1-C3 lower alkyl group such as methyl, ethyl, iso-propyl, and most preferably a methyl group. preferable.
前記一般式（１）で表わされる有機半導体材料以外の有機半導体材料（Ｂ）としては、例えば、アントラセン、テトラセン、ペンタセン、フェナントレン、ピレン、クリセン、ペリレン、コロネン、オリゴフェニレン（ｎ＝４−１２）、ルブレン等の炭化水素系芳香族誘導体、オリゴチオフェン（ｎ＝４−１２）、フタロシアニン、ポルフィリン、ベンゾジチオフェン、ベンゾチエノベンゾチオフェン、ジナフトチエノチオフェン、ナフトジチオフェン等の複素環系芳香族誘導体などが挙げられ、これらの混合物を用いることも可能である。 Examples of the organic semiconductor material (B) other than the organic semiconductor material represented by the general formula (1) include anthracene, tetracene, pentacene, phenanthrene, pyrene, chrysene, perylene, coronene, and oligophenylene (n = 4-12). , Aromatic aromatic derivatives such as rubrene, oligothiophene (n = 4-12), phthalocyanine, porphyrin, benzodithiophene, benzothienobenzothiophene, dinaphthothienothiophene, naphthodithiophene, etc. It is also possible to use a mixture of these.
一般式（１）で表わされる有機半導体材料以外の有機半導体材料（Ｂ）としては、ペンタセン、フタロシアニン、オリゴチオフェンやベンゾチオフェン系、アンスラチオフェン系、ベンゾチエノベンゾチオフェン系等のヘテロアセン系有機半導体材料が挙げられる。その中でも、一般式（３）に示されるベンゾチエノベンゾチオフェンの誘導体が好ましい。一般式（３）中、Ｘ２は置換基を有してもよい脂肪族炭化水素残基又は置換基を有してもよい芳香族残基を表わす。ここに示すＸ２は先に説明したＸ１と同じであることができる。
一般式（１）で表わされる有機半導体材料以外の有機半導体（Ｂ）としては、更に好ましくは一般式（４）に示すジフェニル誘導体がさらに好ましい。一般式（４）中、Ｒ２は水素原子又は置換基を有してもよい脂肪族炭化水素残基を表わす。脂肪族炭化水素残基としては、先に説明した脂肪族炭化水素系残基と同じでよい。Examples of the organic semiconductor material (B) other than the organic semiconductor material represented by the general formula (1) include pentacene, phthalocyanine, oligothiophene, benzothiophene, anthrathiophene, and benzothienobenzothiophene heteroacene organic semiconductor materials. Can be mentioned. Among them, a benzothienobenzothiophene derivative represented by the general formula (3) is preferable. In general formula (3), X 2 represents an aliphatic hydrocarbon residue which may have a substituent or an aromatic residue which may have a substituent. X 2 shown here can be the same as X 1 described above.
As the organic semiconductor (B) other than the organic semiconductor material represented by the general formula (1), a diphenyl derivative represented by the general formula (4) is more preferable. In general formula (4), R 2 represents a hydrogen atom or an aliphatic hydrocarbon residue which may have a substituent. The aliphatic hydrocarbon residue may be the same as the aliphatic hydrocarbon residue described above.
式（１）で表わされる有機半導体材料（Ａ）の製造方法は、例えば特許文献５に記載の方法、すなわち下記反応式で表わすことができる。まず、２，６−ジヒドロキシナフタレンを出発原料として、臭素化を繰り返しテトラブロモ体を得た後、錫を用いて脱ハロゲンし、引き続き無水トリフルオロメタンスルフォン酸を作用させる。この化合物に、更に対応するアセチレン誘導体を非プロトン性極性溶媒中、パラジウム触媒などの存在下で、反応させることで前駆体のジブロモ−ジエチニルナフタレン誘導体を得ることができる。この前駆体を硫化ナトリウム水和物等の硫化物塩を用いて加熱反応を行うことで目的物の一般式（１）の化合物が得られる。
The method for producing the organic semiconductor material (A) represented by the formula (1) can be represented by, for example, the method described in
化合物の精製方法は、特に限定されず、再結晶、カラムクロマトグラフィー、及び真空昇華精製等の公知の方法が採用できる。また必要に応じてこれらの方法を組み合わせて用いてもよい。 The method for purifying the compound is not particularly limited, and known methods such as recrystallization, column chromatography, and vacuum sublimation purification can be employed. Moreover, you may use combining these methods as needed.
一般式（１）で表わされる化合物の具体例を以下に示す。 Specific examples of the compound represented by the general formula (1) are shown below.
一般式（３）で表わされる化合物は、例えば特許文献１及び特許文献６に記載の方法で得ることができる。
The compound represented by the general formula (3) can be obtained by the methods described in
一般式（３）で表わされる化合物の具体例を以下に示す。 Specific examples of the compound represented by the general formula (3) are shown below.
次に図を用いて本発明の電界効果トランジスタの構造について説明するが、本発明はこれらの構造に限定されるものではない。
図１に、本発明の電界効果トランジスタ（素子）のいくつかの態様例を示す。各例において、１がソース電極、２が半導体層、３がドレイン電極、４が絶縁体層、５がゲート電極、６が基板をそれぞれ表す。尚、各層や電極の配置は、素子の用途により適宜選択できる。Ａ〜Ｄ及びＦは基板と並行方向に電流が流れるので、横型ＦＥＴと呼ばれる。Ａはボトムゲートボトムコンタクト型構造、Ｂはトップコンタクトボトムゲート型構造と呼ばれる。Ｂ’はＢの半導体層を二つに分けた、すなわち二層を積層した態様のものである。また、Ｃは半導体上にソース及びドレイン電極、絶縁体層を設け、さらにその上にゲート電極を形成しているトップゲートトップコンタクト型構造である。Ｄはボトムゲートボトム＆トップコンタクト型トランジスタと呼ばれる構造である。Ｅは縦型の構造をもつＦＥＴである静電誘導トランジスタ（ＳＩＴ）の模式図である。このＳＩＴ構造によれば、電流の流れが平面状に広がるので一度に大量のキャリアが移動できる。またソース電極とドレイン電極が縦に配されているので電極間距離を小さくできるため応答が高速である。従って、大電流を流す、あるいは高速のスイッチングを行うなどの用途に好ましく適用できる。また、Ｆはトップゲートボトムコンタクト型であり、Ｆ’はＦの半導体層を二つに分けた、すなわち二層を積層した態様のものある。Next, the structure of the field effect transistor of the present invention will be described with reference to the drawings, but the present invention is not limited to these structures.
FIG. 1 shows some examples of the field effect transistor (element) of the present invention. In each example, 1 represents a source electrode, 2 represents a semiconductor layer, 3 represents a drain electrode, 4 represents an insulator layer, 5 represents a gate electrode, and 6 represents a substrate. In addition, arrangement | positioning of each layer and an electrode can be suitably selected with the use of an element. A-D and F are called lateral FETs because current flows in a direction parallel to the substrate. A is called a bottom gate bottom contact type structure, and B is called a top contact bottom gate type structure. B ′ is a mode in which the semiconductor layer of B is divided into two, that is, two layers are stacked. C is a top gate top contact type structure in which source and drain electrodes and an insulator layer are provided on a semiconductor and a gate electrode is formed thereon. D is a structure called a bottom gate bottom & top contact type transistor. E is a schematic diagram of an electrostatic induction transistor (SIT) which is an FET having a vertical structure. According to this SIT structure, a large amount of carriers can move at a time because the current flow spreads in a plane. Further, since the source electrode and the drain electrode are arranged vertically, the distance between the electrodes can be reduced, so that the response is fast. Therefore, it can be preferably applied to uses such as flowing a large current or performing high-speed switching. F is a top gate bottom contact type, and F ′ is an embodiment in which the semiconductor layer of F is divided into two, that is, two layers are stacked.
各態様例における構成要素につき説明する。
基板６は、その上に形成される各層が剥離することなく保持できることが必要である。例えば樹脂フィルム、紙、ガラス、石英、セラミックなどの絶縁性材料、金属や合金などの導電性基板上にコーティング等により絶縁層を形成した物、樹脂と無機材料など各種組合せからなる材料等が使用しうる。使用しうる樹脂フィルムの例としては、例えばポリエチレンテレフタレート、ポリエチレンナフタレート、ポリエーテルスルホン、ポリアミド、ポリイミド、ポリカーボネート、セルローストリアセテート、ポリエーテルイミドなどが挙げられる。樹脂フィルムや紙を用いると、素子に可撓性を持たせることができ、フレキシブルで、軽量となり、実用性が向上する。基板の厚さとしては、通常１μｍ〜１０ｍｍであり、好ましくは５μｍ〜５ｍｍである。The components in each example will be described.
The
ソース電極１、ドレイン電極３、ゲート電極５には導電性を有する材料が用いられる。例えば、白金、金、銀、アルミニウム、クロム、タングステン、タンタル、ニッケル、コバルト、銅、鉄、鉛、錫、チタン、インジウム、パラジウム、モリブデン、マグネシウム、カルシウム、バリウム、リチウム、カリウム、ナトリウム等の金属及びそれらを含む合金；ＩｎＯ2、ＺｎＯ2、ＳｎＯ2、ＩＴＯ等の導電性酸化物；ポリアニリン、ポリピロール、ポリチオフェン、ポリアセチレン、ポリパラフェニレンビニレン、ポリジアセチレン等の導電性高分子化合物；シリコン、ゲルマニウム、ガリウム砒素等の半導体；カーボンブラック、フラーレン、カーボンナノチューブ、グラファイト等の炭素材料等が使用されうる。また、導電性高分子化合物や半導体にはドーピングが行われていてもよい。その際のドーパントとしては、例えば、塩酸、硫酸、スルホン酸等の酸、ＰＦ5、ＡｓＦ5、ＦｅＣｌ3等のルイス酸、ヨウ素等のハロゲン原子、リチウム、ナトリウム、カリウム等の金属原子等が用いられる。また、上記材料にカーボンブラックや金属粒子などを分散した導電性の複合材料も用いられる。これらの材料は電極の仕事関数を変化させることが出来、良好な電荷注入特性を有する電界効果トランジスタを得ることが出来る。
各電極１、３、５には配線が連結されているが、配線も電極とほぼ同様の材料により作製される。A conductive material is used for the
A wiring is connected to each of the
絶縁体層４としては絶縁性を有する材料が用いられる。例えば、ポリパラキシリレン、ポリアクリレート、ポリメチルメタクリレート、ポリスチレン、ポリビニルフェノール、ポリアミド、ポリイミド、ポリカーボネート、ポリエステル、ポリビニルアルコール、ポリ酢酸ビニル、ポリウレタン、ポリスルホン、エポキシ樹脂、フェノール樹脂、フッ素樹脂等のポリマー及びこれらを組み合わせた共重合体；二酸化珪素、酸化アルミニウム、酸化チタン、酸化タンタル等の酸化物；ＳｒＴｉＯ3、ＢａＴｉＯ3等の強誘電性酸化物；窒化珪素、窒化アルミニウム等の窒化物；硫化物；フッ化物などの誘電体、あるいは、これら誘電体の粒子を分散させたポリマー等が使用しうる。絶縁体層４の膜厚は、材料によって異なるが、通常０．１ｎｍ〜１００μｍ、好ましくは０．５ｎｍ〜５０μｍ、より好ましくは５ｎｍ〜１０μｍである。An insulating material is used for the
半導体層２の材料として、一般式（１）で表される有機半導体材料（Ａ）を単独で使用することもできるが、一般式（１）で表わされる有機半導体材料（Ａ）と、前記一般式（１）で表わされる有機半導体材料以外の有機半導体材料（Ｂ）を組み合わせて用いることもできる。本発明では、有機半導体材料（Ａ）と有機半導体材料（Ｂ）とを混合して使用することもできるし、有機半導体材料（Ａ）の層と有機半導体材料（Ｂ）の層を積層して用いることもできる。半導体層の材料はこれらの構成成分の以外の成分をさらに含んでいてもよいが、当該材料の総重量に対して、有機半導体材料（Ａ）と有機半導体材料（Ｂ）を合計で、５０質量％以上、好ましくは８０質量％以上、更に好ましくは９５質量％以上含むことが必要である。
半導体層２の膜厚は、必要な機能を失わない範囲で、薄いほど好ましい。Ｂ及びＦに示すようなスタガ型の電界効果トランジスタにおいては、膜厚方向の電荷の移動が必要であり、更に膜厚が厚くなると漏れ電流が増加してくることもあるためである。必要な機能を示すために、通常、１ｎｍ〜１μｍ、好ましくは５ｎｍ〜５００ｎｍ、より好ましくは１０ｎｍ〜３００ｎｍである。なお、有機半導体材料（Ａ）を含有する層と有機半導体材料（Ｂ）を含有する層とが積層構造をとっている場合、トータルの膜厚は前述と同じでよい。それぞれの膜厚は必要な機能を失わない範囲で任意に調整できる。またこれらの材料の混合比率や膜厚を調整することによって、良好な半導体特性を有する電界効果トランジスタが得られる。Although the organic semiconductor material (A) represented by the general formula (1) can be used alone as the material of the
The thickness of the
本発明の電界効果トランジスタには各層の間や素子の外面に必要に応じて他の層を設けることができる。例えば、半導体層上に直接または他の層を介して、保護層を形成すると、湿度や酸素などの外気の影響を小さくすることができ、また、素子のＯＮ／ＯＦＦ比を上げることが出来るなど、電気的特性を安定化できる利点もある。
保護層の材料としては特に限定されないが、例えば、エポキシ樹脂、ポリメチルメタクリレート等のアクリル樹脂、ポリウレタン、ポリイミド、ポリビニルアルコール、フッ素樹脂、ポリオレフィン等の各種樹脂からなる膜や、酸化珪素、酸化アルミニウム、窒化珪素等、無機酸化膜や窒化膜等の誘電体からなる膜が好ましく用いられる。特に、酸素や水分の透過率や吸水率の小さな樹脂（ポリマー）が好ましい。近年、有機ＥＬディスプレイ用に開発されている保護材料も使用が可能である。保護層の膜厚は、その目的に応じて任意の膜厚を採用できるが、通常１００ｎｍ〜１ｍｍである。In the field effect transistor of the present invention, other layers can be provided between the layers or on the outer surface of the element as necessary. For example, when a protective layer is formed directly on the semiconductor layer or via another layer, the influence of outside air such as humidity and oxygen can be reduced, and the ON / OFF ratio of the element can be increased. There is also an advantage that the electrical characteristics can be stabilized.
Although it does not specifically limit as a material of a protective layer, For example, the film | membrane which consists of various resins, such as acrylic resins, such as an epoxy resin and polymethylmethacrylate, polyurethane, polyimide, polyvinyl alcohol, a fluororesin, polyolefin, silicon oxide, aluminum oxide, A film made of a dielectric such as an inorganic oxide film or a nitride film such as silicon nitride is preferably used. In particular, a resin (polymer) having low oxygen and moisture permeability and water absorption is preferable. In recent years, protective materials developed for organic EL displays can also be used. Although the film thickness of a protective layer can employ | adopt arbitrary film thickness according to the objective, it is 100 nm-1 mm normally.
また半導体が積層される基板または絶縁体層上などに表面処理を行うことにより、素子の特性を向上させることが可能である。例えば基板表面の親水性／疎水性の度合いを調整することにより、その上に成膜される膜の膜質を改良しうる。特に、有機半導体材料は分子の配向など膜の状態によって特性が大きく変わることがある。そのため、基板表面処理によって、基板とその後に成膜される半導体膜との界面部分の分子配向が制御され、キャリア移動度等の特性が改良されるものと考えられる。このような基板処理としては、例えば、ヘキサメチルジシラザン、シクロヘキセン、オクタデシルトリクロロシラン等による疎水化処理、塩酸や硫酸、酢酸等による酸処理、水酸化ナトリウム、水酸化カリウム、水酸化カルシウム、アンモニア等によるアルカリ処理、オゾン処理、フッ素化処理、酸素やアルゴン等のプラズマ処理、ラングミュア・ブロジェット膜の形成処理、その他の絶縁体や半導体の薄膜の形成処理、機械的処理、コロナ放電などの電気的処理、繊維等を利用したラビング処理等が挙げられる。 In addition, by performing surface treatment on a substrate or an insulator layer over which a semiconductor is stacked, the characteristics of the element can be improved. For example, by adjusting the degree of hydrophilicity / hydrophobicity of the substrate surface, the film quality of the film formed thereon can be improved. In particular, the characteristics of organic semiconductor materials can vary greatly depending on the state of the film, such as molecular orientation. Therefore, it is considered that the substrate surface treatment controls the molecular orientation at the interface portion between the substrate and the semiconductor film formed thereafter, and improves characteristics such as carrier mobility. Examples of such substrate treatment include hydrophobization treatment with hexamethyldisilazane, cyclohexene, octadecyltrichlorosilane, acid treatment with hydrochloric acid, sulfuric acid, acetic acid, sodium hydroxide, potassium hydroxide, calcium hydroxide, ammonia, etc. Electrical treatment such as alkali treatment with ozone, ozone treatment, fluorination treatment, plasma treatment with oxygen and argon, Langmuir / Blodgett film formation process, other insulator and semiconductor thin film formation process, mechanical process, corona discharge, etc. Examples thereof include rubbing treatment using treatment, fibers, and the like.
これらの態様において各層を設ける方法としては、例えば真空蒸着法、スパッタ法、塗布法、印刷法、ゾルゲル法等が適宜採用できる。 As a method of providing each layer in these embodiments, for example, a vacuum deposition method, a sputtering method, a coating method, a printing method, a sol-gel method, or the like can be appropriately employed.
次に、本発明に係る電界効果トランジスタの製造方法について、図１の態様例Ｂに示すトップコンタクトボトムゲート型電界効果トランジスタ（ＦＥＴ）を例として、図２に基づき以下に説明する。
この製造方法は前記した他の態様の電界効果トランジスタ等にも同様に適用しうるものである。Next, a method for manufacturing a field effect transistor according to the present invention will be described below with reference to FIG. 2, taking a top contact bottom gate field effect transistor (FET) shown in the example B of FIG. 1 as an example.
This manufacturing method can be similarly applied to the field effect transistors of the other embodiments described above.
（基板及び基板処理）
基板６上に必要な層や電極を設けることで作製される（図２（１）参照）。基板としては上記で説明したものを用いうる。この基板上に前述の表面処理などを行うことも可能である。基板６の厚みは、必要な機能を妨げない範囲で薄い方が好ましい。材料によっても異なるが、通常１μｍ〜１０ｍｍであり、好ましくは５μｍ〜５ｍｍである。また、必要により、基板に電極の機能を持たせるようにしてもよい。(Substrate and substrate processing)
It is manufactured by providing necessary layers and electrodes on the substrate 6 (see FIG. 2 (1)). As the substrate, those described above can be used. It is also possible to perform the above-described surface treatment or the like on this substrate. The thickness of the
（ゲート電極の形成）
基板６上にゲート電極５を形成する（図２（２）参照）。電極材料としては上記で説明したものが用いられる。電極膜を成膜する方法としては、各種の方法を用いることが出来、例えば真空蒸着法、スパッタ法、塗布法、熱転写法、印刷法、ゾルゲル法等が採用される。成膜時又は成膜後、所望の形状になるよう必要に応じてパターニングを行うのが好ましい。パターニングの方法としても各種の方法を用いうるが、例えばフォトレジストのパターニングとエッチングを組み合わせたフォトリソグラフィー法等が挙げられる。又、インクジェット印刷、スクリーン印刷、オフセット印刷、凸版印刷等の印刷法、マイクロコンタクトプリンティング法等のソフトリソグラフィーの手法、及びこれら手法を複数組み合わせた手法を利用し、パターニングすることも可能である。ゲート電極５の膜厚は、材料によっても異なるが、通常０．１ｎｍ〜１０μｍであり、好ましくは０．５ｎｍ〜５μｍであり、より好ましくは１ｎｍ〜３μｍである。また、ゲート電極と基板を兼ねる場合は上記の膜厚より大きくてもよい。(Formation of gate electrode)
A
（絶縁体層の形成）
ゲート電極５上に絶縁層４を形成する（図２（３）参照）。絶縁体材料としては上記で説明したもの等が用られる。絶縁体層４を形成するにあたっては各種の方法を用いうる。例えばスピンコーティング、スプレーコーティング、ディップコーティング、キャスト、バーコート、ブレードコーティングなどの塗布法、スクリーン印刷、オフセット印刷、インクジェット等の印刷法、真空蒸着法、分子線エピタキシャル成長法、イオンクラスタービーム法、イオンプレーティング法、スパッタリング法、大気圧プラズマ法、ＣＶＤ法などのドライプロセス法が挙げられる。その他、ゾルゲル法やアルミニウム上のアルマイト、シリコンの熱酸化膜のように金属上に酸化物膜を形成する方法等が採用される。
なお、絶縁体層と半導体層が接する部分においては、両層の界面で半導体分子を良好に配向させるために、絶縁体層に所定の表面処理を行うことができる。表面処理の手法は、基板の表面処理と同様のものが用いうる。絶縁体層４の膜厚は、その機能を損なわない範囲で薄い方が好ましい。通常０．１ｎｍ〜１００μｍであり、好ましくは０．５ｎｍ〜５０μｍであり、より好ましくは５ｎｍ〜１０μｍである。(Formation of insulator layer)
An insulating
Note that, in a portion where the insulator layer and the semiconductor layer are in contact with each other, a predetermined surface treatment can be performed on the insulator layer in order to favorably align the semiconductor molecules at the interface between the two layers. As the surface treatment method, the same surface treatment as that of the substrate can be used. The thickness of the
（半導体層の形成）
半導体材料としては上記で説明したような材料が使用される。半導体層を成膜するにあたっては、各種の方法を用いることが出来る。スパッタリング法、ＣＶＤ法、分子線エピタキシャル成長法、真空蒸着法等の真空プロセスでの形成方法と、ディップコート法、ダイコーター法、ロールコーター法、バーコーター法、スピンコート法等の塗布法、インクジェット法、スクリーン印刷法、オフセット印刷法、マイクロコンタクト印刷法などの溶液プロセスでの形成方法に大別される。以下、半導体層の形成方法について詳細に説明する。(Formation of semiconductor layer)
As the semiconductor material, the materials described above are used. Various methods can be used for forming the semiconductor layer. Formation method in vacuum process such as sputtering method, CVD method, molecular beam epitaxial growth method, vacuum deposition method, coating method such as dip coating method, die coater method, roll coater method, bar coater method, spin coating method, ink jet method In addition, it is roughly classified into formation methods in solution processes such as screen printing, offset printing, and microcontact printing. Hereinafter, a method for forming a semiconductor layer will be described in detail.
まず、材料を真空プロセスによって成膜し半導体層を得る方法について説明する。
前記半導体材料をルツボや金属のボート中で真空下、加熱し、蒸発した半導体材料を基板（絶縁体層、ソース電極及びドレイン電極の露出部）に付着（蒸着）させる方法（真空蒸着法）が好ましく採用される。この際、真空度は、通常１．０×１０−１Ｐａ以下、好ましくは１．０×１０−４Ｐａ以下である。また、蒸着時の基板温度によって半導体膜、ひいては電界効果トランジスタの特性が変化するので、注意深く基板温度を選択するのが好ましい。蒸着時の基板温度は通常、０〜２００℃、好ましくは１０〜１５０℃である。また、蒸着速度は、通常０．００１ｎｍ／秒〜１０ｎｍ／秒であり、好ましくは０．０１ｎｍ／秒〜１ｎｍ／秒である。
また半導体材料を積層構造とするためには、順次に各々の材料を加熱、蒸発させ、積層させることにより得られる。混合する場合には、通常、各々の材料を同時に加熱、蒸発させる共蒸着により材料の混合した構造の半導体層を得ることが出来る。First, a method for obtaining a semiconductor layer by depositing a material by a vacuum process will be described.
A method (vacuum deposition method) in which the semiconductor material is heated in a crucible or a metal boat under vacuum and the evaporated semiconductor material is attached (deposited) to a substrate (exposed portions of the insulator layer, the source electrode and the drain electrode). Preferably employed. Under the present circumstances, a vacuum degree is 1.0 * 10 < -1 > Pa or less normally, Preferably it is 1.0 * 10 <-4> Pa or less. In addition, since the characteristics of the semiconductor film and hence the field effect transistor vary depending on the substrate temperature during vapor deposition, it is preferable to select the substrate temperature carefully. The substrate temperature during vapor deposition is usually 0 to 200 ° C, preferably 10 to 150 ° C. The deposition rate is usually 0.001 nm / second to 10 nm / second, preferably 0.01 nm / second to 1 nm / second.
Moreover, in order to make a semiconductor material into a laminated structure, each material is obtained by heating and evaporating and laminating sequentially. In the case of mixing, usually, a semiconductor layer having a structure in which the materials are mixed can be obtained by co-evaporation in which each material is heated and evaporated simultaneously.
本発明における有機の半導体材料は、比較的低分子化合物であるため、このような真空プロセスが好ましく用いうる。このような真空プロセスには、やや高価な設備が必要であるというものの、成膜性が良く均一な膜が得られやすいという利点がある。 Since the organic semiconductor material in the present invention is a relatively low molecular compound, such a vacuum process can be preferably used. Although such a vacuum process requires somewhat expensive equipment, there is an advantage that a uniform film can be easily obtained with good film formability.
次に、半導体材料を溶液プロセスによって成膜し半導体層を得る方法について説明する。この方法は一般的には溶媒に溶解する有機の半導体材料の場合に使用することが多い。
この方法では、前記材料を溶媒に溶解又は分散し、基板（絶縁体層、ソース電極及びドレイン電極の露出部）に塗布する。塗布の方法としては、キャスティング、スピンコーティング、ディップコーティング、ブレードコーティング、ワイヤバーコーティング、スプレーコーティング等のコーティング法や、インクジェット印刷、スクリーン印刷、オフセット印刷、凸版印刷等の印刷法、マイクロコンタクトプリンティング法等のソフトリソグラフィーの手法等、さらにはこれらの手法を複数組み合わせた方法を採用しうる。これらの方法により形成される半導体層の膜厚は、機能を損なわない範囲で薄い方が好ましい。膜厚が厚くなると漏れ電流が大きくなり、膜厚方向の電荷の移動の為にエネルギーが必要となる懸念がある。半導体層の膜厚は、通常１ｎｍ〜１μｍ、好ましくは５ｎｍ〜５００ｎｍ、より好ましくは１０ｎｍ〜３００ｎｍである。
また半導体材料の混合膜は、各材料を一緒に溶解させ、上記のプロセスで成膜することによって容易に得られる。しかし積層構造とするためには、それぞれの材料の溶媒への溶解度の問題や、積層時に先に出来た膜が後から成膜する材料の溶液に浸食されてしまうこともあり、成膜条件の最適化が必要となる。半導体層を形成するにあたり、このような溶液プロセスを用いると、比較的安価な設備で大面積の電界効果トランジスタを製造できるという利点がある。また溶液プロセスの後に真空プロセスを用いるなど、組み合わせて成膜することも可能である。Next, a method for obtaining a semiconductor layer by forming a semiconductor material by a solution process will be described. This method is generally used in the case of an organic semiconductor material that is soluble in a solvent.
In this method, the material is dissolved or dispersed in a solvent and applied to a substrate (exposed portions of the insulator layer, the source electrode, and the drain electrode). Coating methods include casting, spin coating, dip coating, blade coating, wire bar coating, spray coating, and other coating methods, inkjet printing, screen printing, offset printing, letterpress printing, and other micro contact printing methods. The method of soft lithography, etc., or a method combining a plurality of these methods may be employed. The thickness of the semiconductor layer formed by these methods is preferably thin as long as the function is not impaired. As the film thickness increases, the leakage current increases, and there is a concern that energy is required for the movement of charges in the film thickness direction. The film thickness of the semiconductor layer is usually 1 nm to 1 μm, preferably 5 nm to 500 nm, more preferably 10 nm to 300 nm.
A mixed film of semiconductor materials can be easily obtained by dissolving each material together and forming the film by the above process. However, in order to obtain a laminated structure, the solubility of each material in a solvent and the film formed earlier during lamination may be eroded by the solution of the material to be formed later. Optimization is required. When such a solution process is used for forming a semiconductor layer, there is an advantage that a large-area field effect transistor can be manufactured with relatively inexpensive equipment. It is also possible to form a film in combination, such as using a vacuum process after the solution process.
このように形成された半導体層（図２（４）参照）は、後処理によりさらに特性を改良することが可能である。例えば、加熱処理により、成膜時に生じた膜中の歪みを緩和することができ、特性の向上や安定化を図ることができる。さらに、酸素や水素等の酸化性あるいは還元性の気体や液体にさらすことにより、酸化あるいは還元による特性変化を誘起することもできる。これは、例えば膜中のキャリア密度の増加あるいは減少の目的で利用することができる。 The semiconductor layer thus formed (see FIG. 2D) can be further improved in characteristics by post-processing. For example, the heat treatment can relieve distortion in the film generated during film formation, and can improve and stabilize characteristics. Furthermore, a change in characteristics due to oxidation or reduction can be induced by exposure to an oxidizing or reducing gas or liquid such as oxygen or hydrogen. This can be used for the purpose of increasing or decreasing the carrier density in the film, for example.
（ソース電極及びドレイン電極の形成）
ソース電極１及びドレイン電極３の形成方法等はゲート電極５の形成方法に準じて形成することが出来る（図２（５）参照）。半導体層の上に電極が位置するトップコンタクト構造の場合はシャドウマスクを用いた真空蒸着法が一般的に使用されており、逆に半導体層の下に位置するボトムコンタクト構造の場合はフォトリソグラフィーや各種印刷法を用いて電極のパターニングを形成することが多い。(Formation of source electrode and drain electrode)
The
（保護層）
半導体層上に保護層７を形成するには各種の方法を採用しうる。保護層が樹脂からなる場合は、例えば、樹脂溶液を塗布後、乾燥させて樹脂膜とする方法、樹脂モノマーを塗布あるいは蒸着したのち重合する方法などが挙げられる。成膜後に架橋処理を行ってもよい。保護層が無機物からなる場合は、例えば、スパッタリング法、蒸着法等の真空プロセスでの形成方法や、ゾルゲル法等の溶液プロセスでの形成方法も用いることができる。
本発明の電界効果トランジスタにおいては半導体層上の他、各層の間にも必要に応じて保護層を設けることが出来る。それらの層は電界効果トランジスタの電気的特性の安定化に寄与する場合がある。(Protective layer)
Various methods can be employed to form the
In the field effect transistor of the present invention, a protective layer can be provided between the layers as needed in addition to the semiconductor layer. These layers may contribute to stabilization of the electrical characteristics of the field effect transistor.
電界効果トランジスタの動作特性は、半導体層のキャリア移動度、絶縁層の静電容量、素子の構成（ソース・ドレイン電極間距離及び幅等）などにより決まる。電界効果トランジスタに用いる半導体材料としては、半導体層を形成した場合のキャリア移動度が高いものほど好ましい。本発明の電界効果トランジスタの半導体層は、前記一般式（５）で表わされるナフトジチオフェン系化合物を含むことができ、また、一般式（１）で表される有機半導体材料（Ａ）を含有する層と、前記一般式（１）で表わされる有機半導体材料以外の有機半導体材料（Ｂ）を含有する層とを半導体層として積層することもできる。前記積層型の電界効果トランジスタを用いると大気中において安定であり、寿命が長いという利点がある。またヒステリシスが低減しており、さらに低い閾値電圧を有することから、実際の使用においては、駆動電圧が低くなり、消費電力が従来のものよりも低下することにより省エネルギー化が可能となる。さらに閾値電圧の低下によって電極から半導体膜への電荷の注入障壁が低減されることにより、半導体素子及びそれを有する半導体デバイス自体の耐久性の向上にも効果があり、均一性及び信頼性の増した電界効果トランジスタを得ることができる。 The operating characteristics of the field effect transistor are determined by the carrier mobility of the semiconductor layer, the capacitance of the insulating layer, the element configuration (distance and width between source and drain electrodes, etc.), and the like. As a semiconductor material used for the field effect transistor, a material having higher carrier mobility when a semiconductor layer is formed is preferable. The semiconductor layer of the field effect transistor of the present invention can contain a naphthodithiophene compound represented by the general formula (5) and also contains an organic semiconductor material (A) represented by the general formula (1). And a layer containing an organic semiconductor material (B) other than the organic semiconductor material represented by the general formula (1) can be stacked as a semiconductor layer. Use of the stacked field effect transistor is advantageous in that it is stable in the atmosphere and has a long lifetime. In addition, since the hysteresis is reduced and the threshold voltage is lower, in actual use, the driving voltage is lowered, and the power consumption is reduced as compared with the conventional one, thereby enabling energy saving. Further, the barrier for charge injection from the electrode to the semiconductor film is reduced by lowering the threshold voltage, so that the durability of the semiconductor element and the semiconductor device having the semiconductor element itself is also improved, and the uniformity and reliability are increased. A field effect transistor can be obtained.
以下、実施例を挙げて本発明を更に詳細に説明するが、本発明はこれらの例に限定されるものではない。実施例中、特に指定しない限り、部は質量部を、％は質量％をそれぞれ表わす。 EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated still in detail, this invention is not limited to these examples. In the examples, unless otherwise specified, parts represent parts by mass and% represents mass%.
実施例１
３，７−ジブロモ−２，６−ビス（４−トリルエチニル）ナフタレンの合成
窒素雰囲気下において、３，７−ジブロモ−２，６−ビス（トリフルオロメタンスルフォニルオキシ）ナフタレン（１．２ｇ，２．０ｍｍｏｌ）をＤＭＦ（１５ｍｌ）とＤＩＰＡ（１５ｍｌ）の混合溶液に溶解させ、アルゴンガスを用いて３０分間脱気を行った。これに、Ｐｄ（ＰＰｈ３）２Ｃｌ２（０．１４ｇ，０．１ｍｍｏｌ，１０ｍｏｌ％）とＣｕＩ（０．０７６ｇ，０．２ｍｍｏｌ，２０ｍｏｌ％）と４−エチニルトルエンとを加え、室温で２時間攪拌し、薗頭カップリングを行った。その後、析出した生成物を濾取し、水、エタノール、ヘキサンにて洗浄した。それをクロロホルムで再結晶を行うことで精製し、３，７−ジブロモ−２，６−ビス（４−トリルエチニル）ナフタレンを白色固体として得た（０．５７ｇ，５６％）。
1H NMR(400 MHz, CDCl3 ) δ 8.04 (s, 2H, ArH), 7.93 (s, 2H, ArH), 7.52 (d, 4H, J= 8.0 Hz, PhH), 7.21 (d, 4H, J= 8.0 Hz, PhH ), 2.35 (s, 6H, CH3).Example 1
Synthesis of 3,7-dibromo-2,6-bis (4-tolylethynyl) naphthalene
Under a nitrogen atmosphere, 3,7-dibromo-2,6-bis (trifluoromethanesulfonyloxy) naphthalene (1.2 g, 2.0 mmol) was dissolved in a mixed solution of DMF (15 ml) and DIPA (15 ml), and argon Degassing was performed using gas for 30 minutes. To this was added Pd (PPh 3 ) 2 Cl 2 (0.14 g, 0.1 mmol, 10 mol%), CuI (0.076 g, 0.2 mmol, 20 mol%) and 4-ethynyltoluene, and 2 hours at room temperature. Stir and perform Sonogashira coupling. Thereafter, the precipitated product was collected by filtration and washed with water, ethanol and hexane. It was purified by recrystallization from chloroform to obtain 3,7-dibromo-2,6-bis (4-tolylethynyl) naphthalene as a white solid (0.57 g, 56%).
1 H NMR (400 MHz, CDCl 3 ) δ 8.04 (s, 2H, ArH), 7.93 (s, 2H, ArH), 7.52 (d, 4H, J = 8.0 Hz, PhH), 7.21 (d, 4H, J = 8.0 Hz, PhH), 2.35 (s, 6H, CH 3 ).
実施例２
３，７−ジブロモ−２，６−ビス（３−トリルエチニル）ナフタレンの合成
４−エチニルトルエンの代わりに３−エチニルトルエンを使用すること以外は実施例１と同様の操作を行い、３，７−ジブロモ−２，６−ビス（３−トリルエチニル）ナフタレンが黄色固体として得られた（５４％）。
1H NMR(400 MHz, CDCl3 ) δ 8.05 (s, 2H, ArH), 7.94 (s, 2H, ArH), 7.45 (d, 2H, J= 12.0 Hz, PhH ), 7.30 (t, 2H, J= 8.0 Hz, PhH), 7.20 (d, 2H, J= 4.0 Hz, PhH ), 2.35 (s, 6H, CH3).Example 2
Synthesis of 3,7-dibromo-2,6-bis (3-tolylethynyl) naphthalene
The same operation as in Example 1 was performed except that 3-ethynyltoluene was used instead of 4-ethynyltoluene to obtain 3,7-dibromo-2,6-bis (3-tolylethynyl) naphthalene as a yellow solid. (54%).
1 H NMR (400 MHz, CDCl 3 ) δ 8.05 (s, 2H, ArH), 7.94 (s, 2H, ArH), 7.45 (d, 2H, J = 12.0 Hz, PhH), 7.30 (t, 2H, J = 8.0 Hz, PhH), 7.20 (d, 2H, J = 4.0 Hz, PhH), 2.35 (s, 6H, CH 3 ).
実施例３
２，７−ビス（４−トリル）−ナフト［２，３−ｂ：７，６−ｂ’］ジチオフェン（化合物（６））の合成
Ｎａ２Ｓ・９Ｈ２Ｏ（０．９６ｇ，４．０ｍｍｏｌ）をＮＭＰ（３０ｍｌ）に溶解させ、１９０℃、大気下で１時間攪拌した後、３，７−ジブロモ−２，６−ビス（４−トリルエチニル）ナフタレン（０．５７ｇ、１．０ｍｍｏｌ）のＮＭＰ溶液を滴下し、１６時間攪拌した。その後、反応溶液を飽和塩化アンモニウム水溶液（３００ｍｌ）中に注ぎ、固体を析出させた。これを濾取し、水、エタノール、ヘキサン、塩化メチレン、クロロホルムの順で洗浄した。得られた粗生成物を、真空下、３６０℃にて昇華精製を行い２，７−ビス（４−トリル）−ナフト［２，３−ｂ：７，６−ｂ’］ジチオフェンを黄色固体として得た（０．２６ｇ，６３％）。
質量分析ＭＳ （ＥＩ＝７０ｅＶ）ｍ／ｚ＝４２０（Ｍ＋）（島津 ＧＣＭＳ−ＱＰ ２０１０ＳＥ）
吸収スペクトル：λｍａｘ４４６，４７８ｎｍ（薄膜）（島津自記分光光度計 ＵＶ−３６００型（Ｐ／Ｎ２０６−１３５００））
元素分析：Ａｎａｌ．Ｃａｌｃｄ（％）ｆｏｒ Ｃ２８Ｈ２０Ｓ２：Ｃ７９．９６，Ｈ４．７９；ｆｏｕｎｄ Ｃ８０．０４，Ｈ４．７９Example 3
Synthesis of 2,7-bis (4-tolyl) -naphtho [2,3-b: 7,6-b ′] dithiophene (compound (6))
Na 2 S · 9H 2 O (0.96 g, 4.0 mmol) was dissolved in NMP (30 ml), stirred at 190 ° C. in the atmosphere for 1 hour, and then 3,7-dibromo-2,6-bis (4 -Tolylethynyl) naphthalene (0.57 g, 1.0 mmol) in NMP was added dropwise and stirred for 16 hours. Thereafter, the reaction solution was poured into a saturated aqueous ammonium chloride solution (300 ml) to precipitate a solid. This was collected by filtration and washed with water, ethanol, hexane, methylene chloride, and chloroform in this order. The obtained crude product was purified by sublimation at 360 ° C. under vacuum to obtain 2,7-bis (4-tolyl) -naphtho [2,3-b: 7,6-b ′] dithiophene as a yellow solid. Obtained (0.26 g, 63%).
Mass spectrometry MS (EI = 70 eV) m / z = 420 (M + ) (Shimadzu GCMS-QP 2010SE)
Absorption spectrum: λmax 446, 478 nm (thin film) (Shimadzu autograph spectrophotometer UV-3600 type (P / N206-13500))
Elemental analysis: Anal. Calcd (%) for C 28 H 20 S 2: C79.96, H4.79; found C80.04, H4.79
実施例４
２，７−ビス（３−トリル）−ナフト［２，３−ｂ：７，６−ｂ’］ジチオフェン（化合物（７））の合成
３，７−ジブロモ−２，６−ビス（４−トリルエチニル）ナフタレンの代わりに３，７−ジブロモ−２，６−ビス（３−トリエチニル）ナフタレンに代えた以外は実施例３と同様の操作を行い２，７−ビス（３−トリル）−ナフト［２，３−ｂ：７，６−ｂ’］ジチオフェンを得た（４６％）。
質量分析ＭＳ（ＥＩ＝７０ｅＶ）ｍ／ｚ＝４２０（Ｍ＋）（島津 ＧＣＭＳ−ＱＰ ２０１０ＳＥ）
吸収スペクトル：λｍａｘ４４６，４７８ｎｍ（薄膜）（島津自記分光光度計 ＵＶ−３６００型（Ｐ／Ｎ２０６−１３５００））
元素分析：Ａｎａｌ．Ｃａｌｃｄ（％）ｆｏｒ Ｃ２８Ｈ２０Ｓ２：Ｃ７９．９６，Ｈ４．７９；ｆｏｕｎｄ Ｃ８０．２２，Ｈ４．５９Example 4
Synthesis of 2,7-bis (3-tolyl) -naphtho [2,3-b: 7,6-b ′] dithiophene (compound (7))
The same operation as in Example 3 except that 3,7-dibromo-2,6-bis (3-triethynyl) naphthalene was used instead of 3,7-dibromo-2,6-bis (4-tolylethynyl) naphthalene. To give 2,7-bis (3-tolyl) -naphtho [2,3-b: 7,6-b ′] dithiophene (46%).
Mass spectrometry MS (EI = 70 eV) m / z = 420 (M + ) (Shimadzu GCMS-QP 2010SE)
Absorption spectrum: λmax 446, 478 nm (thin film) (Shimadzu autograph spectrophotometer UV-3600 type (P / N206-13500))
Elemental analysis: Anal. Calcd (%) for C 28 H 20 S 2: C79.96, H4.79; found C80.22, H4.59
実施例５ 化合物（６）（ｐ−ｔｏｌｙｌＮＤＴ）の電界効果トランジスタの作製
オクタデシルトリクロロシラン処理を行った２００ｎｍのＳｉＯ２熱酸化膜付きｎドープシリコンウェハー（面抵抗０．０２Ω・ｃｍ以下）を真空蒸着装置内に設置し、装置内の真空度が５．０×１０−３Ｐａ以下になるまで排気した。抵抗加熱蒸着法によって、この電極に基板温度約１００℃の条件下、化合物（６）を１〜２Å／ｓｅｃの蒸着速度で５０ｎｍの厚さに蒸着し、半導体層（２）を形成した。次いでこの基板に電極作成用シャドウマスクを取り付け、真空蒸着装置内に設置し、装置内の真空度が１．０×１０−４Ｐａ以下になるまで排気し、抵抗加熱蒸着法によって、金の電極、すなわちソース電極（１）及びドレイン電極（３）を４０ｎｍの厚さに蒸着し、ＴＣ（トップコンタクト）型である本発明の電界効果トランジスタ（チャネル長５０μｍ、チャネル幅１．５ｍｍ）を得た。Example 5 Production of Field Effect Transistor of Compound (6) (p-tolylNDT) An n-doped silicon wafer with 200 nm SiO 2 thermal oxide film (surface resistance 0.02 Ω · cm or less) subjected to octadecyltrichlorosilane treatment was vacuum deposited. It installed in the apparatus and exhausted until the vacuum degree in the apparatus was set to 5.0 * 10 < -3 > Pa or less. The compound (6) was deposited on this electrode at a substrate temperature of about 100 ° C. at a deposition rate of 1 to 2 liters / sec to a thickness of 50 nm by a resistance heating deposition method to form a semiconductor layer (2). Next, a shadow mask for electrode preparation is attached to this substrate, and it is placed in a vacuum vapor deposition apparatus. The vacuum in the apparatus is evacuated to 1.0 × 10 −4 Pa or less, and a gold electrode is formed by resistance heating vapor deposition. That is, the source electrode (1) and the drain electrode (3) were deposited to a thickness of 40 nm to obtain a TC (top contact) type field effect transistor (
なお、本実施例における電界効果トランジスタにおいては、熱酸化膜付きｎドープシリコンウェハーにおける熱酸化膜が絶縁層（４）の機能を有し、ｎドープシリコンウェハーが基板（６）及びゲート電極（５）の機能を兼ね備えている（図３参照）。得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−６０Ｖとし、ゲート電圧を６０Ｖから−６０Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は１．３１ｃｍ２／Ｖｓであり、閾値電圧は４８Ｖ、Ｉｏｎ／Ｉｏｆｆは１０６であった。In the field effect transistor of this example, the thermal oxide film in the n-doped silicon wafer with the thermal oxide film has the function of the insulating layer (4), and the n-doped silicon wafer is the substrate (6) and the gate electrode (5). ) (See FIG. 3). The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −60 V, the gate voltage was scanned from 60 V to −60 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of the device was 1.31cm 2 / Vs, the threshold voltage is 48V, Ion / Ioff was 10 6.
実施例６ 化合物（７）（ｍ−ｔｏｌｙｌＮＤＴ）の電界効果トランジスタの作製
オクチルトリクロロシラン処理を行った２００ｎｍのＳｉＯ２熱酸化膜付きｎドープシリコンウェハー（面抵抗０．０２Ω・ｃｍ以下）を真空蒸着装置内に設置し、装置内の真空度が５．０×１０−３Ｐａ以下になるまで排気した。抵抗加熱蒸着法によって、この電極に基板温度約１００℃の条件下、化合物（７）を１〜２Å／ｓｅｃの蒸着速度で５０ｎｍの厚さに蒸着し、半導体層（２）を形成した。次いでこの基板に電極作成用シャドウマスクを取り付け、真空蒸着装置内に設置し、装置内の真空度が１．０×１０−４Ｐａ以下になるまで排気し、抵抗加熱蒸着法によって、金の電極、すなわちソース電極（１）及びドレイン電極（３）を４０ｎｍの厚さに蒸着し、ＴＣ（トップコンタクト）型である本発明の電界効果トランジスタ（チャネル長５０μｍ、チャネル幅１．５ｍｍ）を得た。Example 6 Production of Field Effect Transistor of Compound (7) (m-tolyl NDT) An n-doped silicon wafer with 200 nm SiO 2 thermal oxide film (surface resistance 0.02 Ω · cm or less) subjected to octyltrichlorosilane treatment was vacuum deposited. It installed in the apparatus and exhausted until the vacuum degree in the apparatus was set to 5.0 * 10 < -3 > Pa or less. The compound (7) was vapor-deposited on the electrode at a substrate temperature of about 100 ° C. at a deposition rate of 1 to 2 liters / sec to a thickness of 50 nm by a resistance heating vapor deposition method to form a semiconductor layer (2). Next, a shadow mask for electrode preparation is attached to this substrate, and it is placed in a vacuum vapor deposition apparatus. The vacuum in the apparatus is evacuated to 1.0 × 10 −4 Pa or less, and a gold electrode is formed by resistance heating vapor deposition. That is, the source electrode (1) and the drain electrode (3) were deposited to a thickness of 40 nm to obtain a TC (top contact) type field effect transistor (
得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−６０Ｖとし、ゲート電圧を２０Ｖから−６０Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は０．３４ｃｍ２／Ｖｓであり、閾値電圧は−２Ｖ、Ｉｏｎ／Ｉｏｆｆは１０５であった。The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −60 V, the gate voltage was scanned from 20 V to −60 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of the device was 0.34 cm 2 / Vs, the threshold voltage is -2 V, Ion / Ioff was 10 5.
実施例７ 化合物（６）（ｐ−ｔｏｌｙｌＮＤＴ）と化合物（２３）（ＤＰｈ−ＢＴＢＴ）の積層型電界効果トランジスタの作製
オクチルトリクロロシラン処理を行った２００ｎｍのＳｉＯ２熱酸化膜付きｎドープシリコンウェハー（面抵抗０．０２Ω・ｃｍ以下）を真空蒸着装置内に設置し、装置内の真空度が５．０×１０−３Ｐａ以下になるまで排気した。抵抗加熱蒸着法によって、この電極に基板温度約２５℃の条件下、化合物（２３）を１〜２Å／ｓｅｃの蒸着速度で５０ｎｍの厚さに蒸着し、次いで化合物（６）を１〜２Å／ｓｅｃの蒸着速度で５ｎｍの厚さに蒸着し半導体層（２）を形成した。次いでこの基板に電極作成用シャドウマスクを取り付け、真空蒸着装置内に設置し、装置内の真空度が１．０×１０−４Ｐａ以下になるまで排気し、抵抗加熱蒸着法によって、金の電極、すなわちソース電極（１）及びドレイン電極（３）、を４０ｎｍの厚さに蒸着し、ＴＣ（トップコンタクト）型である本発明の電界効果トランジスタ（チャネル長５０μｍ、チャネル幅１．５ｍｍ）を得た。Example 7 Production of Stacked Field Effect Transistor of Compound (6) (p-tolyl NDT) and Compound (23) (DPh-BTBT) An n-doped silicon wafer with 200 nm SiO 2 thermal oxide film subjected to octyltrichlorosilane treatment ( A surface resistance of 0.02 Ω · cm or less) was placed in a vacuum deposition apparatus, and evacuated until the degree of vacuum in the apparatus was 5.0 × 10 −3 Pa or less. By resistance heating vapor deposition, compound (23) was vapor-deposited on this electrode at a substrate temperature of about 25 ° C. at a vapor deposition rate of 1 to 2 Å / sec to a thickness of 50 nm, and then compound (6) was added to 1 to 2 Å / sec. A semiconductor layer (2) was formed by vapor deposition to a thickness of 5 nm at a deposition rate of sec. Next, a shadow mask for electrode preparation is attached to this substrate, and it is placed in a vacuum vapor deposition apparatus. The vacuum in the apparatus is evacuated to 1.0 × 10 −4 Pa or less, and a gold electrode is formed by resistance heating vapor deposition. That is, the source electrode (1) and the drain electrode (3) are deposited to a thickness of 40 nm to obtain a field effect transistor (
得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−６０Ｖとし、ゲート電圧を２０Ｖから−６０Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は３．１ｃｍ２／Ｖｓであり、閾値電圧は−７Ｖ、Ｉｏｎ／Ｉｏｆｆは１０７であった。The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −60 V, the gate voltage was scanned from 20 V to −60 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of this device was 3.1 cm 2 / Vs, the threshold voltage was −7 V, and Ion / Ioff was 10 7 .
実施例８ 化合物（５）（ＤＰｈ−ＮＤＴ）と化合物（２３）（ＤＰｈ−ＢＴＢＴ）の積層型電界効果トランジスタの作製
化合物（６）の代わりに化合物（５）を用いること以外は、実施例７と同様の方法により、電界効果トランジスタを得た。Example 8 Production of Stacked Field Effect Transistor of Compound (5) (DPh-NDT) and Compound (23) (DPh-BTBT) Example 7 except that compound (5) was used instead of compound (6) A field effect transistor was obtained by the same method.
得られた電界効果トランジスタを実施例７と同様に半導体特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は１．５ｃｍ２／Ｖｓであり、閾値電圧は−２１Ｖ、Ｉｏｎ／Ｉｏｆｆは１０８であった。Semiconductor characteristics of the obtained field effect transistor were measured in the same manner as in Example 7. From the obtained voltage-current curve, the carrier mobility of this device was 1.5 cm 2 / Vs, the threshold voltage was −21 V, and Ion / Ioff was 10 8 .
比較例１ 化合物（２３）（ＤＰｈ−ＢＴＢＴ）の単層型電界効果トランジスタの作製
オクチルトリクロロシラン処理を行った２００ｎｍのＳｉＯ２熱酸化膜付きｎドープシリコンウェハー（面抵抗０．０２Ω・ｃｍ以下）を真空蒸着装置内に設置し、装置内の真空度が５．０×１０−３Ｐａ以下になるまで排気した。抵抗加熱蒸着法によって、この電極に基板温度約２５℃の条件下、化合物Ｎｏ．２３を１〜２Å／ｓｅｃの蒸着速度で５０ｎｍの厚さに蒸着し、半導体層（２）を形成した。次いでこの基板に電極作成用シャドウマスクを取り付け、真空蒸着装置内に設置し、装置内の真空度が１．０×１０−４Ｐａ以下になるまで排気し、抵抗加熱蒸着法によって、金の電極、すなわちソース電極（１）及びドレイン電極（３）を４０ｎｍの厚さに蒸着し、ＴＣ（トップコンタクト）型である本発明の電界効果トランジスタ（チャネル長５０μｍ、チャネル幅１．５ｍｍ）を得た。Comparative Example 1 Preparation of Compound (23) (DPh-BTBT) Single Layer Field Effect Transistor 200 nm SiO 2 thermally oxidized n-doped silicon wafer subjected to octyltrichlorosilane treatment (surface resistance 0.02 Ω · cm or less) Was placed in a vacuum deposition apparatus and evacuated until the degree of vacuum in the apparatus was 5.0 × 10 −3 Pa or less. By resistance heating vapor deposition, this electrode was subjected to compound no. 23 was deposited to a thickness of 50 nm at a deposition rate of 1 to 2 liters / sec to form a semiconductor layer (2). Next, a shadow mask for electrode preparation is attached to this substrate, and it is placed in a vacuum vapor deposition apparatus. The vacuum in the apparatus is evacuated to 1.0 × 10 −4 Pa or less, and a gold electrode is formed by resistance heating vapor deposition. That is, the source electrode (1) and the drain electrode (3) were deposited to a thickness of 40 nm to obtain a TC (top contact) type field effect transistor (
得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−６０Ｖとし、ゲート電圧を２０Ｖから−６０Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は０．８ｃｍ２／Ｖｓであり、閾値電圧は−２４Ｖ、Ｉｏｎ／Ｉｏｆｆは１０８であった。The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −60 V, the gate voltage was scanned from 20 V to −60 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of this device was 0.8 cm 2 / Vs, the threshold voltage was −24 V, and Ion / Ioff was 10 8 .
実施例７、実施例８及び比較例１の電圧電流曲線（図４）から明らかなように、本発明の電界効果型トランジスタは移動度が早く、閾値電圧が低く、またヒステリシスの殆ど見られないトランジスタ特性を示した。
実施例９
電界効果トランジスタのチャネル長Ｌ（２０、４０μｍ）を変化させる事以外は実施例７、実施例８及び比較例１と同様な操作で電界効果トランジスタを作製し、移動度を測定した。結果を表１に示す。
Example 9
A field effect transistor was produced in the same manner as in Example 7, Example 8, and Comparative Example 1 except that the channel length L (20, 40 μm) of the field effect transistor was changed, and the mobility was measured. The results are shown in Table 1.
実施例１０ 化合物（６）（ｐ−ｔｏｌｙｌＮＤＴ）と化合物（２０）（Ｃ８−ＢＴＢＴ）の積層型電界効果トランジスタの作製
ＨＭＤＳ処理を行った３００ｎｍのＳｉＯ２熱酸化膜付きｎドープシリコンウェハー（面抵抗０．０２Ω・ｃｍ以下）を真空蒸着装置内に設置し、装置内の真空度が１．０×１０−３Ｐａ以下になるまで排気した。抵抗加熱蒸着法によって、この電極に基板温度約２５℃の条件下、化合物（２０）を１Å／ｓｅｃの蒸着速度で５０ｎｍの厚さに蒸着し、次いで化合物（６）を１〜２Å／ｓｅｃの蒸着速度で５ｎｍの厚さに蒸着し半導体層（２）を形成した。次いでこの基板に電極作成用シャドウマスクを取り付け、真空蒸着装置内に設置し、装置内の真空度が５．０×１０−４Ｐａ以下になるまで排気し、抵抗加熱蒸着法によって、金の電極、すなわちソース電極（１）及びドレイン電極（３）、を５０ｎｍの厚さに蒸着し、ＴＣ（トップコンタクト）型である本発明の電界効果トランジスタ（チャネル長２００μｍ、チャネル幅２．５ｍｍ）を得た。Example 10 Production of Stacked Field Effect Transistor of Compound (6) (p-tolyl NDT) and Compound (20) (C8-BTBT) n-doped silicon wafer with 300 nm SiO 2 thermal oxide film subjected to HMDS treatment (surface resistance) 0.02 Ω · cm or less) was placed in a vacuum deposition apparatus, and evacuated until the degree of vacuum in the apparatus became 1.0 × 10 −3 Pa or less. The compound (20) was vapor-deposited to a thickness of 50 nm at a deposition rate of 1 ｓｅｃ / sec on this electrode at a substrate temperature of about 25 ° C. by resistance heating vapor deposition, and then the compound (6) was deposited at 1 to 2 Å / sec. A semiconductor layer (2) was formed by vapor deposition to a thickness of 5 nm at a vapor deposition rate. Next, a shadow mask for electrode preparation is attached to this substrate, and it is placed in a vacuum vapor deposition apparatus, evacuated until the degree of vacuum in the apparatus becomes 5.0 × 10 −4 Pa or less, and gold electrode is formed by resistance heating vapor deposition. That is, the source electrode (1) and the drain electrode (3) are deposited to a thickness of 50 nm to obtain a field effect transistor (channel length 200 μm, channel width 2.5 mm) of the present invention which is a TC (top contact) type. It was.
得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−１００Ｖとし、ゲート電圧を２０Ｖから−１００Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は１０．５ｃｍ２／Ｖｓであり、閾値電圧は−４３Ｖ、Ｉｏｎ／Ｉｏｆｆは４×１０８であった。The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −100 V, the gate voltage was scanned from 20 V to −100 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of this device was 10.5 cm 2 / Vs, the threshold voltage was −43 V, and Ion / Ioff was 4 × 10 8 .
比較例２ 化合物（２０）（Ｃ８−ＢＴＢＴ）の単層型電界効果トランジスタの作製
化合物（６）の薄膜を形成しなかったこと以外は、実施例１０と同様な方法で電界効果トランジスタを得た。Comparative Example 2 Fabrication of Compound (20) (C8-BTBT) Single Layer Field Effect Transistor A field effect transistor was obtained in the same manner as in Example 10 except that the compound (6) thin film was not formed. .
得られた電界効果トランジスタをプローバー内に設置し半導体パラメーターアナライザー４２００ＳＣＳ（ケースレー社製）を用いて半導体特性を測定した。半導体特性はドレイン電圧を−１００Ｖとし、ゲート電圧を２０Ｖから−１００Ｖまでで走査し、ドレイン電流−ゲート電圧（トランスファー）特性を測定した。得られた電圧電流曲線より、本素子のキャリア移動度は６．０ｃｍ２／Ｖｓであり、閾値電圧は−３６Ｖ、Ｉｏｎ／Ｉｏｆｆは２×１０８であった。The obtained field effect transistor was installed in a prober, and the semiconductor characteristics were measured using a semiconductor parameter analyzer 4200SCS (manufactured by Keithley). The semiconductor characteristics were such that the drain voltage was −100 V, the gate voltage was scanned from 20 V to −100 V, and the drain current-gate voltage (transfer) characteristics were measured. From the obtained voltage-current curve, the carrier mobility of this device was 6.0 cm 2 / Vs, the threshold voltage was −36 V, and Ion / Ioff was 2 × 10 8 .
以上の結果より分かるように、比較例１ではチャネル長が短くなった場合には移動度が低くなっているが、本発明のトランジスタではそのような傾向は見られず、チャネル長が短くなっても移動度は低下しなかった。また、本発明のトランジスタは短いチャネル長での高移動度動作が可能である為、大きな電流を流すことが可能となり、かつ高密度集積に適していることがわかった。また本発明の電界効果トランジスタは短チャネル長の電圧電流曲線より、ヒステリシスが少なく、良好な特性を有していることが分かった。上記の結果より明らかなように、本発明の化合物を積層した電界効果トランジスタは、明らかに移動度の高い、良好な半導体特性を示していることが分かった。 As can be seen from the above results, in Comparative Example 1, the mobility is low when the channel length is short, but such a tendency is not seen in the transistor of the present invention, and the channel length is short. However, the mobility did not decrease. Further, it was found that the transistor of the present invention can operate with high mobility with a short channel length, so that a large current can flow and is suitable for high-density integration. It was also found that the field effect transistor of the present invention has good characteristics with less hysteresis than the short channel length voltage-current curve. As is clear from the above results, it was found that the field effect transistor in which the compound of the present invention was laminated exhibited a good semiconductor characteristic with a clearly high mobility.
Claims (5)
（Ｘ２は置換基を有してもよい脂肪族炭化水素残基又は置換基を有してもよい芳香族残基を表す。） An electric field having a structure in which a layer containing the organic semiconductor material (A) represented by the general formula (2) and a layer containing the organic semiconductor material (B) represented by the general formula (3) are laminated. effect transistor data.
(X 2 represents an aliphatic hydrocarbon residue that may have a substituent or an aromatic residue that may have a substituent.)
（Ｒ２は水素原子又は置換基を有してもよい脂肪族炭化水素残基を表す。） An organic semiconductor material represented by the general formula (3) is the general formula (4), the field effect transistor of claim 1.
(R 2 represents a hydrogen atom or an aliphatic hydrocarbon residue which may have a substituent.)
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