JP2010232413A - Vertical organic semiconductor device - Google Patents
Vertical organic semiconductor device Download PDFInfo
- Publication number
- JP2010232413A JP2010232413A JP2009078144A JP2009078144A JP2010232413A JP 2010232413 A JP2010232413 A JP 2010232413A JP 2009078144 A JP2009078144 A JP 2009078144A JP 2009078144 A JP2009078144 A JP 2009078144A JP 2010232413 A JP2010232413 A JP 2010232413A
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- JP
- Japan
- Prior art keywords
- fine particles
- organic semiconductor
- substrate
- semiconductor device
- thin film
- Prior art date
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- PZOUSPYUWWUPPK-UHFFFAOYSA-N indole Natural products CC1=CC=CC2=C1C=CN2 PZOUSPYUWWUPPK-UHFFFAOYSA-N 0.000 description 1
- RKJUIXBNRJVNHR-UHFFFAOYSA-N indolenine Natural products C1=CC=C2CC=NC2=C1 RKJUIXBNRJVNHR-UHFFFAOYSA-N 0.000 description 1
- 125000004926 indolenyl group Chemical group 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000008040 ionic compounds Chemical class 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 125000002462 isocyano group Chemical group *[N+]#[C-] 0.000 description 1
- 125000005956 isoquinolyl group Chemical group 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000005499 meniscus Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- PQIOSYKVBBWRRI-UHFFFAOYSA-N methylphosphonyl difluoride Chemical group CP(F)(F)=O PQIOSYKVBBWRRI-UHFFFAOYSA-N 0.000 description 1
- 238000000813 microcontact printing Methods 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- LKKPNUDVOYAOBB-UHFFFAOYSA-N naphthalocyanine Chemical class N1C(N=C2C3=CC4=CC=CC=C4C=C3C(N=C3C4=CC5=CC=CC=C5C=C4C(=N4)N3)=N2)=C(C=C2C(C=CC=C2)=C2)C2=C1N=C1C2=CC3=CC=CC=C3C=C2C4=N1 LKKPNUDVOYAOBB-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000000449 nitro group Chemical group [O-][N+](*)=O 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- AZQWKYJCGOJGHM-UHFFFAOYSA-N para-benzoquinone Natural products O=C1C=CC(=O)C=C1 AZQWKYJCGOJGHM-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000002964 pentacenes Chemical class 0.000 description 1
- FVDOBFPYBSDRKH-UHFFFAOYSA-N perylene-3,4,9,10-tetracarboxylic acid Chemical compound C=12C3=CC=C(C(O)=O)C2=C(C(O)=O)C=CC=1C1=CC=C(C(O)=O)C2=C1C3=CC=C2C(=O)O FVDOBFPYBSDRKH-UHFFFAOYSA-N 0.000 description 1
- 125000005561 phenanthryl group Chemical group 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920005593 poly(benzyl methacrylate) Polymers 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000553 poly(phenylenevinylene) Polymers 0.000 description 1
- 229920000548 poly(silane) polymer Polymers 0.000 description 1
- 229920001467 poly(styrenesulfonates) Polymers 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920001197 polyacetylene Polymers 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920006289 polycarbonate film Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002689 polyvinyl acetate Polymers 0.000 description 1
- 239000011118 polyvinyl acetate Substances 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- MWWATHDPGQKSAR-UHFFFAOYSA-N propyne Chemical group CC#C MWWATHDPGQKSAR-UHFFFAOYSA-N 0.000 description 1
- 125000004309 pyranyl group Chemical group O1C(C=CC=C1)* 0.000 description 1
- DNXIASIHZYFFRO-UHFFFAOYSA-N pyrazoline Chemical compound C1CN=NC1 DNXIASIHZYFFRO-UHFFFAOYSA-N 0.000 description 1
- 125000005412 pyrazyl group Chemical group 0.000 description 1
- 125000001725 pyrenyl group Chemical group 0.000 description 1
- 125000005494 pyridonyl group Chemical group 0.000 description 1
- 125000000714 pyrimidinyl group Chemical group 0.000 description 1
- 125000000168 pyrrolyl group Chemical group 0.000 description 1
- 125000005493 quinolyl group Chemical group 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000005060 rubber Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 150000005082 selenophenes Chemical class 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 150000003384 small molecules Chemical class 0.000 description 1
- PJANXHGTPQOBST-UHFFFAOYSA-N stilbene Chemical class C=1C=CC=CC=1C=CC1=CC=CC=C1 PJANXHGTPQOBST-UHFFFAOYSA-N 0.000 description 1
- 235000021286 stilbenes Nutrition 0.000 description 1
- 125000000542 sulfonic acid group Chemical group 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- VJYJJHQEVLEOFL-UHFFFAOYSA-N thieno[3,2-b]thiophene Chemical class S1C=CC2=C1C=CS2 VJYJJHQEVLEOFL-UHFFFAOYSA-N 0.000 description 1
- CRUIOQJBPNKOJG-UHFFFAOYSA-N thieno[3,2-e][1]benzothiole Chemical class C1=C2SC=CC2=C2C=CSC2=C1 CRUIOQJBPNKOJG-UHFFFAOYSA-N 0.000 description 1
- 150000003568 thioethers Chemical class 0.000 description 1
- 125000003396 thiol group Chemical group [H]S* 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 125000005208 trialkylammonium group Chemical group 0.000 description 1
- 150000003852 triazoles Chemical class 0.000 description 1
- 125000006617 triphenylamine group Chemical class 0.000 description 1
- 150000004961 triphenylmethanes Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000002061 vacuum sublimation Methods 0.000 description 1
- 229910001935 vanadium oxide Inorganic materials 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
Abstract
Description
本発明は、縦型有機半導体デバイスに関する。更に詳しくは、本発明は特定の有機化合物により形成される半導体層を有することを特徴とする縦型有機半導体デバイスに関する。 The present invention relates to a vertical organic semiconductor device. More specifically, the present invention relates to a vertical organic semiconductor device having a semiconductor layer formed of a specific organic compound.
近年、有機半導体デバイスとして有機ＥＬ素子が実用化され、有機トランジスタ、有機太陽電池などの新規デバイスの研究開発が盛んに行われている。軽量でフレキシブルという特徴を有し、印刷法や低温プロセスが可能であり、これまでのシリコンにない特徴を有している。
しかし、有機半導体は無機半導体に比べキャリア移動度が低いために、オン抵抗が高いという問題点があり、低動作電圧で高出力電流を得ることが困難であった。この問題点を解決する方法として、有機トランジスタでは静電誘導型トランジスタ(ＳＩＴ)などの縦型構造素子が提案されている。ＳＩＴは、キャリアが広い断面積にわたって短い距離を走行することから、オン抵抗や動作電圧の低減が期待されている（特許文献１）。コロイダルリソグラフィー法を用いた有機ＳＩＴは、安価で簡便に製造する事が可能であり、動作電圧、周波数特性に優れ、スイッチング特性を有する上に、銅フタロシアニン(CuPc)やペンタセンを、半導体材料として用いることで優れた特性を得られることが報告されている（特許文献２、３）。しかし、これらの材料は大気雰囲気においてアクセプタが生じ、雰囲気によって素子特性が大きく変化してしまうという問題点を有していた。よって、安定動作のためには大気雰囲気下で安定な材料を探索する必要があった。
この材料として、大気雰囲気下で安定で、イオン化ポテンシャル(ＩＰ)が大きく、比較的高いキャリア移動度を示すことが知られているジフェニルベンゾチエノベンゾチオフェン(DPh-BTBT)の使用が検討されている（非特許文献１，２，３）。
この材料を使用することで高い大気雰囲気安定性及び高ＯＮ／ＯＦＦ比が得られているが、その一方でＣｕＰｃやペンタセンを用いた有機ＳＩＴと比較してＯＮ電流密度が１桁程度低く、更なる改良が求められている。
In recent years, organic EL elements have been put into practical use as organic semiconductor devices, and research and development of new devices such as organic transistors and organic solar cells have been actively conducted. It has the characteristics of being lightweight and flexible, and can be used for printing and low-temperature processes, and has characteristics not found in conventional silicon.
However, since the organic semiconductor has a lower carrier mobility than the inorganic semiconductor, there is a problem that the on-resistance is high, and it is difficult to obtain a high output current at a low operating voltage. As a method for solving this problem, a vertical structure element such as a static induction transistor (SIT) has been proposed as an organic transistor. SIT is expected to reduce on-resistance and operating voltage because the carrier travels a short distance over a wide cross-sectional area (Patent Document 1). Organic SIT using colloidal lithography can be easily manufactured at low cost, has excellent operating voltage and frequency characteristics, has switching characteristics, and uses copper phthalocyanine (CuPc) or pentacene as a semiconductor material. It has been reported that excellent characteristics can be obtained (Patent Documents 2 and 3). However, these materials have a problem in that acceptors are generated in an air atmosphere, and device characteristics greatly change depending on the atmosphere. Therefore, for stable operation, it is necessary to search for a material that is stable in an air atmosphere.
As this material, the use of diphenylbenzothienobenzothiophene (DPh-BTBT), which is known to be stable in the air atmosphere, has a large ionization potential (IP), and exhibits relatively high carrier mobility, is being studied. (Non-patent documents 1, 2, 3).
The use of this material provides high atmospheric stability and a high ON / OFF ratio. On the other hand, the ON current density is about an order of magnitude lower than that of organic SIT using CuPc or pentacene. There is a need for improvements.
本発明は優れた特性を有する縦型有機半導体デバイスを得ることを、詳しくは雰囲気安定性、高ＯＮ／ＯＦＦ比、高電流密度を兼ね備えた実用的な縦型有機半導体デバイス、更に詳しくは静電誘導型トランジスタを提供することを目的とする。 The present invention provides a vertical organic semiconductor device having excellent characteristics, more specifically, a practical vertical organic semiconductor device having atmospheric stability, a high ON / OFF ratio, and a high current density, and more specifically, an electrostatic An object is to provide an inductive transistor.
本発明者等は、上記課題を解決すべく鋭意検討の結果、特定の構造をもつジフェニルベンゾチエノベンゾチオフェン(DPh-BTBT)誘導体が、上記の点で従来の有機半導体材料と比較して優れた特性を有することと、更に特定の構造を有するアクセプタ型有機材料を組み合わせて用いることにより、半導体特性が非常に向上した縦型有機半導体デバイスが得られ、更に素子作成時または作成後に熱処理を行うことでその効果が顕著に上がることを見出し、本発明を完成させるに至った。 As a result of diligent studies to solve the above problems, the present inventors have found that a diphenylbenzothienobenzothiophene (DPh-BTBT) derivative having a specific structure is superior to conventional organic semiconductor materials in the above points. A vertical organic semiconductor device with greatly improved semiconductor characteristics can be obtained by combining the use of an acceptor-type organic material having a specific structure and a specific structure, and heat treatment is performed at the time of element creation or after creation. As a result, the inventors have found that the effect is remarkably improved, and have completed the present invention.
即ち、本発明は、その一つの態様において、
（１）一般式（１）で表される化合物を半導体材料として含む、縦型有機半導体デバイス。
（Ｒ１及びＲ２はそれぞれ独立に置換基を有してもよい芳香族基を表す。）
（２）Ｒ１及びＲ２がそれぞれ独立に置換基を有してもよいフェニル基である、（１）に記載の縦型有機半導体デバイス。
（３）前記デバイスが薄膜トランジスタである、（１）又は（２）に記載の縦型有機半導体デバイス。
（４）前記薄膜トランジスタが静電誘導型トランジスタである、（３）に記載の縦型有機半導体デバイス。
（５）前記デバイスが太陽電池である、（１）又は（２）に記載の縦型有機半導体デバイス。
（６）半導体材料として、一般式（１）で表される化合物及びアクセプタ型有機半導体材料の組み合わせを含む、（１）乃至（５）に記載の縦型有機半導体デバイス。
（７）前記アクセプタ型有機半導体材料が、テトラシアノキノジメタン誘導体、フタロシアニン誘導体又はフラーレン誘導体のいずれか一つを含有する、（６）に記載の縦型有機半導体デバイス、
に関する。
That is, the present invention, in one embodiment thereof,
(1) A vertical organic semiconductor device comprising a compound represented by the general formula (1) as a semiconductor material.
(R 1 and R 2 each independently represents an aromatic group which may have a substituent.)
(2) The vertical organic semiconductor device according to (1), wherein R 1 and R 2 are each independently a phenyl group which may have a substituent.
(3) The vertical organic semiconductor device according to (1) or (2), wherein the device is a thin film transistor.
(4) The vertical organic semiconductor device according to (3), wherein the thin film transistor is an electrostatic induction transistor.
(5) The vertical organic semiconductor device according to (1) or (2), wherein the device is a solar cell.
(6) The vertical organic semiconductor device according to (1) to (5), which includes a combination of a compound represented by the general formula (1) and an acceptor organic semiconductor material as a semiconductor material.
(7) The vertical organic semiconductor device according to (6), wherein the acceptor-type organic semiconductor material contains any one of a tetracyanoquinodimethane derivative, a phthalocyanine derivative, or a fullerene derivative,
About.
特定の構造をもつジフェニルベンゾチエノベンゾチオフェン(DPh-BTBT)誘導体が、上記の点で従来の有機半導体材料と比較して優れた特性を有することを見出し、更に特定の構造を有するアクセプタ型有機材料を組み合わせて用いることにより、雰囲気安定性、高ＯＮ／ＯＦＦ比、高電流密度を兼ね備えた実用的な縦型有機半導体デバイス、更に詳しくは静電誘導型トランジスタを提供できる。 We have found that diphenylbenzothienobenzothiophene (DPh-BTBT) derivatives with a specific structure have superior characteristics compared to conventional organic semiconductor materials in the above points, and also acceptor-type organic materials with a specific structure By using these in combination, it is possible to provide a practical vertical organic semiconductor device that combines atmospheric stability, a high ON / OFF ratio, and a high current density, and more specifically, an electrostatic induction transistor.
本発明を詳細に説明する。
本発明は特定の有機化合物を半導体材料として用いた縦型有機半導体デバイスに関し、半導体材料として前記式（１）で表される化合物を使用し、半導体層を形成したものである。そこでまず上記式（１）の化合物について説明する。
The present invention will be described in detail.
The present invention relates to a vertical organic semiconductor device using a specific organic compound as a semiconductor material, wherein a semiconductor layer is formed using the compound represented by the formula (1) as a semiconductor material. Therefore, first, the compound of the above formula (1) will be described.
式（１）中、Ｒ１及びＲ２はそれぞれ独立に置換基を有してもよい芳香族炭基を表す。置換基を有しても良い芳香族基の具体例としては、フェニル基、ナフチル基、アンスリル基、フェナンスリル基、ピレニル基、ベンゾピレニル基などの芳香族炭化水素基やピリジル基、ピラジル基、ピリミジル基、キノリル基、イソキノリル基、ピロリル基、インドレニル基、イミダゾリル基、カルバゾリル基、チエニル基、フリル基、ピラニル基、ピリドニル基などの複素環基、ベンゾキノリル基、アントラキノリル基、ベンゾチエニル基のような縮合系複素環基が挙げられる。これらのうち、好ましいものはフェニル基、ナフチル基、ピリジル基及びチエニル基である。 In formula (1), R 1 and R 2 each independently represent an aromatic carbon group that may have a substituent. Specific examples of the aromatic group that may have a substituent include aromatic hydrocarbon groups such as phenyl group, naphthyl group, anthryl group, phenanthryl group, pyrenyl group, and benzopyrenyl group, pyridyl group, pyrazyl group, and pyrimidyl group. , Quinolyl group, isoquinolyl group, pyrrolyl group, indolenyl group, imidazolyl group, carbazolyl group, thienyl group, furyl group, pyranyl group, pyridonyl group and other heterocyclic groups, benzoquinolyl group, anthraquinolyl group, benzothienyl group A heterocyclic group is mentioned. Of these, preferred are a phenyl group, a naphthyl group, a pyridyl group, and a thienyl group.
また、置換基の具体例としては、特に制限はないが、アルキル基、芳香族基、フッ素原子、塩素原子、臭素原子、ヨウ素原子等のハロゲン原子、ヒドロキシル基、メルカプト基、ニトロ基、アルコキシル基、アルキル置換アミノ基、アリール置換アミノ基、非置換アミノ基、アリール基、アシル基、アルコキシカルボニル基、シアノ基、イソシアノ基、アシルオキシ基等が挙げられる。このなかでもアルキル基、芳香族基、ハロゲン原子、アルコキシル基が好ましい。 Specific examples of the substituent are not particularly limited, but include halogen groups such as alkyl groups, aromatic groups, fluorine atoms, chlorine atoms, bromine atoms, iodine atoms, hydroxyl groups, mercapto groups, nitro groups, alkoxyl groups. Alkyl-substituted amino group, aryl-substituted amino group, unsubstituted amino group, aryl group, acyl group, alkoxycarbonyl group, cyano group, isocyano group, acyloxy group and the like. Among these, an alkyl group, an aromatic group, a halogen atom, and an alkoxyl group are preferable.
式（１）で表される化合物は、特許文献４、５及び非特許文献４に開示された公知の方法などにより合成することができる。例えば以下のスキーム１に記された方法が挙げられる。原料としてニトロスチルベン誘導体（Ａ）を用いて、ベンゾチエノベンゾチオフェン骨格（Ｄ）を形成し、引き続きアミノ化物（Ｅ）、ハロゲン化物（Ｆ）を経た後、ホウ酸誘導体とカップリングをして所望の化合物を得ることが可能である。特許文献５の方法によれば、対応するベンズアルデヒド誘導体より１ステップで製造できるため、より効果的である。 The compound represented by the formula (1) can be synthesized by a known method disclosed in Patent Documents 4 and 5 and Non-Patent Document 4. For example, the method described in the following scheme 1 can be mentioned. Using nitrostilbene derivative (A) as a raw material, benzothienobenzothiophene skeleton (D) is formed, followed by amination (E) and halide (F), and then coupling with boric acid derivative as desired It is possible to obtain a compound of According to the method of Patent Document 5, since it can be produced in one step from the corresponding benzaldehyde derivative, it is more effective.
上記式（１）で表される化合物の精製方法は、特に限定されず、再結晶、カラムグロマトグラフィー、及び真空昇華精製等の公知の方法が採用できる。また必要に応じてこれらの方法を組み合わせることができる。 The purification method of the compound represented by the above formula (1) is not particularly limited, and known methods such as recrystallization, column chromatography, and vacuum sublimation purification can be employed. These methods can be combined as necessary.
下記に上記式（１）で示される化合物の具体例を示す。 Specific examples of the compound represented by the above formula (1) are shown below.
本発明の縦型有機半導体デバイスとして、具体的には有機薄膜トランジスタ（図１−Ｃ）、有機太陽電池（図１-Ａ）、有機ＥＬ（図１-Ｂ）、有機レーザーなどが挙げられる。それぞれ縦位置に電極が存在するため電荷の移動する距離が比較的短く、さらに電極自体を広い断面積にすることが容易で電荷移動度が比較的低い有機半導体材料には適した構造と言える。有機薄膜トランジスタはその作製プロセスの容易さから横型構造を有したものが一般的であるが、有機半導体材料の電荷移動度が低いことや電極間の距離を短くするのが困難なことから、動作速度の向上が低く、オン抵抗が高くなることなどの問題が残っており、縦型構造トランジスタが検討されている。この縦型構造トランジスタとして静電誘導型トランジスタが挙げられる。 Specific examples of the vertical organic semiconductor device of the present invention include an organic thin film transistor (FIG. 1-C), an organic solar cell (FIG. 1-A), an organic EL (FIG. 1-B), and an organic laser. It can be said that the structure is suitable for an organic semiconductor material in which the distance in which charges move is relatively short due to the presence of electrodes in the vertical positions, and the electrodes themselves can easily have a wide cross-sectional area and the charge mobility is relatively low. Organic thin-film transistors generally have a horizontal structure because of their ease of manufacturing process, but the operating speed is low due to the low charge mobility of organic semiconductor materials and the difficulty in shortening the distance between electrodes. However, there is still a problem that the on-resistance is low and the on-resistance is high, and vertical structure transistors are being studied. An example of the vertical structure transistor is an electrostatic induction transistor.
図２に本発明の縦型有機トランジスタの一例である有機静電誘導型トランジスタ（ＳＩＴ）の代表的な素子構造を詳細に説明するが、本発明はこれらの構造には限定されるものではない。ＳＩＴはソース電極（Ｓ）とドレイン電極（Ｄ）とからなる電極対を備え、電極間にこれら電極対と接触することなくゲート電極（Ｇ）が形成されている。ドレイン電極（Ｄ）とゲート電極（Ｇ）は電極面の実質的に同じ位置に貫通孔を有し、これらの貫通孔は共通の貫通孔を形成している。実質的に同じ位置とはスイッチング素子をソース電極側又は基板側から垂直に透視したときに貫通孔又は孔が同一の軸線上に重なって見える位置を意味する。ソース電極（Ｓ）は貫通孔の位置でゲート電極（Ｇ）に向かって突起する突起状構造を有する。ゲート電極（Ｇ）及びドレイン電極（Ｄ）に設けられた貫通孔には活性層（Ａ）として有機半導体材料が充填されている。対向するゲート電極（Ｇ）とドレイン電極間には絶縁層（ＧＩ）が設けられ、絶縁材料が充填されている。しかしこの絶縁層（ＧＩ）は絶縁材料であることが好ましいが、必ずしも絶縁性を有する必要はなく、有機半導体材料を充填してゲート電極とショットキー接合されていても良い。 FIG. 2 illustrates in detail a typical element structure of an organic static induction transistor (SIT) which is an example of the vertical organic transistor of the present invention, but the present invention is not limited to these structures. . The SIT includes an electrode pair composed of a source electrode (S) and a drain electrode (D), and a gate electrode (G) is formed between the electrodes without contacting the electrode pair. The drain electrode (D) and the gate electrode (G) have a through hole at substantially the same position on the electrode surface, and these through holes form a common through hole. Substantially the same position means a position where the through holes or holes appear to overlap on the same axis when the switching element is viewed vertically from the source electrode side or the substrate side. The source electrode (S) has a protruding structure protruding toward the gate electrode (G) at the position of the through hole. The through holes provided in the gate electrode (G) and the drain electrode (D) are filled with an organic semiconductor material as an active layer (A). An insulating layer (GI) is provided between the opposing gate electrode (G) and drain electrode, and is filled with an insulating material. However, this insulating layer (GI) is preferably an insulating material, but it does not necessarily have insulating properties, and may be filled with an organic semiconductor material and Schottky bonded to the gate electrode.
活性層
活性層（Ａ）は有機半導体材料であるホール輸送性物質又は電子輸送性物質により構成される。
本発明の縦型静電誘導型トランジスタでは半導体材料として、一般式（１）で表される化合物が用いられることが特徴である。該化合物は混合物であってもよいが、活性層（Ａ）中には式（１）で表される化合物を通常５０重量％以上、好ましくは８０重量％以上、更に好ましくは９５重量％以上含むことが好ましい。一般的に本発明の一般式（１）の化合物はホール輸送型のＰ型半導体として用いられる。
電界効果トランジスタの特性を改善したり他の特性を付与するために、必要に応じて他の有機半導体材料や各種添加剤を混合することができる。具体的にはＰ型又はＮ型の有機半導体材料としては低分子化合物及び高分子化合物が使用可能である。
Active Layer The active layer (A) is composed of a hole transporting substance or an electron transporting substance that is an organic semiconductor material.
The vertical electrostatic induction transistor of the present invention is characterized in that a compound represented by the general formula (1) is used as a semiconductor material. The compound may be a mixture, but the active layer (A) usually contains 50% by weight or more, preferably 80% by weight or more, more preferably 95% by weight or more of the compound represented by the formula (1). It is preferable. Generally, the compound of the general formula (1) of the present invention is used as a hole transport type P-type semiconductor.
In order to improve the characteristics of the field effect transistor or to impart other characteristics, other organic semiconductor materials and various additives can be mixed as necessary. Specifically, a low molecular compound and a high molecular compound can be used as the P-type or N-type organic semiconductor material.
上記低分子化合物としてはフタロシアニン系誘導体、ナフタロシアニン系誘導体、アゾ化合物系誘導体、ペリレン系誘導体、インジゴ系誘導体、キナクリドン系誘導体、アントラキノン類等の多環キノン系誘導体、シアニン系誘導体、フラーレン類誘導体、インドール、カルバゾール、オキサゾール、インオキサゾール、チアゾール、イミダゾール、ピラゾール、オキサアジアゾール、ピラゾリン、チアチアゾール、トリアゾール等の含窒素環式化合物誘導体、ヒドラジン誘導体、トリフェニルアミン誘導体、トリフェニルメタン誘導体、スチルベン類、アントラキノン、ジフェノキノン等のキノン化合物誘導体、アントラセン、ベンタセン、ピレン、フェナントレン、コロネン等の多環芳香族化合物誘導体、ベンゾチエノベンゾチオフェン誘導体、ベンゾセレノベンゾセレノフェン誘導体、ベンゾジチオフェン誘導体、ベンゾジセレノフェン誘導体、ジナフトチエノチオフェン誘導体、ジナフトセレノセレノフェン誘導体などのカルコゲノ含有多環化合物誘導体等が挙げられる。 Examples of the low molecular weight compounds include phthalocyanine derivatives, naphthalocyanine derivatives, azo compound derivatives, perylene derivatives, indigo derivatives, quinacridone derivatives, polycyclic quinone derivatives such as anthraquinones, cyanine derivatives, fullerene derivatives, Nitrogen-containing cyclic compound derivatives such as indole, carbazole, oxazole, inoxazole, thiazole, imidazole, pyrazole, oxaadiazole, pyrazoline, thiathiazole, triazole, hydrazine derivative, triphenylamine derivative, triphenylmethane derivative, stilbene, Quinone compound derivatives such as anthraquinone and diphenoquinone, polycyclic aromatic compound derivatives such as anthracene, bentacene, pyrene, phenanthrene and coronene, benzothienobenzothiophene Conductor, benzo seleno benzoselenophene derivatives, benzodithiophene derivatives, benzodioxanyl selenophene derivatives, Gina shift thienothiophene derivatives, Karukogeno containing polycyclic compound derivatives such as Gina shift seleno selenophene derivatives.
上記高分子化合物としては、上記の低分子化合物がポリエチレン鎖、ポリシロキサン鎖、ポリエーテル鎖、ポリエステル鎖、ポリアミド鎖、ポリイミド鎖等の通常の電気的に不活性な高分子鎖の主鎖中に結合したもの、又は側鎖としてペンダント状に結合したものを用いることができる。
上記高分子化合物として共役性高分子化合物を用いることも好ましい。共役性高分子化合物の好ましい例としては、ポリパラフエニレン等の芳香族系共役性高分子化合物、ポリアセチレン等の脂肪族系共役性高分子化合物、ポリピロール、ポリチオフェン等の複素環式共役性高分子化合物、ポリアニリン類、ポリフェニレンサルファイド等のへテロ原子含有共役性高分子化合物、ポリ（フェニレンビニレン）、ポリ（アリーレンビニレン）、ポリ（チエニレンビニレン）等の上記共役性高分子化合物の構成単位が交互に結合した構造を有する複合型共役系高分子化合物等の炭素系共役性高分子化合物が挙げられる。さらに、ポリシラン類、ジシラニレンアリレンポリマー類、（ジシラニレン）エテニレンポリマー類、（ジシラニレン）エチニレンポリマー類等のジシラニレン−炭素系共役性ポリマー構造等のオリゴシラン類と炭素系共役性構造が交互に連鎖した高分子化合物等を用いるのも好ましい。
As the polymer compound, the low-molecular compound is contained in a main chain of a normal electrically inactive polymer chain such as a polyethylene chain, a polysiloxane chain, a polyether chain, a polyester chain, a polyamide chain, and a polyimide chain. What was couple | bonded or what was couple | bonded in the pendant shape as a side chain can be used.
It is also preferable to use a conjugated polymer compound as the polymer compound. Preferred examples of the conjugated polymer compound include aromatic conjugated polymer compounds such as polyparaphenylene, aliphatic conjugated polymer compounds such as polyacetylene, and heterocyclic conjugated polymers such as polypyrrole and polythiophene. Constituent units of the above conjugated polymer compounds such as compounds, polyanilines, heteroatom-containing conjugated polymer compounds such as polyphenylene sulfide, poly (phenylene vinylene), poly (arylene vinylene), poly (thienylene vinylene) And carbon-based conjugated polymer compounds such as a composite conjugated polymer compound having a structure bonded to the. In addition, oligosilanes such as polysilanes, disilanylene allylene polymers, (disilanylene) ethenylene polymers, (disilanylene) ethynylene polymers, etc., and other oligosilanes and carbon-based conjugated structures are alternated. It is also preferable to use a polymer compound or the like chained to each other.
また活性層（Ａ）は複数の層から構成されていてもよい。複数ある場合の例として図３に電荷注入層（ＣＩ）をソース電極との界面に設けた構成を示す。この電荷注入層（ＣＩ）はソース電極（Ｓ）から活性層（Ａ）の電荷の注入を容易にするために設けられるものである。Ｐ型駆動のＳＩＴの大気雰囲気安定性を上げるためにＨＯＭＯの深い材料を用いると、電極からの注入障壁が大きくなる。その接触抵抗を緩和するために、電荷注入層にアクセプタ材料を使用することができる。この電荷注入層（ＣＩ）に用いる材料としては上記した低分子系及び高分子系の有機半導体材料や無機半導体材料、金属材料などが挙げられる。有機ＥＬ素子用途に開発された電荷注入用の材料及びそれらの組み合わせが好適に使用することができるが、電荷の注入障壁を減少し、安定的に本願のＳＩＴが作用できれば特に限定されるものではない。
本発明の一般式（１）で表わされる化合物は、一般的に深いＨＯＭＯを有する半導体であるため、組み合わされる電荷注入層（ＣＩ）用の材料としては電子親和力の大きい材料であることが望ましい。この材料として、一般的なアクセプタ型の材料を用いることができるが、特にアクセプタ型有機半導体材料が挙げられる。具体的にはペリレン誘導体、テトラシアノキノジメタン誘導体、フタロシアニン誘導体、フラーレン誘導体などが挙げられる。ペリレン誘導体としてはペリレンテトラカルボン酸無水物、及びそのジイミド誘導体（アルキル体やアリール体など）等；テトラシアノキノジメタン誘導体としてはテトラシアノキノジメタン、及びそのフッ素化誘導体（ジフルオロ体（Ｆ２ＴＣＮＱ）やテトラフルオロ体（Ｆ４ＴＣＮＱ）など）等；フタロシアニン誘導体としては無金属フタロシアニンのヘキサデカフルオロ誘導体（Ｆ１６Ｈ２Ｐｃ）、銅フタロシアニンのオクタフルオロ誘導体（Ｆ８ＣｕＰｃ）及びヘキサデカフルオロ誘導体（Ｆ１６ＣｕＰｃ）等；フラーレン誘導体としてはフラーレン、及びそのフッ素化誘導体（たとえばＣ６０Ｆ３６）等が挙げられる。好ましくはＦ４ＴＣＮＱ、Ｆ１６ＣｕＰｃ又はＣ６０Ｆ３６が挙げられ、さらに好ましくはＦ１６ＣｕＰｃまたはＣ６０Ｆ３６が挙げられる。
The active layer (A) may be composed of a plurality of layers. As an example in the case where there are a plurality of layers, FIG. 3 shows a configuration in which a charge injection layer (CI) is provided at the interface with the source electrode. This charge injection layer (CI) is provided to facilitate injection of charges from the source electrode (S) to the active layer (A). If a material having a deep HOMO is used in order to increase the atmospheric stability of the P-type driven SIT, an injection barrier from the electrode increases. An acceptor material can be used for the charge injection layer to reduce the contact resistance. Examples of the material used for the charge injection layer (CI) include the low molecular and high molecular organic semiconductor materials, inorganic semiconductor materials, and metal materials described above. Materials for charge injection developed for organic EL device applications and combinations thereof can be suitably used, but are not particularly limited as long as the SIT of the present application can be stably operated by reducing the charge injection barrier. Absent.
Since the compound represented by the general formula (1) of the present invention is generally a semiconductor having a deep HOMO, the material for the combined charge injection layer (CI) is preferably a material having a high electron affinity. As this material, a general acceptor type material can be used, and an acceptor type organic semiconductor material is particularly mentioned. Specific examples include perylene derivatives, tetracyanoquinodimethane derivatives, phthalocyanine derivatives, fullerene derivatives, and the like. Perylene derivatives such as perylene tetracarboxylic acid anhydrides and diimide derivatives thereof (alkyl and aryl forms); tetracyanoquinodimethane derivatives such as tetracyanoquinodimethane and fluorinated derivatives thereof (difluoro form (F2TCNQ)) And tetrafluoro derivatives (F4TCNQ) and the like; phthalocyanine derivatives include metal-free phthalocyanine hexadecafluoro derivatives (F16H2Pc), copper phthalocyanine octafluoro derivatives (F8CuPc), hexadecafluoro derivatives (F16CuPc), etc .; And fullerenes and fluorinated derivatives thereof (for example, C60F36). Preferably F4TCNQ, F16CuPc or C60F36 is mentioned, More preferably, F16CuPc or C60F36 is mentioned.
この電荷注入層は単独でも用いることが出来るが、混合することが好ましい。特に一般式（１）の化合物と混合することにより、ソース電極（Ｓ）からの電荷注入障壁を低減を図ることが可能である。混合の方法として溶液プロセスとしては最初から混合した溶液を用いることが好ましく、蒸着方法などの真空プロセスを用いる場合は共蒸着でも最初から混合しておいてもよい。 This charge injection layer can be used alone, but is preferably mixed. In particular, the charge injection barrier from the source electrode (S) can be reduced by mixing with the compound of the general formula (1). As a mixing method, a solution mixed from the beginning is preferably used as a solution process. When a vacuum process such as a vapor deposition method is used, co-deposition or mixing may be performed from the beginning.
（基板）
基板は一般的にドレイン電極（Ｄ）の下部に設けられており、本発明のデバイスを支持することができればよい。表面が平滑なものであれば材質は特に限定されず、ガラス、シリコン等の無機材料、ポリマーフィルム等の有機材料等を用いることができる。有機材料を基板として用いる場合には、平滑性、防湿、防酸素等の特性を付与するため金属酸化物薄膜等を表面にコートしてもよい。
(substrate)
The substrate is generally provided under the drain electrode (D), as long as it can support the device of the present invention. The material is not particularly limited as long as the surface is smooth, and an inorganic material such as glass or silicon, an organic material such as a polymer film, or the like can be used. When an organic material is used as the substrate, a metal oxide thin film or the like may be coated on the surface in order to impart characteristics such as smoothness, moisture resistance, and oxygen resistance.
（電極）
ソース電極（Ｓ）、ドレイン電極（Ｄ）及びゲート電極（Ｇ）は十分な導電性を有する材質であれば特に限定されず、金、銀、銅、白金、ニッケル、タングステン、アルミニウム、これらの合金等の金属類、ＩＴＯ、フッ素ドープされた酸化第二スズ、酸化バナジウム等の金属酸化物類、グラファイト、Ｎ型またはＰ型にドーピングされたダイヤモンド、シリコンや化合物半導体類、ポリアニリン類、ポリチオフェン類、ポリピロール類等の共役性高分子化合物を含む有機導電材料等を用いることができる。
(electrode)
The source electrode (S), the drain electrode (D), and the gate electrode (G) are not particularly limited as long as the materials have sufficient conductivity. Gold, silver, copper, platinum, nickel, tungsten, aluminum, and alloys thereof Metals such as ITO, fluorine-doped stannic oxide, vanadium oxide, graphite, diamond doped with N-type or P-type, silicon and compound semiconductors, polyanilines, polythiophenes, An organic conductive material containing a conjugated polymer compound such as polypyrrole can be used.
ソース電極（Ｓ）およびドレイン電極（Ｄ）の厚さは特に限定されない。通常５ｎｍ〜１０００ｎｍであり、好ましくは８ｎｍ〜２００ｎｍ、より好ましくは１０ｎｍ〜１００ｎｍである。ゲート電極（Ｇ）及びドレイン電極（Ｄ）はシート状に形成されていればよく、形状は平面状でも、曲面状でも、円筒状でもよい。ソース電極（Ｓ）及びドレイン電極（Ｄ）は、活性層に対して電気的にオーム性の接触となることが望ましい。 The thicknesses of the source electrode (S) and the drain electrode (D) are not particularly limited. Usually, it is 5 nm-1000 nm, Preferably it is 8 nm-200 nm, More preferably, it is 10 nm-100 nm. The gate electrode (G) and the drain electrode (D) may be formed in a sheet shape, and the shape may be flat, curved, or cylindrical. The source electrode (S) and the drain electrode (D) are preferably in an ohmic contact with the active layer.
ゲート電極（Ｇ）の厚さは特に限定されない。通常５ｎｍ〜５００ｎｍであり、好ましくは８ｎｍ〜１００ｎｍ、より好ましくは１０ｎｍ〜５０ｎｍである。５００ｎｍ以下であればソース電極（Ｓ）とドレイン電極（Ｄ）の間隔が拡大しすぎず、素子の内部抵抗の上昇を抑えることができる。また、５ｎｍ以上であれば、均一な連続膜を形成することができる上、ゲート電極（Ｇ）のシート抵抗が増大せず、素子の電圧−電流特性が悪化せず、ＯＦＦ電流値も増大も抑制できる。ゲート電極（Ｇ）は、活性層に対して電気的にショットキ性の接触となることが望ましい。 The thickness of the gate electrode (G) is not particularly limited. Usually, it is 5 nm-500 nm, Preferably it is 8 nm-100 nm, More preferably, it is 10 nm-50 nm. If it is 500 nm or less, the space | interval of a source electrode (S) and a drain electrode (D) will not expand too much, and the raise of the internal resistance of an element can be suppressed. If the thickness is 5 nm or more, a uniform continuous film can be formed, the sheet resistance of the gate electrode (G) does not increase, the voltage-current characteristics of the element do not deteriorate, and the OFF current value also increases. Can be suppressed. The gate electrode (G) is preferably in electrical Schottky contact with the active layer.
ゲート電極（Ｇ）の一方の面はソース電極（Ｓ）に、他方の面はドレイン電極（Ｄ）に対面しており、それぞれの面に開口部を１つずつ有する複数の貫通孔が形成されている。ドレイン電極（Ｄ）の一方の面はゲート電極（Ｇ）に、他方の面は基板に対面しており、それぞれの面に開口部を１つずつ有する複数の貫通孔が形成されている。ドレイン電極（Ｄ）の貫通孔はゲート電極（Ｇ）の貫通孔と実質的に同じ位置に存在する（図２及び３）。 One surface of the gate electrode (G) faces the source electrode (S) and the other surface faces the drain electrode (D), and a plurality of through holes having one opening on each surface are formed. ing. One surface of the drain electrode (D) faces the gate electrode (G), the other surface faces the substrate, and a plurality of through holes having one opening on each surface are formed. The through hole of the drain electrode (D) exists at substantially the same position as the through hole of the gate electrode (G) (FIGS. 2 and 3).
ドレイン電極（Ｄ）及びゲート電極（Ｇ）の開口部の平均半径は絶縁層（ＧＩ）を介したドレイン電極（Ｄ）とゲート電極間の距離の合計と同じ程度であることが好ましい。それぞれの開口部の孔径は１ｎｍ〜１０μｍであるのが好ましく、１０ｎｍ〜１０００ｎｍであるのがより好ましく、２０ｎｍ〜５００ｎｍであるのが更に好ましい。開口部が１０μｍ以下であれば、ＯＦＦ電流値が増大せず、駆動電圧が上昇を避けることができる。また、１ｎｍ以上であれば素子をＯＮとすることができる。また、開口部の開口率（開口部の総面積×１００／貫通孔が形成されている領域の総面積）は１０〜９０％が好ましく、２０〜８０％がより好ましい。開口率が１０％以上であれば素子の内部抵抗が増大せず、開口率が９０％以下であればゲート電極（Ｇ）のシート抵抗が増大するのを抑制することができる。 The average radius of the openings of the drain electrode (D) and the gate electrode (G) is preferably about the same as the total distance between the drain electrode (D) and the gate electrode through the insulating layer (GI). The pore diameter of each opening is preferably 1 nm to 10 μm, more preferably 10 nm to 1000 nm, and still more preferably 20 nm to 500 nm. If the opening is 10 μm or less, the OFF current value does not increase and the drive voltage can be prevented from rising. If the thickness is 1 nm or more, the element can be turned on. Further, the opening ratio of the opening (total area of the opening × 100 / total area of the region where the through holes are formed) is preferably 10 to 90%, and more preferably 20 to 80%. If the aperture ratio is 10% or more, the internal resistance of the element does not increase, and if the aperture ratio is 90% or less, an increase in the sheet resistance of the gate electrode (G) can be suppressed.
図４は本発明の有機スイッチング素子に用いるゲート電極を示す部分平面図である。ゲート電極（Ｇ）は複数の貫通孔により形成された開口部を有する。ドレイン電極（Ｄ）はゲート電極（Ｇ）と同様の形状（図２，３）を有する。 FIG. 4 is a partial plan view showing a gate electrode used in the organic switching element of the present invention. The gate electrode (G) has an opening formed by a plurality of through holes. The drain electrode (D) has the same shape (FIGS. 2 and 3) as the gate electrode (G).
一般にＳＩＴにおいては、開口部がゲート電極（Ｇ）全体にわたって均一に配置されている方がゲート電極（Ｇ）面内の電位分布が均質になり易く、電界集中等による素子破壊等が起きにくい。またゲート電圧の変化に応じてソース・ドレイン間に流れる電流値も急峻に変化させることができる。 In general, in SIT, when the openings are uniformly arranged over the entire gate electrode (G), the potential distribution in the plane of the gate electrode (G) is more likely to be uniform, and device breakdown due to electric field concentration or the like is less likely to occur. In addition, the value of the current flowing between the source and drain can be changed abruptly according to the change in the gate voltage.
これを防止するためには、ゲート電圧に対するソース・ドレイン間電流の応答性をある程度落す方がむしろ好ましい。開口部の孔径に分布を持たせるとゲート電極面内の電圧の掛かり方が不均一になるため、応答性が低下する。ただし、あまり不規則にしてしまうと応答性が必要以上に低下してしまう上、電界集中による素子破壊等も起こりやすくなる。開口部の孔径の分布は、ＣＶ値で０．１％〜２０％の範囲が好ましい。 In order to prevent this, it is preferable to reduce the responsiveness of the source-drain current to the gate voltage to some extent. If distribution is given to the hole diameters of the openings, the method of applying a voltage in the gate electrode surface becomes non-uniform, and the responsiveness decreases. However, if it is too irregular, the responsiveness will be lowered more than necessary, and device breakdown due to electric field concentration will easily occur. The distribution of the hole diameter of the opening is preferably in the range of 0.1% to 20% in terms of CV value.
（絶縁層）
絶縁層（ＧＩ）としては絶縁性を有する材料が用いられる。例えば、ポリパラキシリレン、ポリアクリレート、ポリメチルメタクリレート、ポリスチレン、ポリビニルフェノール、ポリアミド、ポリイミド、ポリカーボネート、ポリエステル、ポリビニルアルコール、ポリ酢酸ビニル、ポリウレタン、ポリスルホン、エポキシ樹脂、フェノール樹脂等のポリマー及びこれらを組み合わせた共重合体；二酸化珪素、酸化アルミニウム、酸化チタン、酸化タンタル等の金属酸化物；ＳｒＴｉＯ３、ＢａＴｉＯ３等の強誘電性金属酸化物；窒化珪素、窒化アルミニウム等の窒化物；硫化物；フッ化物などの誘電体；あるいは、これら誘電体の粒子を分散させたポリマー；等が使用しうる。絶縁層（ＧＩ）の膜厚は、材料によって異なるが、通常５ｎｍ〜１０００ｎｍ、好ましくは１０ｎｍ〜５００ｎｍ、より好ましくは２０ｎｍ〜３００ｎｍである。
またこの絶縁層（ＧＩ）は絶縁材料であることが好ましいが、必ずしも絶縁性を有する必要はなく、有機半導体材料を充填してゲート電極とショットキー接合されている構造も使用することができる。
(Insulating layer)
An insulating material is used for the insulating layer (GI). For example, polymers such as polyparaxylylene, polyacrylate, polymethyl methacrylate, polystyrene, polyvinylphenol, polyamide, polyimide, polycarbonate, polyester, polyvinyl alcohol, polyvinyl acetate, polyurethane, polysulfone, epoxy resin, phenol resin, and combinations thereof Copolymers; Metal oxides such as silicon dioxide, aluminum oxide, titanium oxide and tantalum oxide; Ferroelectric metal oxides such as SrTiO 3 and BaTiO 3 ; Nitrides such as silicon nitride and aluminum nitride; Sulfides; Dielectrics such as compounds; or polymers in which particles of these dielectrics are dispersed; and the like can be used. Although the film thickness of an insulating layer (GI) changes with materials, it is 5 nm-1000 nm normally, Preferably it is 10 nm-500 nm, More preferably, it is 20 nm-300 nm.
This insulating layer (GI) is preferably made of an insulating material, but it is not necessarily required to have insulating properties, and a structure in which an organic semiconductor material is filled and Schottky junction with the gate electrode can be used.
有機静電誘導型トランジスタの製造方法
有機静電誘導型トランジスタ（ＳＩＴ）の製造方法として、微粒子をシャドーマスクとした薄膜形成方法において貫通孔を形成し、ＳＩＴを製造する方法を例示する。この製造方法は主に二つの工程からなる。第一の工程は、複数の貫通孔によるパターン形成された薄膜を基板上に形成する工程である。薄膜の形成方法としては、例えば基板上に付着させた微粒子をシャドーマスクとして用い、微粒子の上から蒸着等の手段により薄膜（図２の場合は、ドレイン電極、絶縁層、ゲート電極）を形成した後、液中超音波処理や粘着シートを貼り、その後剥離することで、選択的に微粒子を除去することによってパターン形成された薄膜を形成する方法等がある。第二の工程は第一の工程で形成したパターン形成薄膜上に蒸着等の手段により機能層（活性層及びソース電極）を積層し、ＳＩＴを形成する工程である。
以下工程ごとにさらに詳細に説明する。
Method for Producing Organic Static Induction Type Transistor As a method for producing an organic static induction type transistor (SIT), a method of producing a SIT by forming a through hole in a thin film formation method using fine particles as a shadow mask is exemplified. This manufacturing method mainly consists of two steps. The first step is a step of forming a thin film patterned with a plurality of through holes on a substrate. As a method of forming the thin film, for example, the fine particles adhered on the substrate are used as a shadow mask, and a thin film (in the case of FIG. 2, drain electrode, insulating layer, gate electrode) is formed by means such as vapor deposition from the fine particles. Thereafter, there is a method of forming a patterned thin film by selectively removing fine particles by applying an ultrasonic treatment in liquid or an adhesive sheet and then peeling it. The second step is a step of forming SIT by laminating functional layers (active layer and source electrode) on the patterned thin film formed in the first step by means such as vapor deposition.
Hereinafter, it demonstrates in detail for every process.
第一の工程
第一の工程とは、基板上に付着させた微粒子をシャドーマスクとして用い、微粒子の上から蒸着等の手段により薄膜を形成した後、液中超音波処理や粘着シートを貼り、その後剥離する処理を実施することで、選択的に微粒子を除去することによって貫通孔が形成された薄膜を形成する工程である。
The first step The first step is to use the fine particles adhered on the substrate as a shadow mask, form a thin film by means such as vapor deposition from above the fine particles, and then apply an ultrasonic treatment in the liquid or an adhesive sheet, and then This is a process of forming a thin film in which through-holes are formed by selectively removing fine particles by performing a peeling process.
（基板）
ここで用いられる基板の素材は特に制限はないが、例えば、ガラス、金属酸化物（例えば、酸化アルミニウム、ＳｉＯ２、ＩＴＯ）、これらの金属酸化物でコートしたプラスティックフィルム（例えば、ポリエチレンテレフタレート（ＰＥＴ）フィルム、ポリエチレンナフタレート（ＰＥＮ）フィルム、ポリカーボネートフィルム）などが好ましい。
さらに、基板表面の親疎水性、静電荷、凹凸等は微粒子の接着力に影響を与えるので、これらを制御することが好ましい。制御方法としては、紫外線（ＵＶ）・オゾン洗浄、表面修飾剤（例えば、ポリ（ジアリルジメチルアンモニウムクロライド）（ＰＤＤＡ）、ポリ(スチレンスルホン酸ナトリウム)、ポリ(3，4−オキシエチレンオキシチオフェン)）による表面修飾などが挙げられる。基板の厚さに特に制約はないが、ガラス基板であれば０．１ｍｍ〜１０ｍｍが好ましく、フィルム基板であれば１μｍ〜１ｍｍが好ましい。
(substrate)
The material of the substrate used here is not particularly limited. For example, glass, metal oxides (for example, aluminum oxide, SiO 2 , ITO), and plastic films coated with these metal oxides (for example, polyethylene terephthalate (PET)) ) Film, polyethylene naphthalate (PEN) film, polycarbonate film) and the like.
Furthermore, since hydrophilicity / hydrophobicity, electrostatic charge, unevenness and the like on the substrate surface affect the adhesion of fine particles, it is preferable to control them. Control methods include ultraviolet (UV) and ozone cleaning, surface modifiers (for example, poly (diallyldimethylammonium chloride) (PDDA), poly (sodium styrenesulfonate), poly (3,4-oxyethyleneoxythiophene)) The surface modification by etc. is mentioned. Although there is no restriction | limiting in particular in the thickness of a board | substrate, 0.1 mm-10 mm are preferable if it is a glass substrate, and 1 micrometer-1 mm are preferable if it is a film substrate.
（微粒子）
微粒子の材質は特に制限されないが、表面に静電荷を持つ、又は微粒子に静電荷を付与できることが好ましい。また、加熱処理により適度に軟化するものを用いることが好ましく、例えばポリマー微粒子の場合、ガラス転移温度が−１００℃〜２００℃が好ましく、０℃〜１２０℃がより好ましい。このような微粒子として、例えば、ポリスチレン微粒子、ポリメタクリル酸メチル微粒子、ポリメタクリル酸ベンジル微粒子などがあげられ、粒径が単分散で表面官能基の自由度が高く、入手も容易なことから、ポリスチレン微粒子がより好ましい。
また、微粒子と基板との静電的相互作用は、微粒子の形状や表面処理法によっても制御することができるので、適切な形状、表面処理を施すことができる。このとき、薄膜の形成後に微粒子を除去することにも適した形状、表面処理とすることがより好ましい。微粒子の形状は球状、楕円球状、多面体等が好ましく、球状がより好ましい。微粒子の表面修飾としては、微粒子のコアシェル化、化学修飾、プラズマ処理、界面活性剤の添加、置換基（例えば、カルボキシル基、トリアルキルアンモニウム基、アミノ基、水酸基、スルホン酸基）の付加などが好ましい。
さらに、薄膜に形成される微細孔のサイズ（開口径）は、微粒子のサイズ（粒径）によって制御できるので、所望のスイッチング素子の設計に適したサイズの粒子を選択することが好ましく、粒径（本発明において、粒径とは粒子の投影面積と等価な円の直径をいう）は１ｎｍ〜５μmが好ましく、１０ｎｍ〜２μmがより好ましく、３０ｎｍ〜１μmが特に好ましい。微粒子の粒径分布に特に制限はないが、単分散であることが好ましい。
(Fine particles)
The material of the fine particles is not particularly limited, but it is preferable that the surface has an electrostatic charge or can impart an electrostatic charge to the fine particles. Moreover, it is preferable to use what softens moderately by heat processing, for example, in the case of a polymer microparticle, glass transition temperature is preferable -100 degreeC-200 degreeC, and 0 degreeC-120 degreeC is more preferable. Examples of such fine particles include polystyrene fine particles, polymethyl methacrylate fine particles, and polybenzyl methacrylate fine particles. Since the particle size is monodispersed and the degree of freedom of surface functional groups is high, it is easy to obtain polystyrene. Fine particles are more preferable.
Further, since the electrostatic interaction between the fine particles and the substrate can be controlled by the shape of the fine particles and the surface treatment method, an appropriate shape and surface treatment can be performed. At this time, it is more preferable to have a shape and surface treatment suitable for removing fine particles after the formation of the thin film. The shape of the fine particles is preferably spherical, elliptical, or polyhedral, and more preferably spherical. The surface modification of fine particles includes core-shell formation of fine particles, chemical modification, plasma treatment, addition of a surfactant, addition of a substituent (for example, carboxyl group, trialkylammonium group, amino group, hydroxyl group, sulfonic acid group). preferable.
Furthermore, since the size (opening diameter) of the micropores formed in the thin film can be controlled by the size (particle diameter) of the fine particles, it is preferable to select particles having a size suitable for the design of the desired switching element. (In the present invention, the particle diameter means a diameter of a circle equivalent to the projected area of the particles) is preferably 1 nm to 5 μm, more preferably 10 nm to 2 μm, and particularly preferably 30 nm to 1 μm. The particle size distribution of the fine particles is not particularly limited, but is preferably monodispersed.
（分散液）
分散液は、微粒子と基板の静電的相互作用を妨げず、処理プロセス中、微粒子を安定して分散させることができる溶媒が好ましい。分散液は、水でも有機溶媒でもよいが、分散液の調製の容易さや、静電的相互作用を強く働かせるという観点からは水が好ましい。微粒子の分散性を良好にするため適当な界面活性剤を添加してもよい。微粒子の分散濃度は、微粒子または基板の性質、得られる微粒子の設置密度によって適宜制御することができ、好ましくは０．０１質量％〜１０質量％であり、０．１質量％〜１質量％がより好ましい。
(Dispersion)
The dispersion is preferably a solvent that does not hinder electrostatic interaction between the fine particles and the substrate and can stably disperse the fine particles during the treatment process. The dispersion may be water or an organic solvent, but water is preferred from the viewpoint of easy preparation of the dispersion and exerting strong electrostatic interaction. In order to improve the dispersibility of the fine particles, an appropriate surfactant may be added. The dispersion concentration of the fine particles can be appropriately controlled by the properties of the fine particles or the substrate and the density of the obtained fine particles, and is preferably 0.01% by mass to 10% by mass, and 0.1% by mass to 1% by mass. More preferred.
（微粒子の設置）
微粒子の基板への設置方法は通常、バーコート法、スキージ塗布法、スピンコート法、インクジェット法、スプレー法、浸漬吸着法が用いられている。中でもスピンコート法及び浸漬吸着法が好ましく用いられる。
浸漬吸着法とは、微粒子を分散した分散液中に基板を浸漬し、基板と粒子の静電的相互作用により、粒子を基板に吸着させる方法である。微粒子の設置においては、基板と粒子間の相互作用を十分に高めることが好ましく、基板自身が十分な静電荷を有していれば、直接、微粒子を基板に設置することが可能である。
一方、基板自身が静電荷を持たないか、又は持っていても弱い場合は、表面修飾剤を使用することができ、基板表面を修飾することにより、その静電荷を高めることができる。また、基板と微粒子が同一の静電荷を有する場合にも、表面修飾剤を用い、基板表面を正電荷とし、微粒子の設置を実現することができる。必要に応じて、複数の表面修飾剤を用い、積層した表面修飾層を形成することも可能である。
(Installation of fine particles)
As a method for placing the fine particles on the substrate, a bar coating method, a squeegee coating method, a spin coating method, an ink jet method, a spray method, or an immersion adsorption method is usually used. Of these, spin coating and immersion adsorption are preferably used.
The immersion adsorption method is a method in which a substrate is immersed in a dispersion liquid in which fine particles are dispersed, and particles are adsorbed on the substrate by electrostatic interaction between the substrate and the particles. In the placement of the fine particles, it is preferable to sufficiently enhance the interaction between the substrate and the particles. If the substrate itself has a sufficient electrostatic charge, the fine particles can be directly placed on the substrate.
On the other hand, when the substrate itself has no electrostatic charge or is weak even if it has, an electrostatic charge can be used, and the electrostatic charge can be increased by modifying the substrate surface. In addition, even when the substrate and the fine particles have the same electrostatic charge, the surface modification agent can be used to make the substrate surface positive and the fine particles can be placed. If necessary, a plurality of surface modifiers can be used to form a laminated surface modification layer.
（微粒子の設置後の処理）
分散液から引き上げた微粒子設置基板は、分散媒が残留しているため、室温での自然乾燥、圧縮空気による送風乾燥、減圧乾燥、昇温などにより乾燥させることが好ましい。
一方、基板を分散液から引き上げて乾燥する際には、設置した微粒子は凝集する性質をもつため問題が生ずる場合があり、これを防ぐ手段が必要となる。微粒子が凝集してしまうと、設置した微粒子の均一な分散性は失われ、素子としたときの性能を低下させる原因となるからである。このような凝集は、基板の上に残留した分散媒を乾燥させる際、微粒子の間には微小なメニスカスが形成され、粒子の間にキャピラリーフォースが働くことによって凝集が生じる。凝集を制御するためには、前述の基板と粒子間の静電的相互作用を強め、微粒子の基板への固着力を高めることが好ましい。
(Treatment after installation of fine particles)
Since the dispersion medium remains, the fine particle-installed substrate pulled up from the dispersion is preferably dried by natural drying at room temperature, blown drying with compressed air, reduced pressure drying, temperature rise, or the like.
On the other hand, when the substrate is pulled up from the dispersion and dried, the installed fine particles have the property of agglomerating, which may cause a problem, and means for preventing this is required. This is because if the fine particles are aggregated, the uniform dispersibility of the installed fine particles is lost, which causes a decrease in the performance of the device. In such agglomeration, when the dispersion medium remaining on the substrate is dried, a minute meniscus is formed between the fine particles, and agglomeration occurs due to the capillary force acting between the particles. In order to control agglomeration, it is preferable to increase the electrostatic interaction between the aforementioned substrate and particles, and to increase the adhesion of fine particles to the substrate.
固着力を高めるために、加熱により微粒子を適度に軟化させ、微粒子と基板の設置面積を増大させることが好ましい。加熱する方法は、基板を劣化させず、設置した微粒子を適度に軟化できればどのような方法でもよいが、液中でリンスする方法、加熱した微粒子分散液中に基板を浸漬する方法、ホットプレートなどを用いて基板を直接加熱する方法などが好ましい。液中リンスによる加熱の場合、リンス溶媒としては、水系溶媒（例えば、蒸留水、超純水、イオン交換水など）、有機溶媒（例えば、アルコール、アセトンなど）、又はそれらの混合液が好ましく用いられ、作業性や生産性の観点から水系溶媒がより好ましい。液中リンスによる加熱時間は適宜設定できるが、１秒〜１０分が好ましく、１０秒〜1分がより好ましい。
加熱する温度は、微粒子が基板に固着するように、適度に軟化する温度が好ましく、用いられる微粒子によって適宜設定することができる。例えば、ポリマー微粒子を用いた場合、そのポリマーのガラス転移温度（Ｔｇ）付近で加熱し軟化させることが好ましく、ガラス転移温度より３０℃高い温度以下、３０℃低い温度以上の温度範囲が好ましく、ガラス転移温度より１０℃高い温度以下、１０℃低い温度以上の温度範囲がより好ましい。さらに、加熱温度は、水系溶媒による液中リンスによる加熱、及び有機半導体の製造を考慮すると、７０℃〜１００℃が好ましく、８０℃〜１００℃がより好ましい。
In order to increase the fixing force, it is preferable to moderately soften the fine particles by heating and increase the installation area of the fine particles and the substrate. The heating method may be any method as long as the installed fine particles can be appropriately softened without deteriorating the substrate, but a method of rinsing in the liquid, a method of immersing the substrate in the heated fine particle dispersion, a hot plate, etc. A method in which the substrate is directly heated by using is preferable. In the case of heating by rinsing in liquid, as the rinsing solvent, an aqueous solvent (for example, distilled water, ultrapure water, ion-exchanged water, etc.), an organic solvent (for example, alcohol, acetone, etc.), or a mixture thereof is preferably used. In view of workability and productivity, an aqueous solvent is more preferable. The heating time by rinsing in the liquid can be appropriately set, but is preferably 1 second to 10 minutes, more preferably 10 seconds to 1 minute.
The heating temperature is preferably a temperature that softens moderately so that the fine particles adhere to the substrate, and can be appropriately set depending on the fine particles used. For example, when polymer fine particles are used, it is preferably heated and softened in the vicinity of the glass transition temperature (Tg) of the polymer, and a temperature range of 30 ° C. higher than the glass transition temperature and a temperature higher than 30 ° C. is preferable. A temperature range of not more than 10 ° C higher than the transition temperature and not less than 10 ° C is more preferable. Furthermore, the heating temperature is preferably 70 ° C. to 100 ° C., more preferably 80 ° C. to 100 ° C. in consideration of heating by submerged rinsing with an aqueous solvent and production of an organic semiconductor.
加熱後は、凝集を確実に防ぐため、冷却することが好ましく、例えば、冷却水（例えば室温以下の水）でリンスすることが好ましい。
また、微粒子を吸着させた後に、基板上の余分な粒子を洗浄することが好ましい。この処理をしない場合、微粒子が単粒子層にならず、粒子が積み重なった領域ができてしまうためである。
乾燥、加熱、冷却、及び洗浄を行う工程は、作業効率を考慮し適宜決定することができるが、微粒子の設置後、これらの工程を経た後、薄膜の形成に移行することが好ましい。また、加熱や冷却処理を液中リンスにより行う場合には、洗浄処理を兼ねることもできる。
After heating, in order to prevent aggregation reliably, it is preferable to cool, for example, it is preferable to rinse with cooling water (for example, water below room temperature).
Moreover, it is preferable to wash the excess particles on the substrate after the fine particles are adsorbed. If this treatment is not performed, the fine particles do not become a single particle layer, and a region where the particles are stacked is formed.
The steps of drying, heating, cooling, and washing can be appropriately determined in consideration of work efficiency, but it is preferable to move to the formation of a thin film after these steps after the installation of the fine particles. Moreover, when performing a heating and cooling process by the rinse in a liquid, it can also serve as a washing process.
（薄膜の設置）
本発明のＳＩＴにおける電極や絶縁膜は、例えば、スパッタリング法、蒸着法、めっき法、塗布法等の薄膜パターンニング方法、スプレー法などの各種の薄膜形成方法によって形成することができ、これらの方法は使用する材料に応じて適宜選択することができる。薄膜の厚さは、素子動作のための設計的観点と機械的選択剥離のための感度や選択比によって材料ごとに設定することができ、１ｎｍ〜１０μmが好ましい。ただし、設置した微粒子を除去する観点から、微細孔を形成する薄膜の厚さは、粒径と同等以下が好ましく、粒径の１／２以下がより好ましい。薄膜を積層膜とする場合、積層膜数に制限はない。
積層膜としたときの各層は素子としたときの各機能層とすることができ、例えば、ソース電極層（Ｓ）、ドレイン電極層（Ｄ）、ゲート電極層（Ｇ）、絶縁層（ＧＩ）、活性層（Ａ）などとすることができる。
本発明のＳＩＴにおいて具体的に示すと先に微粒子を設置した基板上にドレイン電極（Ｄ）、絶縁層（ＧＩ）、ゲート電極（Ｇ）の順に形成すればよい。
(Installation of thin film)
The electrode and the insulating film in the SIT of the present invention can be formed by various thin film forming methods such as a sputtering method, a vapor deposition method, a plating method, a coating method, and a thin film patterning method such as a spray method. Can be appropriately selected depending on the material to be used. The thickness of the thin film can be set for each material depending on the design viewpoint for device operation and the sensitivity and selectivity for mechanical selective peeling, and is preferably 1 nm to 10 μm. However, from the viewpoint of removing the installed fine particles, the thickness of the thin film forming the micropores is preferably equal to or less than the particle size, and more preferably ½ or less of the particle size. When the thin film is a laminated film, the number of laminated films is not limited.
Each layer in the laminated film can be a functional layer in the element. For example, the source electrode layer (S), the drain electrode layer (D), the gate electrode layer (G), and the insulating layer (GI). , And the active layer (A).
Specifically, in the SIT of the present invention, a drain electrode (D), an insulating layer (GI), and a gate electrode (G) may be formed in this order on a substrate on which fine particles have been previously placed.
（微粒子の除去）
基板に配設した微粒子の除去方法は、形成した薄膜を損傷せず、微粒子を確実に除去できる方法が好ましく、例えば、液中超音波処理や粘着シートを貼り、引き続き剥離する処理を実施することで、選択的な微粒子の除去などの方法が挙げられる。液中超音波処理により除去する場合、用いる溶媒は、微粒子を分散させることができ、薄膜などを損なわない溶媒を選択することが好ましい。例えば、形成する膜が有機溶媒に溶解しにくい材料で微粒子が親水性であれば、親水性の有機溶媒を用いる。剥離能及び選択性を高めるため、必要に応じて洗浄液の温度や超音波の強度および周波数を選択する。超音波の周波数としては100Hz〜100MHzが好ましく、１kHz〜10MHzがより好ましい。広範囲にわたる複数の周波数の超音波を同時に照射したり、順次周波数を切り替えて照射したりするのも好ましい。
粘着シートにより除去する工程を詳述する。粘着層と支持体からなる粘着シートを先に形成した薄膜を含む微粒子に貼りつけ、これを剥がすことにより、微粒子が微粒子上の薄膜ごと粘着層に粘着し除去される。微粒子が基板上に密に配設されているため、粘着シートは微粒子の上部に粘着し、粘着層が基板上の微粒子周辺の薄膜と粘着せず、薄膜を基板上に残すことができる。このようにして、薄膜を損傷、破壊などすることなく、微粒子および微粒子上の薄膜のみを除去し、均一な多孔薄膜堆積基板を形成することができる。
(Removal of fine particles)
The method for removing the fine particles disposed on the substrate is preferably a method that can reliably remove the fine particles without damaging the formed thin film. For example, by performing an ultrasonic treatment in liquid or an adhesive sheet, followed by a treatment of peeling. And a method such as selective removal of fine particles. When removing by ultrasonic treatment in liquid, it is preferable to select a solvent that can disperse the fine particles and does not damage the thin film. For example, if the film to be formed is a material that is difficult to dissolve in an organic solvent and the fine particles are hydrophilic, a hydrophilic organic solvent is used. In order to improve the peelability and selectivity, the temperature of the cleaning liquid and the intensity and frequency of the ultrasonic wave are selected as necessary. The frequency of ultrasonic waves is preferably 100 Hz to 100 MHz, and more preferably 1 kHz to 10 MHz. It is also preferable to irradiate ultrasonic waves having a plurality of frequencies over a wide range at the same time or sequentially switch the frequencies.
The process of removing with an adhesive sheet will be described in detail. By sticking an adhesive sheet composed of an adhesive layer and a support to the fine particles including the previously formed thin film and peeling it off, the fine particles adhere to the adhesive layer together with the thin film on the fine particles and are removed. Since the fine particles are densely arranged on the substrate, the adhesive sheet adheres to the upper part of the fine particles, and the adhesive layer does not adhere to the thin film around the fine particles on the substrate, and the thin film can be left on the substrate. In this way, it is possible to remove only the fine particles and the thin film on the fine particles without damaging or destroying the thin film, thereby forming a uniform porous thin film deposition substrate.
このような微粒子の除去に用いられる粘着シートは、微粒子の形状、微粒子の粒径、薄膜の材質、薄膜の厚さ（粒径との関係）などによって適宜選定することができ、特に制限されるものではない。これらの条件を満たせば、市販のものも用いることができる。微粒子の選択的で均一な接着を確保するために、粘着面は平滑であることが好ましい。粘着面の平滑性は、目視において、凹凸が認められないことが好ましい。また、基材にエンボス加工等を施したり、クレープ紙等の基材自身が凹凸を有する場合、粘着面も基材の凹凸を反映するため、基材が目視において認められるような凹凸を持たないものが好ましい。また、粒子表面の薄膜材料に対して適度な粘着力を有することが好ましく、例えば、粘着力を示すＪＩＳ Ｚ−０２３７の値において、０．１N/cm〜５N/cmが好ましく、０．３N/cm〜３N/cmがより好ましい。さらに、基板表面に均一に密着するよう、支持体を含めたシートが適度に柔軟であることが好ましく、例えば、伸びが５０％以上であることが好ましく、１００％以上であることがより好ましい。
支持体を構成する材料は特に制限されないが、ポリ塩化ビニル系フィルム、ポリエステル系フィルム、クレープ紙、ポリオレフィン系白色フィルム、アセテートフィルム、及びこれらのコポリマーやブレンドポリマーなどが挙げられる。粘着剤に用いられる材料は、適度な粘着力があり、薄膜上を汚染しなければ特に制限されないが、ゴム系粘着剤、アクリル系粘着剤、ウレタン系粘着剤などが挙げられる。粘着シートの厚さは、柔軟性（例えば、伸びなど）や強度（例えば、引張強度など）に応じて選定することができ、特に制約はないが、１０μｍ〜１ｍｍが好ましく、５０μｍ〜３００μｍがより好ましい。
電子デバイスへの応用を考えた場合、貼り付け、剥離時に基板表面をイオン性化合物等の有害物質や微粒子で汚染しないことが好ましく、好ましい粘着シートとして、例えば、シリコン半導体のバックグラインディング時に用いる保護フィルムなどが挙げられる。
The pressure-sensitive adhesive sheet used for the removal of such fine particles can be appropriately selected depending on the shape of the fine particles, the particle size of the fine particles, the material of the thin film, the thickness of the thin film (relation with the particle size), and is particularly limited. It is not a thing. A commercially available product can also be used if these conditions are satisfied. In order to ensure selective and uniform adhesion of the fine particles, the pressure-sensitive adhesive surface is preferably smooth. The smoothness of the adhesive surface is preferably such that no irregularities are observed visually. In addition, when embossing or the like is applied to the base material, or when the base material itself such as crepe paper has unevenness, the adhesive surface also reflects the unevenness of the base material, so the base material does not have the unevenness that is visually recognized. Those are preferred. Moreover, it is preferable to have an appropriate adhesive force to the thin film material on the particle surface. For example, in the value of JIS Z-0237 indicating the adhesive force, 0.1 N / cm to 5 N / cm is preferable, and 0.3 N / More preferred is cm to 3 N / cm. Furthermore, it is preferable that the sheet including the support is appropriately flexible so as to uniformly adhere to the substrate surface. For example, the elongation is preferably 50% or more, and more preferably 100% or more.
The material constituting the support is not particularly limited, and examples thereof include polyvinyl chloride film, polyester film, crepe paper, polyolefin white film, acetate film, and copolymers and blend polymers thereof. The material used for the pressure-sensitive adhesive has an appropriate pressure-sensitive adhesive force and is not particularly limited as long as it does not contaminate the thin film, and examples thereof include a rubber-based pressure-sensitive adhesive, an acrylic pressure-sensitive adhesive, and a urethane-based pressure-sensitive adhesive. The thickness of the pressure-sensitive adhesive sheet can be selected according to flexibility (for example, elongation) and strength (for example, tensile strength), and is not particularly limited, but is preferably 10 μm to 1 mm, more preferably 50 μm to 300 μm. preferable.
When considering application to electronic devices, it is preferable that the substrate surface is not contaminated with harmful substances such as ionic compounds and fine particles during pasting and peeling, and as a preferred adhesive sheet, for example, protection used during back grinding of silicon semiconductors A film etc. are mentioned.
粘着テープの貼り付けは、貼り付け時に気泡を巻き込むことを避けることが好ましい。
また、剥離する方法は、微粒子を確実に除去し、薄膜堆積基板を損傷しない方法が好ましく、例えば、緩やかな速度で、目視により確認しながら剥離を行ってもよい。さらに、貼り付け及び剥離時の、圧着する圧力、圧着もしくは剥離する速さ、剥離時の基板とシートの角度などを制御することが好ましく、圧着器具（例えば０．１ｋｇ〜５ｋｇ程度加重）などを適宜選定して使用することが好ましい。
また、粘着シートの基材面をローラーに巻き付けたものや、ローラーの表面が粘着性を有しているものを用いてもよい。
It is preferable that the adhesive tape is affixed to avoid entrainment of bubbles during the affixing.
Further, the peeling method is preferably a method that reliably removes the fine particles and does not damage the thin film deposition substrate. For example, the peeling may be performed while visually checking at a moderate speed. Furthermore, it is preferable to control the pressure for pressure bonding, the speed of pressure bonding or peeling, the angle between the substrate and the sheet at the time of peeling, and the like, for example, a pressure bonding device (for example, a weight of about 0.1 kg to 5 kg). It is preferable to select and use as appropriate.
Moreover, you may use what wound the base material surface of the adhesive sheet around the roller, and the surface of the roller has adhesiveness.
（微細構造）
本発明の多孔薄膜堆積基板における微細孔の開口径（以下、「孔径」ともいう）は、形成過程で用いられる微粒子の粒径にほぼ等しくなる。この性質を利用して、微粒子の粒径、粒径の分布を変化することによって、薄膜の孔径、孔径の分布を自由に制御することができる。孔の位置は基本的にはランダムであるが、孔と孔の相対的位置関係には一定の規則性を有する。これは、孔の位置は微粒子を設置した位置と同じ位置であり、孔間距離は粒子間距離によって定まるからである。
(Fine structure)
The opening diameter of micropores (hereinafter also referred to as “pore diameter”) in the porous thin film deposition substrate of the present invention is substantially equal to the particle diameter of the fine particles used in the formation process. By utilizing this property and changing the particle size and particle size distribution of the fine particles, the pore size and pore size distribution of the thin film can be freely controlled. Although the positions of the holes are basically random, the relative positional relationship between the holes has a certain regularity. This is because the positions of the holes are the same as the positions where the fine particles are installed, and the distance between the holes is determined by the distance between the particles.
以上の第一の工程により複数の貫通孔を有するパターン形成された多孔薄膜構造体基板を形成することが出来る。以下に示す第２の工程にて、引き続きこの多孔基板に機能層を積層し有機ＳＩＴを製造する。 The patterned thin film structure substrate having a plurality of through holes can be formed by the above first step. In the second step shown below, an organic SIT is manufactured by successively laminating a functional layer on this porous substrate.
（活性層（Ａ）の設置）
先に述べた活性層用の有機半導体材料を使用して、先に述べた薄膜の設置と同様の方法を用いて活性層を設置する。本発明の縦型静電誘導型トランジスタでは半導体材料として、一般式（１）で表される化合物が用いられることが特徴である。該化合物は混合物であってもよいが、活性層（Ａ）中には式（１）で表される化合物を通常５０重量％以上、好ましくは８０重量％以上、更に好ましくは９５重量％以上含むことが好ましい。一般的に本発明の一般式（１）の化合物はホール輸送型のＰ型半導体として用いられる。
電界効果トランジスタの特性を改善したり他の特性を付与するために、必要に応じて他の有機半導体材料や各種添加剤が混合されていてもよい。
活性層を形成するにあたっては、各種の製膜方法を用いることができるが、好ましくはスパッタリング法、ＣＶＤ法、分子線エピタキシャル成長法、真空蒸着法等の真空プロセスでの形成方法；ディップコート法、ダイコーター法、ロールコーター法、バーコーター法、スピンコート法等の塗布法、インクジェット法、スクリーン印刷法、オフセット印刷法、マイクロコンタクト印刷法などの溶液プロセスでの形成方法；が挙げられる。
(Installation of active layer (A))
Using the organic semiconductor material for the active layer described above, the active layer is set using the same method as the setting of the thin film described above. The vertical electrostatic induction transistor of the present invention is characterized in that a compound represented by the general formula (1) is used as a semiconductor material. The compound may be a mixture, but the active layer (A) usually contains 50% by weight or more, preferably 80% by weight or more, more preferably 95% by weight or more of the compound represented by the formula (1). It is preferable. Generally, the compound of the general formula (1) of the present invention is used as a hole transport type P-type semiconductor.
In order to improve the characteristics of the field effect transistor or to impart other characteristics, other organic semiconductor materials and various additives may be mixed as necessary.
In forming the active layer, various film forming methods can be used, but preferably a forming method in a vacuum process such as a sputtering method, a CVD method, a molecular beam epitaxial growth method, or a vacuum deposition method; Coating method such as coating method, roll coater method, bar coater method, spin coating method, etc., forming method in solution process such as ink jet method, screen printing method, offset printing method, micro contact printing method.
一例として有機材料を蒸着法によって成膜し活性層を得る方法について説明する。
前記有機半導体材料をルツボや金属のボート中で真空下で、加熱し、蒸発した有機材料を第１の工程で得た基板に付着（蒸着）させる方法、すなわち真空蒸着法が好ましく採用される。この際の真空度は、通常１．０×１０−１Ｐａ以下、好ましくは１．０×１０−３Ｐａ以下である。また、蒸着時の基板温度によって有機半導体膜、ひいては電界効果トランジスタの特性が変化する場合があるので、注意深く基板温度を選択するのが好ましい。蒸着時の基板温度は通常、０〜２００℃であり、好ましくは−１０〜１５０℃であり、より好ましくは０〜１２０℃であり、さらに好ましくは５〜１００℃であり、特に好ましくは１０〜８０℃である。
また、蒸着速度は、通常０．００１ｎｍ／秒〜１０ｎｍ／秒であり、好ましくは０．０１ｎｍ／秒〜１ｎｍ／秒である。
有機材料から形成される活性層の膜厚は、通常１ｎｍ〜１０μｍ、好ましくは５ｎｍ〜５μｍより好ましくは１０ｎｍ〜３μｍである。これは多孔薄膜と開口径や膜厚と密接な関係が生じるため、注意深く最適値を選ぶ必要がある。
また、このように形成された半導体層は、後処理によりさらに特性を改良することが可能である。例えば、熱処理により、成膜時に生じた膜中の歪みが緩和されること、ピンホール等が低減されること、膜中の配列・配向が制御できると考えられていること等の理由により、半導体特性の向上や安定化を図ることができる。本発明の電界効果トランジスタの作成時にはこの熱処理を行うことが特性の向上の為には効果的である。本熱処理は半導体層を形成した後に基板を加熱することによって行う。熱処理の温度は特に制限は無いが通常、室温から２００℃程度で、好ましくは８０〜１８０℃、さらに好ましくは１２０〜１５０℃である。この時の熱処理時間については特に制限は無いが通常１分から２４時間、好ましくは２分から３時間程度である。その時の雰囲気は大気中でもよいが、窒素やアルゴンなどの不活性雰囲気下でもよい。
As an example, a method for obtaining an active layer by depositing an organic material by vapor deposition will be described.
A method in which the organic semiconductor material is heated in a crucible or a metal boat under vacuum to deposit (evaporate) the evaporated organic material on the substrate obtained in the first step, that is, a vacuum evaporation method is preferably employed. The degree of vacuum at this time is usually 1.0 × 10 −1 Pa or less, preferably 1.0 × 10 −3 Pa or less. In addition, since the characteristics of the organic semiconductor film, and thus the field effect transistor, may change depending on the substrate temperature during vapor deposition, it is preferable to select the substrate temperature carefully. The substrate temperature at the time of vapor deposition is usually 0 to 200 ° C., preferably −10 to 150 ° C., more preferably 0 to 120 ° C., further preferably 5 to 100 ° C., and particularly preferably 10 to 10 ° C. 80 ° C.
The deposition rate is usually 0.001 nm / second to 10 nm / second, preferably 0.01 nm / second to 1 nm / second.
The film thickness of the active layer formed from an organic material is usually 1 nm to 10 μm, preferably 5 nm to 5 μm, more preferably 10 nm to 3 μm. Since this has a close relationship with the porous thin film and the opening diameter and film thickness, it is necessary to carefully select an optimum value.
In addition, the characteristics of the semiconductor layer thus formed can be further improved by post-processing. For example, it is considered that the heat treatment reduces strain in the film generated during film formation, reduces pinholes, etc., and can control the arrangement and orientation in the film. The characteristics can be improved and stabilized. In order to improve the characteristics, it is effective to perform this heat treatment when producing the field effect transistor of the present invention. This heat treatment is performed by heating the substrate after forming the semiconductor layer. The temperature of the heat treatment is not particularly limited, but is usually from room temperature to about 200 ° C., preferably 80 to 180 ° C., more preferably 120 to 150 ° C. The heat treatment time at this time is not particularly limited, but is usually about 1 minute to 24 hours, preferably about 2 minutes to 3 hours. The atmosphere at that time may be air, but may be an inert atmosphere such as nitrogen or argon.
（電荷注入層（ＣＩ）の設置）
先に述べた活性層が複数の層の構成時に設置される。先に述べた薄膜の設置と同様の方法を用いて設置すればよい。一般的には蒸着法が用いられ、活性層の製膜方法と同様である。用いる材料も先に述べているが、一般式（１）で表される化合物と上述の特定材料との共蒸着によって形成するのが好適である。共蒸着の割合については材料によって異なるため、一概には言えないが一般式（１）で表される化合物の含有率が５０〜９９．９％、好ましくは７０〜９９．５％、さらに好ましくは８０〜９９％である。膜厚は電荷注入効率をコントロールするのみでなく、大気安定性を上げるためにも重要なポイントであり注意深く選ぶ必要がある。通常１ｎｍ〜５０００ｎｍ、好ましくは５０ｎｍ〜５００ｎｍより好ましくは１００ｎｍ〜３００ｎｍである。
(Installation of charge injection layer (CI))
The active layer described above is installed when a plurality of layers are formed. What is necessary is just to install using the method similar to installation of the thin film mentioned previously. In general, a vapor deposition method is used, which is the same as the method for forming the active layer. Although the material to be used is also described above, it is preferable to form the material by co-evaporation of the compound represented by the general formula (1) and the specific material described above. Since the ratio of co-evaporation varies depending on the material, the content of the compound represented by the general formula (1) is 50 to 99.9%, preferably 70 to 99.5%, more preferably, although it cannot be generally stated. 80-99%. The film thickness is an important point not only for controlling the charge injection efficiency but also for improving the atmospheric stability and must be carefully selected. Usually, 1 nm to 5000 nm, preferably 50 nm to 500 nm, more preferably 100 nm to 300 nm.
（ソース電極（Ｓ）の設置）
活性層（Ａ）の上にスパッタリング法、蒸着法、めっき、ＬＰＤ法等により、好ましくは活性層（Ａ）へのダメージが少ない蒸着法によりソース電極（Ｓ）を形成する。併せて必要に応じてソース電極を所望の配線パターンにパターニングして有機静電誘導型トランジスタ（ＳＩＴ）を完成する。
(Installation of source electrode (S))
A source electrode (S) is formed on the active layer (A) by sputtering, vapor deposition, plating, LPD, or the like, preferably by vapor deposition with little damage to the active layer (A). In addition, if necessary, the source electrode is patterned into a desired wiring pattern to complete an organic electrostatic induction transistor (SIT).
（ＳＩＴアレイ）
上記のように作成した薄膜トランジスタをマトリックス状に配置し、液晶ディスプレイ、エレクトロクロミックディスプレイ、有機ＥＬディスプレイ、デジタルペーパー等の表示装置駆動用のアレイを構成することができる。また本発明のは、ＩＣタグ、ＲＦタグ、ＩＣカード、メモリ、各種センサー（ガスセンサー、ｐＨセンサー等）等の各種の電子デバイスに用いることができる。
(SIT array)
The thin film transistors created as described above can be arranged in a matrix to form an array for driving a display device such as a liquid crystal display, an electrochromic display, an organic EL display, or digital paper. Further, the present invention can be used for various electronic devices such as an IC tag, an RF tag, an IC card, a memory, and various sensors (gas sensor, pH sensor, etc.).
本発明における式（１）で表される化合物は成膜性がよい。ペンタセン誘導体やフタロシアニン誘導体を用いた有機ＳＩＴなどは、大気中においては大気に含まれる水分や酸素などにより不安定で特性が劣化したが、本発明の上記式（１）で表される化合物を半導体材料として用いた場合には、半導体層の作製後においても安定性が高いという利点がある。また上記式（１）で表される化合物により形成された半導体層を有する有機ＳＩＴは大気安定性のみでなく、更に特定の構造を有するアクセプタ型有機材料を組み合わせて用いることにより、高ＯＮ／ＯＦＦ比、高電流密度を兼ね備えた実用的な縦型有機半導体デバイス、更に詳しくは静電誘導型トランジスタを提供できることが明らかになった。
電極から半導体膜への電荷の注入障壁が低減されることにより、半導体素子及びそれを有する半導体デバイス自体の耐久性の向上にも効果があると期待される。
The compound represented by the formula (1) in the present invention has good film forming properties. Organic SIT using a pentacene derivative or a phthalocyanine derivative is unstable and deteriorated in the atmosphere due to moisture or oxygen contained in the atmosphere, but the compound represented by the above formula (1) of the present invention is a semiconductor. When used as a material, there is an advantage that stability is high even after a semiconductor layer is manufactured. In addition, the organic SIT having the semiconductor layer formed of the compound represented by the above formula (1) is not only stable in the atmosphere, but also by using an acceptor type organic material having a specific structure in combination with high ON / OFF. It has been clarified that a practical vertical organic semiconductor device having a high ratio and a high current density, more specifically, an electrostatic induction transistor can be provided.
It is expected that the durability of the semiconductor element and the semiconductor device having the semiconductor element itself can be improved by reducing the charge injection barrier from the electrode to the semiconductor film.
以下、実施例を挙げて本発明を更に詳細に説明するが、本発明はこれらの例に限定されるものではない。実施例中、部は特に指定しない限り質量部を、また％は質量％を、「化合物Ｎｏ．」は上記一般式（１）で表される化合物の具体例で示された「化合物Ｎｏ．」をそれぞれ表す。 EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated still in detail, this invention is not limited to these examples. In Examples, unless otherwise specified, parts are parts by mass,% is% by mass, and “Compound No.” is “Compound No.” shown in the specific example of the compound represented by the general formula (1). Respectively.
実施例１
粒径が２００ｎｍの４級アンモニウムカチオンポリスチレン微粒子(ＥＳ−Ｋ６−１０：メルク社)を用い、０．０５質量％分散溶液濃度の分散液を作成した。この中に、洗剤、アセトン及びＵＶ／Ｏ３洗浄したガラス基板を浸漬し、室温で３０分静置した。その後、基板を９０℃超純水中で３０秒間リンスによる加熱処理を施し、更に室温の超純水で３０秒間リンスし冷却した。超純水から基板を引き上げ、圧縮空気で余分な水を取り除いた後、室温で減圧乾燥を８時間行い基板に微粒子を設置した。
この微粒子設置基板にドレイン電極としてプラチナをＵＬＶＡＣ ＫＩＫＯ社製マグネトロンスパッタ装置（ＳＣＯＴＴ−Ｃ３）を用いて２０ｎｍの厚さにＲＦスパッタした（ターゲット基板間距離は５０ｍｍ、スパッタガス：アルゴン、流量：３０ｓｃｃｍ、ガス圧：０．８Ｐａ、印加電圧：５０Ｗ、製膜レート０．５７ｎｍ／ｓｅｃ）。引き続き、ＳｉＯ２ターゲットとした反応性スパッタリングにて絶縁層のＳｉＯ２を１００ｎｍの厚さに製膜した（スパッタガス：アルゴン，Ｏ２、流量：３０ｓｃｃｍ，１．８ｓｃｃｍ、ガス圧：０．８Ｐａ、印加電圧：１００Ｗ、製膜レート０．１３ｎｍ／ｓｅｃ）。次いで、ゲート電極のアルミを真空蒸着法で０．１−０．２ｎｍ／ｓｅｃの蒸着レートで２０ｎｍ蒸着した。この基板を固定し、試料の表面に粘着テープ（三井化学ＩＣＲＯＳ ＴＡＰＥ：ＳＢ−２０５Ｓ−Ｋ−Ｒ１）を添付し、ハンドローラーを用いて定着し、引き続きゆっくりと剥離することで微粒子を除去し、ＵＶオゾン処理（１５０℃４５分）を実施し微細孔を多数有する多孔薄膜構造体基板を形成した。
次いでこの基板を真空蒸着機に設置し、活性層として化合物（１０）を０．１ｎｍ／ｓｅｃの蒸着速度で２５０ｎｍの膜厚にて製膜した。引き続き電荷注入層として化合物（１０）とフラーレン誘導体Ｃ６０Ｆ３６各々０．０９及び０．０１ｎｍ／ｓｅｃの蒸着速度で共蒸着し（体積比率；化合物（１０）：９０％、Ｃ６０Ｆ３６：１０％）、１００ｎｍの膜厚に製膜した。
最後に上部のソース電極として銀を０．２ｎｍ／ｓｅｃの蒸着速度で５０ｎｍの膜厚に製膜して静電誘導型トランジスタを得た。
半導体特性の測定はＡｇｉｌｅｎｔ Ｔｅｃｈｎｏｌｏｇｉｅｓ社製半導体パラメーターアナライザー Ｅ５２７２Ａを用いて行った。素子面積は２×２ｍｍ２とした。測定はソース電極作成後、大気にさらすことなく素子を作りこみ、まず窒素雰囲気の測定チャンバー中で測定し、その後測定チャンバーに酸素を導入し２日保管後、酸素雰囲気中で測定、更に測定チャンバーを大気開放し２日保管後、大気中での測定を実施し、酸素及び大気暴露に対する安定性を評価した。
大気中でのＯＮ電流：６．５ｍＡ、ＯＮ／ＯＦＦ比 １２１０
本素子のＳＩＴ特性の伝達特性及び大気中の出力静特性を図５に示す。
大気中及び酸素中のＯＮ電流を含めて、結果はまとめて表１に示す。
（表中、ＯＮ電流、ＯＮ／ＯＦＦ比はともに大気中の伝達特性から得ており、ａｉｒ／Ｎ２、Ｏ２／Ｎ２は各雰囲気中のＯＮ電流の比を示している。）
Example 1
Using a quaternary ammonium cationic polystyrene fine particle (ES-K6-10: Merck) having a particle size of 200 nm, a dispersion having a concentration of 0.05 mass% was prepared. In this, a glass substrate washed with detergent, acetone and UV / O 3 was immersed and allowed to stand at room temperature for 30 minutes. Thereafter, the substrate was heat-treated by rinsing in 90 ° C. ultrapure water for 30 seconds, and further rinsed with ultrapure water at room temperature for 30 seconds and cooled. The substrate was lifted from the ultrapure water, excess water was removed with compressed air, and then dried under reduced pressure at room temperature for 8 hours to place fine particles on the substrate.
RF was sputtered onto the fine particle-installed substrate using platinum as a drain electrode to a thickness of 20 nm using a magnetron sputtering device (SCOTT-C3) manufactured by ULVAC KIKO (target substrate distance was 50 mm, sputtering gas: argon, flow rate: 30 sccm, (Gas pressure: 0.8 Pa, applied voltage: 50 W, film forming rate 0.57 nm / sec). Subsequently, by reactive sputtering using a SiO 2 target was formed of SiO 2 insulating layer to a thickness of 100 nm (sputtering gas: argon, O2, flow rate: 30 sccm, 1.8Sccm, gas pressure: 0.8 Pa, applied (Voltage: 100 W, film formation rate 0.13 nm / sec). Next, aluminum of a gate electrode was deposited by 20 nm at a deposition rate of 0.1-0.2 nm / sec by vacuum deposition. This substrate is fixed, an adhesive tape (Mitsui Chemical ICROS TAPE: SB-205S-K-R 1 ) is attached to the surface of the sample, fixed using a hand roller, and then slowly peeled off to remove fine particles. Then, UV ozone treatment (150 ° C. for 45 minutes) was carried out to form a porous thin film structure substrate having a large number of micropores.
Next, this substrate was set in a vacuum vapor deposition machine, and a compound (10) was formed as an active layer with a film thickness of 250 nm at a vapor deposition rate of 0.1 nm / sec. Subsequently, the compound (10) and the fullerene derivative C60F36 were co-deposited at a deposition rate of 0.09 and 0.01 nm / sec as a charge injection layer (volume ratio; compound (10): 90%, C60F36: 10%), respectively. The film was formed to a film thickness.
Finally, silver was formed into a film thickness of 50 nm at a deposition rate of 0.2 nm / sec as an upper source electrode to obtain an electrostatic induction transistor.
Measurement of semiconductor characteristics was performed using a semiconductor parameter analyzer E5272A manufactured by Agilent Technologies. The element area was 2 × 2 mm 2 . After making the source electrode, the device is fabricated without exposing it to the atmosphere. First, measurement is performed in a measurement chamber in a nitrogen atmosphere, then oxygen is introduced into the measurement chamber, stored for 2 days, measurement in an oxygen atmosphere, and further measurement chamber. After being opened to the atmosphere and stored for 2 days, measurements in the atmosphere were carried out to evaluate the stability against oxygen and atmospheric exposure.
ON current in the atmosphere: 6.5 mA, ON / OFF ratio 1210
FIG. 5 shows the transfer characteristic of the SIT characteristic of this element and the static output characteristic in the atmosphere.
The results are summarized in Table 1, including ON currents in the atmosphere and oxygen.
(In the table, the ON current and the ON / OFF ratio are both obtained from atmospheric transfer characteristics, and air / N 2 and O 2 / N 2 indicate the ratio of the ON current in each atmosphere.)
実施例２
実施例１で活性層を蒸着後、真空状態のままで基板温度を１時間かけて１００℃まで上昇させそのまま１時間放置し、アニールを行った。ゆっくりと室温に戻してから実施例１と同様に電荷注入層及びゲート電極を蒸着して素子を作成し、同様な評価を行った。
大気中でのＯＮ電流：２．３４ｍＡ、ＯＮ／ＯＦＦ比 ６２４０
Example 2
After vapor deposition of the active layer in Example 1, the substrate temperature was raised to 100 ° C. over 1 hour in a vacuum state, and the substrate was left as it was for 1 hour for annealing. After slowly returning to room temperature, a charge injection layer and a gate electrode were deposited in the same manner as in Example 1 to prepare a device, and the same evaluation was performed.
ON current in air: 2.34 mA, ON / OFF ratio 6240
実施例３
実施例１で活性層の蒸着時に基板温度を１００℃とし、冷却後に電荷注入層及びゲート電極を蒸着して素子を作成し、同様な評価を行った。
大気中でのＯＮ電流：１０．８ｍＡ、ＯＮ／ＯＦＦ比 ３８２０
Example 3
In Example 1, the substrate temperature was set to 100 ° C. during the deposition of the active layer, and after cooling, a charge injection layer and a gate electrode were deposited to prepare an element, and the same evaluation was performed.
ON current in the atmosphere: 10.8 mA, ON / OFF ratio 3820
比較例１
実施例１で用いた化合物（１０）の代わりに下記の化合物（１００）を用いて、同様の素子を作成し、評価を行った。
大気中でのＯＮ電流：０．１７ｍＡ、ＯＮ／ＯＦＦ比 １０１０
Comparative Example 1
Similar devices were prepared and evaluated using the following compound (100) instead of the compound (10) used in Example 1.
ON current in the atmosphere: 0.17 mA, ON / OFF ratio 1010
比較例２
実施例１で用いた化合物（１０）の代わりに活性層として銅フタロシアニン（１０１）３００ｎｍの膜厚にて製膜した。銅フタロシアニンの場合は高イオン化ポテンシャルではないため、電荷注入層は使用しない構造で、素子を作成し、評価を行った。
大気中でのＯＮ電流：２．０ｍＡ、ＯＮ／ＯＦＦ比 ８３
Comparative Example 2
Instead of the compound (10) used in Example 1, a film having a film thickness of copper phthalocyanine (101) of 300 nm was formed as an active layer. Since copper phthalocyanine does not have a high ionization potential, an element was prepared and evaluated with a structure in which no charge injection layer was used.
ON current in the atmosphere: 2.0 mA, ON / OFF ratio 83
比較例３
実施例１で用いた化合物（１０）の代わりに活性層としてペンタセン（１０２）２００ｎｍの膜厚にて製膜した。ペンタセンの場合は高イオン化ポテンシャルではないため、電荷注入層は使用しない構造で、素子を作成し、評価を行った。
大気中でのＯＮ電流：０．２５ｍＡ、ＯＮ／ＯＦＦ比 ７．８
Comparative Example 3
Instead of the compound (10) used in Example 1, a film of pentacene (102) having a thickness of 200 nm was formed as an active layer. In the case of pentacene, since the ionization potential is not high, an element was fabricated and evaluated with a structure that does not use a charge injection layer.
ON current in the atmosphere: 0.25 mA, ON / OFF ratio 7.8
本発明の半導体材料（１０）と従来の活性材料を比較すると、従来の活性材料であるDPh-BTBT（１００）、銅フタロシアニン（１０１）やペンタセン（１０２）に比べＯＮ電流に優れている。この系統の最高のＯＮ電流であった銅フタロシアニンよりも３倍以上の電流が流れており、高電流駆動が可能となった。ＯＮ／ＯＦＦ比に関しても銅フタロシアニン（１０１）やペンタセン（１０２）に比較して格段に向上しており、雰囲気安定性を確認する窒素中と酸素又は大気中のＯＮ電流変化が非常に少なく特性が大きく向上したことが明確になった。化合物（１）の基本骨格を持ち、両側のフェニル基が無い化合物（１００）はＯＮ／ＯＦＦ比にて化合物（１）に近い値を有しており、比較的、雰囲気安定性も高いが、ＯＮ電流値が４０分の１程度と実用的でなかった。これは基本骨格の両末端の置換基の効果により分子の配向と配列が縦型半導体デバイス用途に改善されたためだと考えられる。さらに実施例２及び３の様に活性層の蒸着後の熱処理又は蒸着中の基板加熱処理はデバイスのＯＮ／ＯＦＦ比を向上させることが分った。
この様に本発明の化合物を半導体材料に用いると、雰囲気安定性、高ＯＮ／ＯＦＦ比、高電流密度を兼ね備え実用的な縦型の有機半導体デバイスが得られることが明らかとなった。
When the semiconductor material (10) of the present invention is compared with the conventional active material, the ON current is superior to that of the conventional active material DPh-BTBT (100), copper phthalocyanine (101) and pentacene (102). Current more than three times that of copper phthalocyanine, which was the highest ON current of this system, flowed, and high current drive was possible. The ON / OFF ratio is also significantly improved compared to copper phthalocyanine (101) and pentacene (102), and there are very few ON current changes in nitrogen and oxygen or the atmosphere to confirm atmospheric stability. It became clear that it was greatly improved. The compound (100) having the basic skeleton of the compound (1) and having no phenyl groups on both sides has a value close to the compound (1) in the ON / OFF ratio, and has relatively high atmospheric stability. The ON current value was about 1/40 and not practical. This is thought to be because the orientation and alignment of molecules were improved for vertical semiconductor device applications due to the effects of substituents at both ends of the basic skeleton. Further, it was found that the heat treatment after the active layer deposition or the substrate heating treatment during the deposition as in Examples 2 and 3 improves the ON / OFF ratio of the device.
Thus, it has been clarified that when the compound of the present invention is used as a semiconductor material, a practical vertical organic semiconductor device having atmospheric stability, a high ON / OFF ratio, and a high current density can be obtained.
Claims (7)
（Ｒ１及びＲ２はそれぞれ独立に置換基を有してもよい芳香族基を表す。） A vertical organic semiconductor device comprising a compound represented by the general formula (1) as a semiconductor material.
(R 1 and R 2 each independently represents an aromatic group which may have a substituent.)
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