JP5820595B2 - 軟質回路用の耐応力性マイクロ・ビア構造 - Google Patents
軟質回路用の耐応力性マイクロ・ビア構造 Download PDFInfo
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- JP5820595B2 JP5820595B2 JP2011036498A JP2011036498A JP5820595B2 JP 5820595 B2 JP5820595 B2 JP 5820595B2 JP 2011036498 A JP2011036498 A JP 2011036498A JP 2011036498 A JP2011036498 A JP 2011036498A JP 5820595 B2 JP5820595 B2 JP 5820595B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Structure Of Printed Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
12 基材
14 複数のダイ・パッド
16 ピッチ
20 チップ・パッケージ
22 ポリイミド軟質層又は回路基板
23 接着剤層
24 複数のビア
26 金属層/材料
28 金属インタコネクト
30 上面
31 被覆パッド
32 付加的なポリイミド軟質層
34 底面部
36 側壁
38 柱状インタコネクト
40 ビア・ストリング故障率軸
42 底面/側壁厚み軸
Claims (10)
- 複数のダイ・パッド(14)を上面に形成した電子チップ(10)と、
該電子チップ(10)の上に配置された第1のポリイミド軟質層(22)であって、各々がそれぞれのダイ・パッド(14)に対応するような複数の第1のビア(24)を内部に形成した第1のポリイミド軟質層(22)と、
前記電子チップ(10)と前記第1のポリイミド軟質層(22)との間に付着させられた第1の接着剤層(23)と、
前記第1のポリイミド軟質層(22)の上面(30)の一部を被覆する第1の被覆パッド(31)を含み、前記第1のポリイミド軟質層(22)の上に形成された複数の第1の金属インタコネクト(28)と、
前記第1のポリイミド軟質層(22)の上に配置された第2のポリイミド軟質層(32)であって、各々がそれぞれの第1の被覆パッド(31)に対応するような複数の第2のビア(24)を内部に形成した第2のポリイミド軟質層(32)と、
前記第1のポリイミド軟質層(22)と前記第2のポリイミド軟質層(32)との間に付着させられた第2の接着剤層(23)と、
前記第2のポリイミド軟質層(32)の上面の一部を被覆する第2の被覆パッド(31)を含み、前記第2のポリイミド軟質層(32)の上に形成された複数の第2の金属インタコネクト(28)と、
を備えたチップ・パッケージ(20)であって、
前記複数の第1の金属インタコネクト(28)の各々が、
前記第1の被覆パッド(31)から下方に前記第1のビア(24)の周辺に沿って前記第1のビア(24)を通過して延在する第1の側壁(36)と、
該第1の側壁(36)に接続されて、それぞれのダイ・パッド(14)との電気的接続を形成する第1の底面(34)と
を含んでおり、
前記第1の底面及び前記第1の側壁の各々の厚みが前記第1の接着剤層(23)の厚みに等しいか又はこれよりも大きく、
前記複数の第2の金属インタコネクト(28)の各々が、
前記第2の被覆パッド(31)から下方に前記第2のビア(24)の周辺に沿って前記第2のビア(24)を通過して延在する第2の側壁(36)と、
該第2の側壁(36)に接続されて、それぞれの第1の被覆パッド(31)との電気的接続を形成する第2の底面(34)と
を含んでおり、
前記第2の底面及び前記第2の側壁の各々の厚みが前記第2の接着剤層(23)の厚みに等しいか又はこれよりも大きい、
チップ・パッケージ(20)。 - 前記第1及び/又は第2の底面(34)及び前記側第1及び/又は第2の壁(36)の各々の厚みは、それぞれの第1及び/又は第2のビア(24)の容積が前記第1及び/又は第2の金属インタコネクト(28)により充填されるような厚みである、請求項1に記載のチップ・パッケージ(20)。
- 前記第1及び/又は第2の金属インタコネクト(28)は柱状インタコネクト(38)を含んでいる、請求項2に記載のチップ・パッケージ(20)。
- 前記第1のポリイミド軟質層(22)は、前記電子チップ(10)を支持するように構成されている自立型フィルムを含んでいる、請求項1乃至3のいずれかに記載のチップ・パッケージ(20)。
- 前記第1及び/又は第2の接着剤層(23)の組成は、エポキシ系誘電材料と、エポキシ樹脂と、光酸発生剤と、酸化防止剤と、前記光酸発生剤に対応する常温触媒とを含んでいる、請求項1乃至4のいずれかに記載のチップ・パッケージ(20)。
- 前記第1及び/又は第2の接着剤層(23)の前記厚みは12マイクロメートル〜25マイクロメートルの範囲にある、請求項1乃至5のいずれかに記載のチップ・パッケージ(20)。
- 前記複数の第1及び/又は第2のビア(24)の各々の径は45マイクロメートル未満である、請求項1乃至6のいずれかに記載のチップ・パッケージ(20)。
- 前記第1及び/又は第2の被覆パッド(31)の厚みは前記第1及び/又は第2の底面(34)及び前記第1及び第2の側壁(36)の厚みよりも大きい、請求項7に記載のチップ・パッケージ(20)。
- 前記複数の第1及び/又は第2の金属インタコネクト(28)は、電気めっき法により前記第1及び/又は第2のポリイミド軟質層(22)の上に形成される、請求項1乃至8のいずれかに記載のチップ・パッケージ(20)。
- 前記電子チップ(10)は、伏せた配向で前記第1の接着剤層(23)を介して前記第1のポリイミド軟質層(22)に接着される、請求項1乃至9のいずれかに記載のチップ・パッケージ(20)。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/715,450 US10276486B2 (en) | 2010-03-02 | 2010-03-02 | Stress resistant micro-via structure for flexible circuits |
US12/715,450 | 2010-03-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011181923A JP2011181923A (ja) | 2011-09-15 |
JP5820595B2 true JP5820595B2 (ja) | 2015-11-24 |
Family
ID=44317930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011036498A Active JP5820595B2 (ja) | 2010-03-02 | 2011-02-23 | 軟質回路用の耐応力性マイクロ・ビア構造 |
Country Status (8)
Country | Link |
---|---|
US (1) | US10276486B2 (ja) |
EP (1) | EP2365523B1 (ja) |
JP (1) | JP5820595B2 (ja) |
KR (1) | KR101787753B1 (ja) |
CN (1) | CN102194776B (ja) |
BR (1) | BRPI1101788A2 (ja) |
SG (2) | SG173975A1 (ja) |
TW (1) | TWI515856B (ja) |
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CN103420330B (zh) * | 2013-09-09 | 2015-09-02 | 厦门大学 | 一种应用于微器件圆片级封装通孔金属互联的制作方法 |
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2010
- 2010-03-02 US US12/715,450 patent/US10276486B2/en active Active
-
2011
- 2011-02-21 SG SG2011012119A patent/SG173975A1/en unknown
- 2011-02-21 SG SG2013064605A patent/SG193826A1/en unknown
- 2011-02-23 JP JP2011036498A patent/JP5820595B2/ja active Active
- 2011-02-25 BR BRPI1101788-0A patent/BRPI1101788A2/pt not_active Application Discontinuation
- 2011-03-01 EP EP11156492.8A patent/EP2365523B1/en active Active
- 2011-03-02 TW TW100106957A patent/TWI515856B/zh active
- 2011-03-02 KR KR1020110018609A patent/KR101787753B1/ko active IP Right Grant
- 2011-03-02 CN CN201110059659.0A patent/CN102194776B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US10276486B2 (en) | 2019-04-30 |
SG173975A1 (en) | 2011-09-29 |
KR101787753B1 (ko) | 2017-10-18 |
TWI515856B (zh) | 2016-01-01 |
US20110215480A1 (en) | 2011-09-08 |
KR20110099658A (ko) | 2011-09-08 |
EP2365523B1 (en) | 2015-01-07 |
CN102194776A (zh) | 2011-09-21 |
CN102194776B (zh) | 2015-11-25 |
TW201218342A (en) | 2012-05-01 |
BRPI1101788A2 (pt) | 2012-07-31 |
SG193826A1 (en) | 2013-10-30 |
EP2365523A2 (en) | 2011-09-14 |
JP2011181923A (ja) | 2011-09-15 |
EP2365523A3 (en) | 2013-04-03 |
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