CN110391191A - 叠层封装结构 - Google Patents

叠层封装结构 Download PDF

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Publication number
CN110391191A
CN110391191A CN201810628042.8A CN201810628042A CN110391191A CN 110391191 A CN110391191 A CN 110391191A CN 201810628042 A CN201810628042 A CN 201810628042A CN 110391191 A CN110391191 A CN 110391191A
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CN
China
Prior art keywords
semiconductor devices
packaging part
encapsulating
packaging
underfill
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Pending
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CN201810628042.8A
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English (en)
Inventor
沈东翰
陈承先
刘国洲
郑锡圭
赖怡仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110391191A publication Critical patent/CN110391191A/zh
Pending legal-status Critical Current

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Abstract

本发明实施例提供一种叠层封装结构，包含：第一封装件、多个导电凸块、第二封装件以及底部填充胶。导电凸块设置在第一封装件的第二表面上且电连接到第一封装件。第二封装件通过导电凸块设置在第一封装件的第二表面上，且包含半导体器件以及包封半导体器件的包封材料。从包封材料的上部表面到半导体器件的上部表面的最短距离大于或大体上等于半导体器件的厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。

Description

叠层封装结构
技术领域
本发明实施例涉及一种叠层封装结构。
背景技术
随着对较小电子产品的需求增长，电子行业中的制造商等不断地寻求缩小电子产品中所用集成电路的尺寸的方法。为此，已研发并使用三维类型集成电路封装技术。
制造3D集成芯片需要堆叠多个半导体封装、在对应封装之间耦接电路以及用电绝缘粘着剂接合封装以形成叠层封装结构。例如使电绝缘粘着剂固化的后续高温处理步骤使叠层封装结构经受机械应力，其可引起非期望的副作用，例如翘曲、开裂、分层以及疵点形成。
发明内容
本发明实施例是针对一种叠层封装结构，其具有较高的成品良率。
根据本发明的实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。导电凸块设置在第一封装件的第二表面上且电连接到第一封装件。第二封装件通过导电凸块设置在第一封装件的第二表面上并包含半导体器件以及包封半导体器件的包封材料。从包封材料的上部表面到半导体器件的上部表面的最短距离大于或等于半导体器件的厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
根据本发明的实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。第一封装件包含包封的半导体器件以及重布线结构。包封的半导体器件包含第一半导体器件、包封第一半导体器件的第一包封材料以及延伸穿过第一包封材料的多个通孔。重布线结构设置在包封的半导体器件的第一表面上且电连接到包封的半导体器件。导电凸块设置在包封的半导体器件的第二表面上且电连接到包封的半导体器件。第二表面与第一表面相对。第二封装件设置在包封的半导体器件的第二表面上并包含第二半导体器件以及包封第二半导体器件的第二包封材料。从第二包封材料的上部表面到第二半导体器件的上部表面的最短距离大于或等于第二半导体器件的厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
根据本发明的实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。第一封装件包含包封的半导体器件以及重布线结构，所述重布线结构设置在包封的半导体器件的第一表面上且电连接到包封的半导体器件。导电凸块设置在包封的半导体器件的第二表面上且电连接到包封的半导体器件。第二封装件通过导电凸块设置在第二表面上并包含多个半导体器件以及包封半导体器件的包封材料。从包封材料的上部表面到半导体器件的最顶部表面的最短距离大于或等于半导体器件的最大厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本发明实施例的各方面。应注意，根据业界中的标准惯例，各个特征未按比例绘制。实际上，为论述清楚起见，可任意增大或减小各个特征的尺寸。
图1到图8说明根据本发明的一些示范性实施例的制造叠层封装结构中的中间阶段的横截面图。
图9描绘说明在指定温度下第二封装件的翘曲与底部填充胶失败率之间的关系的图。
图10描绘说明在另一指定温度下第二封装件的翘曲与底部填充胶失败率之间的关系的图。
图11说明根据本发明的一些示范性实施例的叠层封装结构的横截面图。
图12说明根据本发明的一些示范性实施例的叠层封装结构的横截面图。
附图标号说明
10、10'、10”：叠层封装结构；
100：第一封装件；
101：包封的半导体器件；
110、110a：第一半导体器件；
112：衬底；
113：接垫；
114：导通孔；
116、116a、143：介电层；
120、120a：第一包封材料；
130：通孔；
140、230：重布线结构；
142：重布线路；
144：凸块下金属层；
160：载体；
165：粘着剂层；
170、170a：绝缘层；
172：开口；
182：电连接件；
184：集成无源器件；
200、200'、200”：第二封装件；
201：下部表面；
210、210a、210b、210c：第二半导体器件；
212、222：上部表面；
212a、212b：顶部表面；
220、220’：第二包封材料；
300：导电凸块；
400：底部填充胶；
A1：中心区域；
A2：***区域；
D1、D2、T1、T1'：最短距离；
S1：第一表面；
S2：第二表面；
T2、T3、T4：厚度。
具体实施方式
以下揭露内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本发明实施例。当然，这些只是实例且并不意欲为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或上的形成可包含第一特征与第二特征直接接触地形成的实施例，并且还可包含额外特征可形成在第一特征与第二特征之间从而使得第一特征与第二特征可不直接接触的实施例。另外，本发明实施例可在各个实例中重复参考标号和/或字母。这种重复是出于简化和清楚的目的，且本身并不指示所论述的各种实施方案和/或配置之间的关系。
此外，为易于描述，本文中可使用例如“下方”、“在…下方”、“下部”、“在…上方”、“上部”以及其类似术语的空间相对术语以描述如图式中所示的一个元件或特征与另一元件或特征的关系。除图式中所描绘的定向以外，空间相对术语意欲涵盖器件在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词同样可相应地进行解释。
此外，为易于描述，在本文中可使用例如“第一”、“第二”、“第三”、“第四”以及其类似术语的术语以描述如图式中所示的相似或不同元件或特征，且可取决于存在次序或描述的上下文而互换使用。
还可包含其它特征和工艺。举例来说，可包含测试结构以帮助验证测试3D封装或3DIC器件。测试结构可包含例如形成在重布线层中或衬底上的测试垫，所述衬底允许测试3D封装或3DIC、使用探针和/或探针卡等等。验证测试可在中间结构和最终结构上执行。另外，本文中所公开的结构和方法可以与并有已知良好管芯的中间验证的测试方法结合使用以增加产量并降低成本。
图1到图8说明根据本发明的一些示范性实施例的制造叠层封装结构中的中间阶段的横截面图。应注意，将参照特定情形(即叠层封装(Package on Package；PoP)结构)下的一些实施例描述本发明实施例。然而，本发明实施例中的概念还可应用于其它半导体结构或电路。根据各种实施例提供PoP结构以及形成PoP结构的方法。根据一些实施例说明形成PoP结构的中间阶段。论述实施例的变化。贯穿各个视图和说明性实施例，相似参考标号用于表示相似元件。
在一些实施例中，形成如图8中所示PoP结构10的中间阶段的描述如下。参看图1，提供载体160，且粘着剂层165可设置在载体160上。在一些实施例中，载体160可以是玻璃载体、陶瓷载体或其类似物。粘着剂层165可以是光热转换释放涂层(light to heatconversion release coating；LTHC)或其类似物。在一些实施例中，绝缘层170a可选择性地设置在载体160上或在粘着剂层165(如果存在)上。随后，多个通孔130形成在载体160上，且通孔130围绕待设置第一半导体器件110的中心区域A1。在一些实施例中，通孔130设置在围绕中心区域A1的载体160的***区域A2上。应注意的是，本文中“中心”和“***”可不照字面地解释，而可视为空间上的相对术语，除图式中所描绘的定向以外，所述空间上的相对术语意欲涵盖器件在使用或操作中的不同定向。在本实施例中，通孔130形成在位于载体160上的绝缘层170a上，然而本发明实施例不限于此。在替代实施例中，可省略绝缘层170a和粘着剂层165，而通孔130则直接形成在载体160上。
在一些实施例中，至少一个如图2所示的第一半导体器件110a形成在载体160上且位于中心区域A1内。在本实施例中，第一半导体器件110a形成在位于载体160上的绝缘层170a上，然而本发明实施例不限于此。在一些实施例中，第一半导体器件110a可以是包含逻辑电路于其中的逻辑芯片。在一些示范性实施例中，第一半导体器件110a的数量可以是多个，且可以是为手机应用程序而设计的多个器件管芯(device dies)，且可包含例如电源管理集成电路(Power Management Integrated Circuit；PMIC)管芯和收发器(Transceiver；TRX)管芯。虽然仅示出一个第一半导体器件110a，但是更多的半导体器件可以被放置在载体160上方且彼此齐平。
在一些实施例中，载体160可包含以例如阵列方式配置的多个中心区域A1。相应地，通孔130可经形成以围绕每个中心区域A1，且多个第一半导体器件110a可分别设置在所述多个中心区域A1上，这样通孔130可围绕每个第一半导体器件110a。利用这些布置，可同时形成多个PoP结构。出于简洁和清楚起见，图1到图8中仅示出所述多个PoP结构中的一个的制造工艺。举例来说，图1中示出由所述多个通孔130中的一些围绕的所述多个中心区域A1中的一个。
在一些实施例中，通孔130可预先形成，且随后放置在载体160上。在替代实施例中，通孔130可由例如电镀工艺来形成。通孔130的电镀可在放置第一半导体器件110a之前执行，且可包含以下步骤。举例来说，首先形成晶种层(未绘示)在载体160上方、形成光刻胶层(未绘示)并对其进行图案化工艺以及在被光刻胶层暴露的部份晶种层上电镀而形成通孔130。光刻胶层以及由光刻胶层所覆盖的部份晶种层可随后被移除。第一半导体器件110a可随后放置在载体160上方。通孔130的材料可包含铜、铝或其类似物。相应地，通孔130的底端与第一半导体器件110a的背表面大体上齐平。
在一些示范性实施例中，多个导通孔114(例如铜通孔)可形成在第一半导体器件110a的有源表面(例如顶部表面)上且电耦接到第一半导体器件110a的衬底112上的接垫113。在一些实施例中，介电层116a可形成在第一半导体器件110a的有源表面(例如顶部表面)上，且可覆盖导通孔114的顶部表面。在其它实施例中，介电层116a的顶部表面可与导通孔114的顶部表面大体上齐平。或者，可省略介电层116a，且导通孔114从第一半导体器件110的有源表面突出。在一些实施例中，通孔130的顶端可与导通孔114的顶部表面大体上齐平。在其它实施例中，通孔130的顶端可大体上高于导通孔114的顶部表面。或者，通孔130的顶端可大体上低于导通孔114的顶部表面但是大体上高于导通孔114的底部表面。
随后，载体160上的第一半导体器件110a和通孔130由第一包封材料120a包封。换句话说，第一包封材料120a形成在载体160上以包封在***区域A2处的通孔130以及在中心区域A1处的第一半导体器件110a。在一些实施例中，第一包封材料120a填充在第一半导体器件110a与通孔130之间的间隙，且可与绝缘层170a接触。第一包封材料120a可包含模制化合物(molding compound)、环氧树脂或树脂等。在一些实施例中，第一包封材料120a的顶部表面可高于通孔130的顶端以及介电层116a的顶部表面。即第一包封材料120a覆盖通孔130的顶端以及介电层116a的顶部表面。
随后，执行薄化工艺(可以是研磨工艺)以薄化第一包封材料120a(以及介电层116a)直到显露通孔130的顶端以及导通孔114的顶部表面为止。所得结构绘示于图3中。由于薄化工艺，通孔130的顶端与导通孔114的顶部表面大体上齐平，且与第一包封材料120的顶部表面以及介电层116的顶部表面大体上齐平，如图3中所示。在整篇描述中，如图3中所示的包含第一半导体器件110、通孔130以及第一包封材料120的所得结构被称作包封的半导体器件101，其在工艺中可具有晶片形式。相应地，在包封的半导体器件101中，第一半导体器件110设置在中心区域A1处，通孔130在围绕中心区域A1的***区域A2处延伸穿过第一包封材料120，且第一包封材料120包封第一半导体器件110和通孔130。换句话说，第一包封材料120包封其中的第一半导体器件110，且通孔130延伸穿过第一包封材料120。
接下来参看图4，重布线结构140形成在包封的半导体器件101的第一表面S1上。重布线结构140电连接到包封的半导体器件101的第一半导体器件110和通孔130。在一些实施例中，重布线结构140形成在包封的半导体器件101上方以连接到第一半导体器件110的导通孔114以及通孔130。在一些实施例中，重布线结构140还可使导通孔114与通孔130互连。重布线结构140可由例如以下步骤而形成：沉积导电层、图案化导电层以形成重布线路142、以介电层143部分地覆盖重布线路142并填充重布线路142之间的间隙等。重布线路142的材料可包含金属或包含铝、铜、钨和/或其合金的金属合金。介电层143可由例如氧化物、氮化物、碳化物、碳氮化物、其组合和/或其多层的介电材料来形成。重布线路142形成在介电层143中且电连接到第一半导体器件110和通孔130。另外，凸块下金属(Under BumpMetallurgy；UBM)层144可由溅镀、蒸镀或无电电镀等而形成在重布线结构140上。
参看图5，根据一些示范性实施例，电连接件182中的至少一个以及至少一个集成无源器件(Integrated Passive Device；IPD)184设置在重布线路结构140上。电连接件182的形成可包含将焊料球放置在UBM层144上(或在重布线路结构140上)，并且随后回焊焊料球。在替代实施例中，电连接件182的形成可包含执行电镀工艺以在UBM层144上(或重布线路结构140上)形成焊料块，并且随后回焊焊料块。电连接件182还可包含导电柱，或具有焊料顶盖的导电柱，其也可通过电镀形成。集成无源器件184可使用例如薄膜和光刻工艺的标准晶片制造技术来制造，且可通过例如倒装芯片接合或引线接合(wire bonding)等来安装在重布线路结构140上。
随后参看图6，载体160可去除。在一些实施例中，通过使粘着剂层165失去粘着力或减小粘着力而使载体160脱离包封的半导体器件101和绝缘层170a(如果存在)。粘着剂层165可与载体160一起被去除。举例来说，可使粘着剂层165曝露于UV光下，使得粘着剂层165失去粘着力或减小粘着力，因而可从包封的半导体器件101上去除载体160和粘着剂层165。
在去除载体160之后，通孔130的底端显露出来。在所说明的结构中，通孔130的底端与第一半导体器件110的底部表面以及第一包封材料120的底部表面齐平。在省略绝缘层170a的实施例中，可执行研磨工艺以轻微地研磨第一半导体器件110的底部表面以及通孔130的底端。或者，可省略研磨工艺。
参看图7，在具有绝缘层170a的实施例中，可随后对绝缘层170a执行图案化工艺以形成多个开口172。如此，可形成具有多个开口172的绝缘层170。开口172分别位于通孔130上以显露通孔130的底端。在一些实施例中，开口172可由光刻工艺、激光钻孔工艺等来形成。相应地，所得结构是如图7中所示的第一封装件100。
参看图8，多个导电凸块300可形成在第一封装件100的包封的半导体器件101的第二表面S2上，以电连接到第一封装件100的通孔130。第二表面S2与第一表面S1相对。即重布线结构140与导电凸块300分别设置在包封的半导体器件101的两个相对表面S1、表面S2上。在一些实施例中，导电凸块300设置在绝缘层170的开口172中以连接到通孔130。在一些实施例中，导电凸块300设置在第二表面S2的***区域A2上且围绕中心区域A1，第一半导体器件110位于所述中心区域A1内。
随后，第二封装件200设置在第一封装件100上且通过导电凸块300电连接到通孔130。在一些实施例中，第二封装件200通过导电凸块300设置在包封的半导体器件101的第二表面S2上。第二封装件200以其下部表面201面向包封的半导体器件101的第二表面S2的方式安装在第一封装件100上。在一些实施例中，第二封装件200可以是封装件、器件管芯、无源器件和/或其类似物。在一些实施例中，叠层封装结构10可垂直地组合离散存储器(discrete memory)封装件和逻辑封装件，且可在例如动态随机存储器(Dynamic RandomAccess Memory；DRAM)和其它存储器的存储器中采用(employed)第二封装件200，然而本发明实施例不限于此。
随后，将底部填充胶400填充到在第一封装件100与第二封装件200之间的间隙中以增强导电凸块300的强度且因此增强整个叠层封装结构10的强度。在一些实施例中，底部填充胶400覆盖中心区域A1以及***区域A2，并包封导电凸块300。底部填充胶400可随后由热固化工艺来固化，且固化温度的范围可为约100℃到150℃。相应地，所得结构是如图8中所示的叠层封装结构10。
在一些实施例中，第二封装件200可由倒装芯片接合的方式来安装在第一封装件100上，且第二封装件200可包含设置在重布线结构230上的至少一个第二半导体器件210以及包封第二半导体器件210的第二包封材料220。在一些实施例中，重布线结构230可以是封装衬底。在其它实施例中，重布线结构230可以是与重布线结构140相似的重布线层(redistribution layer；RDL)，其由例如以下步骤来形成：沉积导电层、图案化导电层以形成重布线路、以介电层部分地覆盖重布线路以及填充在重布线路之间的间隙等。
一般来说，在接合工艺期间，如果第二半导体器件210、第二包封材料220以及重布线结构230具有不同的热膨胀(thermal expansion；CTE)系数，那么在加热封装件200以及冷却封装件200时产生不同的膨胀程度。不同程度的膨胀对焊料球连接件施加很大应力，其可引起第二封装件200的翘曲(warpage)。在叠层封装配置中包含倒装芯片封装时会产生额外的难题。在叠层封装结构10中，例如专用集成电路(application specific IC；ASIC)和存储器封装(例如动态随机存取存储器(Dynamic Random Access Memory；DRAM))的两个封装件100和200可以彼此堆叠的方式安装。举例来说，第二封装件200可大于第一封装件100，且可具有围绕其周围的导电凸块300阵列以形成到第一封装件100的连接。例如叠层封装结构10的配置会增加封装件翘曲的可能性。
相应地，在将底部填充胶400分配在具有翘曲轮廓的第一封装件100与第二封装件200之间时，底部填充胶400可能无法完全地填充间隙，这会导致在底部填充胶400内形成空隙。此外，随着高温固化，在底部填充胶400内的空隙将变大且迅速地成核而引起脱层(delamination)。因此，控制叠层封装结构10的翘曲轮廓是甚为重要的，以使底部填充胶400填充在第一封装件100与第二封装件200之间的间隙而没有空隙形成。
为获得在固化工艺期间封装件的翘曲度与底部填充胶400的失败率(例如开裂或脱层等)之间的关系而进行一系列实验，并可相应地计算出由第二封装件200的不同程度的翘曲造成的叠层封装结构10的底部填充胶400的失败率(failure rate)。为监测叠层封装结构10的翘曲，可采用共面性(co-planarity)测量工具，其可采用投影波纹技术(ShadowMoire'technique)来测量叠层封装结构10的共面性。当然，以下实验数据和条件仅出于说明的目的提供，且本发明实施例不限于此，而实际上涵盖作为本文所提供教示的结果而为相关的所有变化。
图9描绘说明在指定温度下第二封装件的翘曲与底部填充胶失败率之间的关系的图。图10描绘说明在另一指定温度下第二封装件的翘曲与底部填充胶失败率之间的关系的图。在图9中展示的实验中，叠层封装结构10暴露于100℃左右的指定温度以模拟底部填充胶400的固化工艺。已发现在第二封装件200的翘曲大体上等于或小于约-20微米时，底部填充胶400的失败率达到0％。另外，在第二封装件200呈凹形翘曲轮廓形式(即第二封装件200的翘曲为负值)时，底部填充胶400的失败率低于10％。
在图10中展示的实验中，叠层封装结构10暴露于150℃左右的指定温度以模拟底部填充胶400的固化工艺。相似地，已发现在第二封装件200的翘曲大体上等于或小于约-20微米时，底部填充胶400的失败率达到0％。另外，在第二封装件200呈凹形翘曲轮廓形式(即第二封装件200的翘曲为负值)时，底部填充胶400的失败率也低于10％。
有监于此，可将第二封装件200的翘曲轮廓控制为凹形翘曲轮廓以降低底部填充胶400的失败率。在实施方案中的一个中，第二封装件200的下部表面201朝向包封的半导体器件101的第二表面S2弯曲，且下部表面201是面向第二表面S2的表面。在一些实施例中，从第二表面S2的中心区域A1到第二封装件200的最短距离D1大体上小于从第二表面S2的***区域A2上的任何位置到第二封装件200的最短距离D2。也就是说，如图8中所绘示，第一封装件100与第二封装件200之间的距离(例如间隙宽度)从***区域A2到中心区域A1逐渐减小。举例来说，中心区域A1处的最短距离D1的范围大体上可介于30微米到60微米之间，而***区域A2处的最短距离D2的范围大体上可介于100微米到140微米之间。当然，实例中的数值范围仅出于说明的目的提供，且本发明实施例不限于所述实例，而实际上涵盖作为本文所提供教示的结果而为相关的所有变化。
为实现第二封装件200的凹形翘曲轮廓，从第二包封材料220的上部表面222到第二半导体器件210的上部表面212的最短距离T1大于或大体上等于第二半导体器件210的厚度T2的两倍(即T1≧2×T2)。通过这种配置，由于第二封装件200的组件之间的热膨胀失配(thermal expansion mismatch)，第二封装件200将在热工艺(thermal process)之后呈凹形翘曲轮廓形式，因此第一封装件100与第二封装件200之间的间隙宽度从***区域A2到中心区域A1逐渐减小。由此，在使底部填充胶400从***区域A2分配并流向中心区域A1时，底部填充胶400可由于毛细作用而轻易地填充中心区域A1处的间隙而没有空隙形成。
图11说明根据本发明的一些示范性实施例的叠层封装结构的横截面图。应注意，图11中绘示的叠层封装结构10'含有许多与先前图8所公开的叠层封装结构10相同或相似的特征。出于清楚和简化的目的，可省略相同或相似特征的细节描述，并且相同或相似参考标号指代相同或类似组件。如下描述图11中绘示的叠层封装结构10'与图8中绘示的叠层封装结构10之间的主要差异。
在一些实施例中，第二封装件200'包含设置在重布线结构230上的多个第二半导体器件210a、210b以及包封所述多个第二半导体器件210a、210b的第二包封材料220。在一些实施例中，重布线结构230可以是封装衬底。在其它实施例中，重布线结构230可以是与重布线结构140相似的重布线层(redistribution layer；RDL)。在一些实施例中，从第二包封材料220的上部表面222到所述多个第二半导体器件210a 210b的最顶部表面的最短距离T1大于或大体上等于所述多个第二半导体器件210a、210b的最大厚度的两倍。
在本实施例中，第二半导体器件210a、第二半导体器件210b以并排方式设置在重布线结构230上。第二半导体器件210a及第二半导体器件210b的厚度T2及厚度T3可相同。在这种情况下，从上部表面222到第二半导体器件210a或第二半导体器件210b中任一个的顶部表面212a或顶部表面212b的最短距离T1大于或大体上等于第二半导体器件210a或第二半导体器件210b中任一个的厚度T2或厚度T3的两倍。在其它实施例中，第二半导体器件210a的厚度T2及第二半导体器件210b的及厚度T3可不同。举例来说，第二半导体器件210a的厚度T2大于第二半导体器件210b的厚度T3。在这种情况下，从上部表面222到第二半导体器件210a的顶部表面212a的最短距离T1大于或大体上等于第二半导体器件210a的厚度T2的两倍。应注意，图11中示出两个第二半导体器件210a、210b，然而本发明实施例并不限制第二封装件200中的第二半导体器件210a、210b的配置和数量。
通过这种配置，第二封装件200'将在热工艺之后呈凹形翘曲轮廓形式，因此第一封装件100与第二封装件200'之间的间隙宽度从***区域A2到中心区域A1逐渐减小。由此，在使底部填充胶400从***区域A2分配且流向中心区域A1时，底部填充胶400可由于毛细作用而轻易地在中心区域A1上方流动，且填充第一封装件100与第二封装件200'之间的间隙而没有空隙形成。
图12说明根据本发明的一些示范性实施例的叠层封装结构的横截面图。应注意，图12中绘示的叠层封装结构10”含有许多与先前图8所公开的叠层封装结构10相同或相似的特征。出于清楚和简化的目的，可省略相同或相似特征的细节描述，并且相同或相似参考标号指代相同或类似组件。如下描述图12中绘示的叠层封装结构10”与图8中绘示的叠层封装结构10之间的主要差异。
在一些实施例中，第二封装件200”包含设置在重布线结构230上的多个第二半导体器件210a、210b、210c以及包封所述多个第二半导体器件210a、210b、210c的第二包封材料220'。在一些实施例中，重布线结构230可以是封装衬底。在其它实施例中，重布线结构230可以是与重布线结构140相似的重布线层(redistribution layer；RDL)。在一些实施例中，从第二包封材料220'的上部表面222到所述多个第二半导体器件210a、210b、210c中的最顶部表面的最短距离T1大于或大体上等于所述多个第二半导体器件210a、210b、210c中的最大厚度的两倍。
在本实施例中，第二半导体器件210b及第二半导体器件210c在重布线结构230上彼此堆叠，且第二半导体器件210a设置于第二半导体器件210b及第二半导体器件210c旁。第二半导体器件210a、第二半导体器件210b、第二半导体器件210c的厚度T2、厚度T3、厚度T4可相同。在这种情况下，从上部表面222到第二半导体器件210a、第二半导体器件210b及第二半导体器件210c中的最顶部表面212b的最短距离T1'大于或大体上等于第二半导体器件210a、第二半导体器件210b及第二半导体器件210c中任一个的厚度T2、厚度T3或厚度T4的两倍。在其它实施例中，第二半导体器件210a、第二半导体器件210b及第二半导体器件210c的厚度T2、厚度T3及厚度T4可不同。举例来说，第二半导体器件210b的厚度T3大于第二半导体器件210c的厚度T4。在这种情况下，从上部表面222到第二半导体器件210b的最顶部表面212b的最短距离T1'大于或大体上等于第二半导体器件210b的厚度T3的两倍(即如果T3≥T4，那么T1'≧2×T3)。在这种情况下，从上部表面222到第二半导体器件210a的顶部表面212a的距离T1也将大于或大体上等于厚度T2的两倍，这是因为厚度T3与厚度T4的总和大于厚度T2。当然，如果厚度T2大于厚度T3与厚度T4的总和，则从上部表面222到顶部表面212a的距离T1成为距离T1和距离T1'中的最短距离，那么最短距离T1在决定第二封装件200”的翘曲方面具有关键性。应注意，第二封装件200”中的第二半导体器件210a、第二半导体器件210b、第二半导体器件210c的配置和数量仅用于说明，且本发明实施例不限于此。
通过这种配置，第二封装件200”将在热工艺之后呈凹形翘曲轮廓形式，这意味着第一封装件100与第二封装件200”之间的间隙宽度从***区域A2到中心区域A1逐渐减小。由此，在使底部填充胶400从***区域A2分配且流向中心区域A1时，底部填充胶400可由于毛细作用而轻易地在中心区域A1上方流动，且填充第一封装件100与第二封装件200”之间的间隙而没有空隙形成。因此，本发明实施例中的叠层封装结构的良率(yield rates)明显提升。
基于以上论述，可见本发明实施例提供各种优势。然而，应理解，并非所有优势都必须在本文中论述，且其它实施例可提供不同优势，并且对于所有实施例并不需要特定优势。
根据本发明的一些实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。导电凸块设置在第一封装件的第二表面上且电连接到第一封装件。第二封装件通过导电凸块设置在第一封装件的第二表面上并包含半导体器件以及包封半导体器件的包封材料。从包封材料的上部表面到半导体器件的上部表面的最短距离大于或等于半导体器件的厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
根据本发明的一些实施例，所述多个导电凸块设置在所述第二表面的***区域上。
根据本发明的一些实施例，所述第二封装件的下部表面朝向所述第一封装件的所述第二表面弯曲，其中所述下部表面面向所述第二表面。
根据本发明的一些实施例，从所述第二表面的中心区域到所述第二封装件的最短距离小于从所述第二表面的***区域上的任何位置到所述第二封装件的最短距离。
根据本发明的一些实施例，从所述包封材料的上部表面到所述半导体器件的上部表面的最短距离大于或等于所述半导体器件的厚度的两倍。
根据本发明的一些实施例，所述第二封装件包括多个半导体器件以及包封所述多个半导体器件的所述包封材料。
根据本发明的一些实施例，从所述包封材料的上部表面到所述多个半导体器件的最顶部表面的最短距离大于或等于所述多个半导体器件的最大厚度的两倍。
根据本发明的一些实施例，所述底部填充胶覆盖所述第二表面的中心区域以及***区域，以及包封所述多个导电凸块。
根据本发明的一些实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。第一封装件包含包封的半导体器件以及重布线结构。包封的半导体器件包含第一半导体器件、包封第一半导体器件的第一包封材料以及延伸穿过第一包封材料的多个通孔。重布线结构设置在包封的半导体器件的第一表面上且电连接到包封的半导体器件。导电凸块设置在包封的半导体器件的第二表面上且电连接到包封的半导体器件。第二表面与第一表面相对。第二封装件设置在包封的半导体器件的第二表面上并包含第二半导体器件以及包封第二半导体器件的第二包封材料。从第二包封材料的上部表面到第二半导体器件的上部表面的最短距离大于或等于第二半导体器件的厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
根据本发明的一些实施例，从所述第二表面的中心区域到所述第二封装件的最短距离小于从所述第二表面的***区域上的任何位置到所述第二封装件的最短距离。
根据本发明的一些实施例，所述多个导电凸块设置在所述***区域上。
根据本发明的一些实施例，所述底部填充胶覆盖所述中心区域以及所述***区域，以及包封所述多个导电凸块。
根据本发明的一些实施例，所述第二半导体器件的数量是多个，以及所述第二包封材料包封所述多个第二半导体器件。
根据本发明的一些实施例，从所述第二包封材料的上部表面到所述多个第二半导体器件的最顶部表面的最短距离大于或等于所述多个第二半导体器件的最大厚度的两倍。
根据本发明的一些实施例，所述第二封装件的下部表面朝向所述第二表面弯曲。
根据本发明的一些实施例，叠层封装结构包含第一封装件、多个导电凸块、第二封装件以及底部填充胶。第一封装件包含包封的半导体器件以及重布线结构，所述重布线结构设置在包封的半导体器件的第一表面上且电连接到包封的半导体器件。导电凸块设置在包封的半导体器件的第二表面上且电连接到包封的半导体器件。第二封装件通过导电凸块设置在第二表面上并包含多个半导体器件以及包封半导体器件的包封材料。从包封材料的上部表面到半导体器件的最顶部表面的最短距离大于或等于半导体器件的最大厚度的两倍。底部填充胶填充在第一封装件与第二封装件之间。
根据本发明的一些实施例，从所述第二表面的中心区域到所述第二封装件的最短距离小于从所述第二表面的***区域上的任何位置到所述第二封装件的最短距离。
根据本发明的一些实施例，所述第二封装件的下部表面朝向所述第二表面弯曲。
根据本发明的一些实施例，所述多个半导体器件以并排方式布置。
根据本发明的一些实施例，所述多个半导体器件彼此堆叠。
前文概述若干实施例的特征，以使得本领域的技术人员可更好地理解本发明实施例的方面。本领域的技术人员应了解，其可以易于使用本发明实施例作为设计或修改用于进行本文中所介绍的实施例的相同目的和/或获得相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到，这些等效构造并不脱离本发明实施例的精神和范围，且本领域的技术人员可在不脱离本发明实施例的精神和范围的情况下在本文中进行各种改变、替代和更改。

Claims (1)

1.一种叠层封装结构，包括：
第一封装件；
多个导电凸块，设置在所述第一封装件的第二表面上以及电连接到所述第一封装件；
第二封装件，通过所述多个导电凸块设置在所述第一封装件的所述第二表面上并包括半导体器件以及包封所述半导体器件的包封材料，其中从所述包封材料的上部表面到所述半导体器件的上部表面的最短距离大于或等于所述半导体器件的厚度的两倍；以及
底部填充胶，填充在所述第一封装件与所述第二封装件之间。
CN201810628042.8A 2018-04-20 2018-06-19 叠层封装结构 Pending CN110391191A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594152A (zh) * 2021-07-12 2021-11-02 南京国博电子股份有限公司 一种大电流pmos管与驱动器三维集成模块

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10546845B2 (en) * 2018-04-20 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structure
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지
US20220352046A1 (en) * 2021-04-28 2022-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8183696B2 (en) * 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US8530277B2 (en) * 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US8610286B2 (en) * 2011-12-08 2013-12-17 Stats Chippac, Ltd. Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
JP5918664B2 (ja) * 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US20160351462A1 (en) * 2015-05-25 2016-12-01 Inotera Memories, Inc. Fan-out wafer level package and fabrication method thereof
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10546845B2 (en) * 2018-04-20 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594152A (zh) * 2021-07-12 2021-11-02 南京国博电子股份有限公司 一种大电流pmos管与驱动器三维集成模块
CN113594152B (zh) * 2021-07-12 2024-03-19 南京国博电子股份有限公司 一种大电流pmos管与驱动器三维集成模块

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