JP5818331B2 - Nウェル/pウェルストラップ構造 - Google Patents
Nウェル/pウェルストラップ構造 Download PDFInfo
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- JP5818331B2 JP5818331B2 JP2013523155A JP2013523155A JP5818331B2 JP 5818331 B2 JP5818331 B2 JP 5818331B2 JP 2013523155 A JP2013523155 A JP 2013523155A JP 2013523155 A JP2013523155 A JP 2013523155A JP 5818331 B2 JP5818331 B2 JP 5818331B2
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- 238000009792 diffusion process Methods 0.000 claims description 66
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Description
Claims (17)
- 半導体基板のN型又はP型ウェルと、
前記ウェルに形成される第1の能動素子と、
前記ウェルに形成され、前記能動素子から分離しているストラップと、
前記能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を備える集積回路構造であって、
前記ストラップは、複数のフローティング・ポリシリコンフィンガーの両側に第1及び第2の拡散領域と、前記複数のフローティング・ポリシリコンフィンガーの両側の前記第1及び第2の拡散領域のそれぞれに接続する前記第1及び第2の接続部とを備える集積回路構造。 - 前記能動素子は、MOSトランジスタである、請求項1に記載の集積回路構造。
- 複数の接続部は、前記第1の拡散領域に接続する、請求項1に記載の集積回路構造。
- 前記フローティング・ポリシリコンフィンガーは、平行である、請求項1に記載の集積回路構造。
- 前記ストラップの前記第1の能動素子から反対側で前記ウェルに形成される第2の能動素子と、
前記第2の能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を更に備える、請求項1に記載の集積回路構造。 - 前記第1の能動素子及び前記ストラップを取り囲むシャロートレンチアイソレーション領域を更に備える、請求項1に記載の集積回路構造。
- 半導体基板のN型又はP型ウェルと、
前記ウェルに形成される第1の能動素子と、
前記ウェルに形成され、前記能動素子から分離しているストラップと、
前記能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を備える集積回路構造であって、
前記ストラップは、フローティング・ポリシリコンフィンガーの両側の第1及び第2の拡散領域と、前記第1及び第2の拡散領域の一方に接続する少なくとも1つの接続部とを備え、前記第1及び第2の拡散領域の他方はフローティング状態である、集積回路構造。 - 前記能動素子は、MOSトランジスタである、請求項7に記載の集積回路構造。
- 複数の接続部は、前記第1及び第2の拡散領域の一方に接続する、請求項7に記載の集積回路構造。
- 前記第1及び第2の拡散領域は、複数のフローティング・ポリシリコンフィンガーの両側に配置される、請求項7に記載の集積回路構造。
- 前記ストラップの前記第1の能動素子から反対側で前記ウェルに形成される第2の能動素子と、
前記第2の能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を更に備える、請求項7に記載の集積回路構造。 - 前記能動素子及び前記ストラップを取り囲むシャロートレンチアイソレーション領域を更に備える、請求項7に記載の集積回路構造。
- 半導体基板のN型又はP型ウェルと、
前記ウェルに形成される第1の能動素子と、
前記ウェルに形成され、前記能動素子から分離しているストラップと、
前記能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を備える集積回路構造であって、
前記ストラップは、複数のフローティング・ポリシリコンフィンガーの両側の第1及び第2の拡散領域と、前記複数のフローティング・ポリシリコンフィンガーの両側の前記第1及び第2の拡散領域のそれぞれに接続する第1及び第2の接続部とを備える、集積回路構造。 - 前記能動素子は、MOSトランジスタである、請求項13に記載の集積回路構造。
- 複数の接続部は、前記第の拡散領域に接続する、請求項13に記載の集積回路構造。
- 前記ストラップの前記第1の能動素子から反対側で前記ウェルに形成される第2の能動素子と、
前記第2の能動素子と前記ストラップとの間の前記ウェル上に配置される単一のダミーポリシリコンフィンガーと、
を更に備える、請求項13に記載の集積回路構造。 - 前記能動素子及び前記ストラップを取り囲むシャロートレンチアイソレーション領域を更に備える、請求項13に記載の集積回路構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/851,805 | 2010-08-06 | ||
US12/851,805 US8217464B2 (en) | 2010-08-06 | 2010-08-06 | N-well/P-well strap structures |
PCT/US2011/001378 WO2012018398A1 (en) | 2010-08-06 | 2011-08-04 | N-well/p-well strap structures |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013535836A JP2013535836A (ja) | 2013-09-12 |
JP5818331B2 true JP5818331B2 (ja) | 2015-11-18 |
Family
ID=45555510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013523155A Expired - Fee Related JP5818331B2 (ja) | 2010-08-06 | 2011-08-04 | Nウェル/pウェルストラップ構造 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8217464B2 (ja) |
EP (1) | EP2601673A4 (ja) |
JP (1) | JP5818331B2 (ja) |
CN (1) | CN103180930B (ja) |
WO (1) | WO2012018398A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8217464B2 (en) | 2010-08-06 | 2012-07-10 | Altera Corporation | N-well/P-well strap structures |
US9449962B2 (en) * | 2010-08-06 | 2016-09-20 | Altera Corporation | N-well/P-well strap structures |
US8853833B2 (en) | 2011-06-13 | 2014-10-07 | Micron Technology, Inc. | Electromagnetic shield and associated methods |
US8350340B1 (en) * | 2011-08-05 | 2013-01-08 | Himax Technologies Limited | Structure of output stage |
US8735994B2 (en) * | 2012-03-27 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical-free dummy gate |
US20120261738A1 (en) * | 2012-06-29 | 2012-10-18 | Dustin Do | N-Well/P-Well Strap Structures |
US9070551B2 (en) * | 2013-06-18 | 2015-06-30 | Qualcomm Incorporated | Method and apparatus for a diffusion bridged cell library |
US9627529B1 (en) | 2015-05-21 | 2017-04-18 | Altera Corporation | Well-tap structures for analog matching transistor arrays |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6501138B1 (en) * | 1999-04-16 | 2002-12-31 | Seiko Epson Corporation | Semiconductor memory device and method for manufacturing the same |
JP2001118988A (ja) * | 1999-10-15 | 2001-04-27 | Mitsubishi Electric Corp | 半導体装置 |
JP4698793B2 (ja) * | 2000-04-03 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4118045B2 (ja) * | 2001-12-07 | 2008-07-16 | 富士通株式会社 | 半導体装置 |
US6788576B2 (en) * | 2002-10-28 | 2004-09-07 | Tower Semiconductor Ltd. | Complementary non-volatile memory cell |
US20050056881A1 (en) * | 2003-09-15 | 2005-03-17 | Yee-Chia Yeo | Dummy pattern for silicide gate electrode |
JP4599048B2 (ja) * | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク |
US7091565B2 (en) * | 2003-10-22 | 2006-08-15 | Marvell World Trade Ltd. | Efficient transistor structure |
US7234069B1 (en) * | 2004-03-12 | 2007-06-19 | Altera Corporation | Precise phase shifting using a DLL controlled, multi-stage delay chain |
US7176714B1 (en) * | 2004-05-27 | 2007-02-13 | Altera Corporation | Multiple data rate memory interface architecture |
JP4357409B2 (ja) * | 2004-12-17 | 2009-11-04 | 株式会社東芝 | 半導体集積回路装置及びその設計方法 |
JP2007012855A (ja) | 2005-06-30 | 2007-01-18 | Matsushita Electric Ind Co Ltd | 半導体集積回路、標準セル、標準セルライブラリ、半導体集積回路の設計方法および半導体集積回路の設計装置 |
US7586147B2 (en) * | 2006-04-17 | 2009-09-08 | Taiwan Semiconductor Manufacturing Co. Ltd. | Butted source contact and well strap |
GB2439759A (en) * | 2006-06-30 | 2008-01-09 | X Fab Uk Ltd | RF-CMOS transistor array |
US7679119B2 (en) | 2006-12-11 | 2010-03-16 | Tower Semiconductor Ltd. | CMOS inverter based logic memory |
KR101186033B1 (ko) * | 2009-09-30 | 2012-09-25 | 에스케이하이닉스 주식회사 | 반도체 기억 장치 및 그의 제조 방법 |
KR101593604B1 (ko) * | 2009-10-29 | 2016-02-12 | 삼성전자주식회사 | 전하 및 자외선(uv) 분석을 위한 장치 |
WO2011077664A1 (ja) * | 2009-12-25 | 2011-06-30 | パナソニック株式会社 | 半導体装置 |
US8217464B2 (en) | 2010-08-06 | 2012-07-10 | Altera Corporation | N-well/P-well strap structures |
-
2010
- 2010-08-06 US US12/851,805 patent/US8217464B2/en active Active
-
2011
- 2011-08-04 JP JP2013523155A patent/JP5818331B2/ja not_active Expired - Fee Related
- 2011-08-04 WO PCT/US2011/001378 patent/WO2012018398A1/en active Application Filing
- 2011-08-04 CN CN201180047562.6A patent/CN103180930B/zh active Active
- 2011-08-04 EP EP11814914.5A patent/EP2601673A4/en not_active Withdrawn
-
2016
- 2016-08-22 US US15/243,732 patent/US10043716B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2013535836A (ja) | 2013-09-12 |
US20120032276A1 (en) | 2012-02-09 |
CN103180930A (zh) | 2013-06-26 |
US10043716B2 (en) | 2018-08-07 |
US8217464B2 (en) | 2012-07-10 |
EP2601673A1 (en) | 2013-06-12 |
WO2012018398A1 (en) | 2012-02-09 |
CN103180930B (zh) | 2016-02-17 |
EP2601673A4 (en) | 2016-11-09 |
US20160358825A1 (en) | 2016-12-08 |
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