JP5692377B2 - 半導体ユニットおよび半導体装置 - Google Patents
半導体ユニットおよび半導体装置 Download PDFInfo
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- JP5692377B2 JP5692377B2 JP2013520502A JP2013520502A JP5692377B2 JP 5692377 B2 JP5692377 B2 JP 5692377B2 JP 2013520502 A JP2013520502 A JP 2013520502A JP 2013520502 A JP2013520502 A JP 2013520502A JP 5692377 B2 JP5692377 B2 JP 5692377B2
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- 241000784732 Lycaena phlaeas Species 0.000 description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
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- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
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Description
各チップを収納するケース75は、放熱体である銅ベース板61に接合し、このケース75上に前記の各端子(コレクタ端子C、エミッタ端子E、ゲート端子G)を露出させ、ケース75内には例えば図示しないゲルが充填されている。
<実施例1>
図1は、この発明の第1実施例の半導体ユニットの構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX1−X1線で切断した要部断面図である。図1(a)は、図1(b)のX2−X2線で切断した平面から矢印方向に見た模式的な要部平面図である。この半導体ユニット100は、炭化珪素半導体基板(SiC半導体基板)に形成されたダイオードチップ(以下、SiC−Diチップという)2を複数個、を並列接続した構造の半導体モジュールである。
この例では、第1共通銅板(第1の共通電極板)1上に4個のSiC−Diチップ2のカソード電極3を半田4で接合し、4個のSiC−Diチップ2のアノード電極5上にそれぞれヒートスプレッダとしての銅ブロック6を半田7で接合する。それぞれの銅ブロック6上に1つの第2共通銅板(第2の共通電極板)8を半田9で接合する。そして、第1共通銅板1のSiC−Diチップ2との接合面とは反対側の主面と、同じく第2共通銅板8の銅ブロック6との接合面とは反対側の面を露出させ、第1共通銅板1と第2共通銅板8で挟まれた領域、少なくともSiC−Diチップ2の端部2aを覆う領域をシリコーンゴムやエポキシ樹脂などの高耐熱樹脂10でモールドする。
<実施例2>
図2は、この発明の第2実施例の半導体ユニットの構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX3−X3線で切断した要部断面図である。図2(a)は、図2(b)のX4−X4線で切断した平面から矢印方向に見た模式的な要部平面図である。この半導体ユニット200は、SiC半導体基板に形成されたSiC−MOSFETチップ12を複数個、並列接続した構造の半導体モジュールである。
図2の半導体ユニット200と図1の半導体ユニット100の違いは、半導体チップとしてSiC−Diチップ2をSiC−MOSFETチップ12に置き換えた点である。また、第1共通銅板1の代わりに、図2に示すような補助導電パターン付き絶縁基板11を用いた点である。
<実施例3>
図3は、この発明の第3実施例の半導体装置の構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX5−X5線で切断した要部断面図である。図3(a)はケース44内の模式的な配置図である。
尚、このリボンワイヤ43の代わりに複数の銅線やアルミニウム線、あるいは単なる薄い銅板などの導体を用いても構わない。
また、半導体装置300は4個のSiC−Diチップ2のアノード電極5が銅ブロック6を介して第2共通銅板8に接続する構造であるため、4個のSiC−Diチップ2間のインダクタンスのばらつきが小さくなり、この4個のSiC−Diチップ2は均一な並列動作ができる。その結果、電流集中による半導体ユニット100の破壊が生じ難くなり、半導体装置300の信頼性が向上する。
<実施例4>
図4は、この発明の第4実施例の半導体装置の構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX6−X6線で切断した要部断面図である。図4(a)はケース57内の模式的な配置図である。
半導体ユニット200の共通銅板18と第7導電パターン54をフリキシブルな平板のリボンワイヤ55で接続する。また、半導体ユニット100の第2共通銅板8と第7導電パターン54をフリキシブルな平板のリボンワイヤ55で接続する。また、半導体ユニット200のゲート導体27を第8導電パターン56にワイヤ58で接続する。このゲート導体27と共通銅板18は、高耐熱樹脂28で電気的に絶縁されている。
尚、このリボンワイヤ55の代わりに複数の銅線やアルミニウム線、あるいは単なる薄い銅板などの導体を用いても構わない。
また、半導体ユニット100,200を用いることで、各チップ間でのインダクタンスのばらつきは小さくなり、各チップ間で均一な並列動作ができる。その結果、電流集中による半導体ユニット100,200の破壊が生じ難くなり半導体装置400の信頼性が向上する。
さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成および応用例に限定されるものではなく、対応するすべての変形例および均等物は、添付の請求項およびその均等物による本発明の範囲とみなされる。
2 SiC−Diチップ
2a,12a 端部
3 カソード電極
4,7,9,14,17,19 半田
5 アノード電極
6,16 銅ブロック
8 第2共通銅板
10,28 高耐熱樹脂
11 補助導電パターン付き絶縁基板
12 SiC−MOSFETチップ
13 ドレイン電極
15 ソース電極
18 共通銅板
20,33 裏面金属膜
21 第1導電パターン
22 絶縁基板
23 接続導体
24,40 ゲートパッド
25 第2導電パターン
26,39,42,58 ワイヤ
27 ゲート導体
31,51 銅ベース板
32,52 導電パターン付き絶縁基板
34 第3導電パターン
35 Si−IGBTチップ
36 コレクタ電極
37 エミッタ電極
38 第4導電パターン
41 第5導電パターン
43,55 リボンワイヤ
44,57 ケース
53 第6導電パターン
54 第7導電パターン
56 第8導電パターン
100,200 半導体ユニット
300,400 半導体装置
C コレクタ端子
E エミッタ端子
G ゲート端子
Claims (2)
- ワイドギャップ半導体基板を用いて形成される半導体チップを多数並列接続してなる半導体ユニットにおいて、
第1の共通導電板の第1の主面上に同一種の複数の前記半導体チップの一方の主面を接合し、前記半導体チップの他方の主面に導電ブロックをそれぞれ接合し、該複数の導電ブロック上に第2の共通導電板の第1の主面を接合し、前記第1の共通導電板の第2の主面と前記第2の共通導電板の第2の主面とを露出させ、前記第1の共通導電板の前記第1の主面と前記第2の共通導電板の前記第1の主面との間に絶縁樹脂を充填して一体化し、
前記半導体チップは、SiCスイッチングデバイスであり、前記一方の主面には第1主電極が形成され、前記他方の主面には第2主電極とゲート電極が形成され、前記第2の共通導電板とは絶縁されて前記第2の共通導電板の前記第2の主面側に導出される第3の導電板を備え、
前記第1主電極が前記第1の共通導電板の前記第1の主面に接合され、前記第2主電極が前記第2の共通導電板の前記第1の主面に前記導電ブロックを介して接合され、前記ゲート電極が前記第3の導電板に接続される、
ことを特徴とする半導体ユニット。 - ワイドギャップ半導体基板を用いて形成されるSiC−ダイオードチップを多数並列接続して内蔵する第1の半導体ユニットと、ワイドギャップ半導体基板を用いて形成されるSiCスイッチングデバイスを多数並列接続して内蔵する第2の半導体ユニットと、を共通の絶縁基板に搭載して接続する半導体装置であって、
第1の共通導電板の第1の主面上に同一種の複数の前記半導体チップの一方の主面を接合し、前記半導体チップの他方の主面に導電ブロックをそれぞれ接合し、該複数の導電ブロック上に第2の共通導電板の第1の主面を接合し、前記第1の共通導電板の第2の主面と前記第2の共通導電板の第2の主面とを露出させ、前記第1の共通導電板の前記第1の主面と前記第2の共通導電板の前記第1の主面との間に絶縁樹脂を充填して一体化し、
前記SiC−ダイオードチップは、
前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、
前記カソード電極が前記第1の共通導電板の前記第1の主面に接合され、
前記アノード電極が前記導電ブロックを介して前記第2の共通導電板の前記第1の主面に接合され、
前記SiCスイッチングデバイスは、前記一方の主面には第1主電極が形成され、前記他方の主面には第2主電極とゲート電極が形成され、前記第2の共通導電板とは絶縁されて前記第2の共通導電板の前記第2の主面側に導出される第3の導電板を備え、
前記第1主電極が前記第1の共通導電板の前記第1の主面に接合され、前記第2主電極が前記第2の共通導電板の前記第1の主面に前記導電ブロックを介して接合され、前記ゲート電極が前記第3の導電板に接続される、
ことを特徴とする半導体装置。
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