JP5571288B2 - ハブ装置、プリフェッチ・モードを選択するための方法、メモリ・システム及びメモリ・サブシステム - Google Patents
ハブ装置、プリフェッチ・モードを選択するための方法、メモリ・システム及びメモリ・サブシステム Download PDFInfo
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- JP5571288B2 JP5571288B2 JP2008014594A JP2008014594A JP5571288B2 JP 5571288 B2 JP5571288 B2 JP 5571288B2 JP 2008014594 A JP2008014594 A JP 2008014594A JP 2008014594 A JP2008014594 A JP 2008014594A JP 5571288 B2 JP5571288 B2 JP 5571288B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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Description
次の行アドレス=現在の行アドレス+(現在の行アドレス−以前の行アドレス)
509 メモリ装置
510 メモリ・コントローラ
604 リンク・インタフェース
606 読み取りデータ・キュー
607 読み取りデータ・セレクタ
610 書き込みデータ・セレクタ
611 書き込みデータ・キュー
615 メモリ装置データ・インタフェース
702 適応的プリフェッチ論理装置(APLU)
704 プリフェッチ・バッファ
706 入力コマンド・ストリーム・インタフェース
708 メモリ・ハブ装置
713 メモリ・ハブ制御
Claims (23)
- メモリ・ハブ装置であって、
前記メモリ・ハブ装置に接続された1つ以上のメモリ装置に向けられる、メモリ・コントローラからのコマンドを検出するための入力コマンド・ストリーム・インタフェースと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを独立的に分析するとともに、前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するための適応的プリフェッチ論理装置(APLU)であって、前記コマンドが前記メモリ・コントローラからの読み取りコマンドであることに応じて、前記プリフェッチ機能は、前記メモリ・コントローラからの前記読み取りコマンドよりも低い優先順位でプリフェッチ読み取りコマンドをディスパッチする、前記APLUと
を備えており、
前記分析は、前記アクセス・パターンに基づいて、前記メモリ・コントローラからの将来のコマンドの予想アドレスを予測することを含み、前記読み取りコマンドの現在のアドレスが前記予想アドレスと一致することに応じて、プリフェッチ可能化カウンタをインクリメントし、そして前記前記予測の正確性がプリフェッチ可能化しきい値以上である場合は、前記プリフェッチ機能を可能化し、一方、前記読み取りコマンドの現在のアドレスが前記予想アドレスと一致しないことに応じて、前記プリフェッチ可能化カウンタの値が0でないことを条件に当該プリフェッチ可能化カウンタをデクリメントし、そして前記予測の正確性がプリフェッチ不能化しきい値以下である場合は、前記プリフェッチ機能を不能化する、
前記メモリ・ハブ装置。 - 前記アクセス・パターンは、読み取りアクセス・パターンである、請求項1に記載のメモリ・ハブ装置。
- プリフェッチされたデータ及びアドレスを格納するために前記プリフェッチ機能によって利用されるプリフェッチ・バッファをさらに備える、請求項1又は2に記載のメモリ・ハブ装置。
- 書き込み動作中に、前記プリフェッチ・バッファ内でデータ・コヒーレンシが維持される、請求項3に記載のメモリ・ハブ装置。
- 前記分析及び前記選択は、前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される、請求項1〜4のいずれか一項に記載のメモリ・ハブ装置。
- 前記メモリ装置のうちの1つのメモリ装置に適用される前記分析及び前記選択は、前記メモリ装置のうちの他のメモリ装置に適用される前記分析及び前記選択とは独立している、請求項1〜5のいずれか一項に記載のメモリ・ハブ装置。
- 前記1つ以上のメモリ装置の1つのバンクに適用される前記分析及び前記選択は、当該1つ以上のメモリ装置内の他のバンクに適用される前記分析及び前記選択とは独立している、請求項1〜6のいずれか一項に記載のメモリ・ハブ装置。
- 前記分析及び前記選択は、前記メモリ装置の全てに適用される、請求項1〜7のいずれか一項に記載のメモリ・ハブ装置。
- 前記コマンドは、メモリ・コマンド・バッファ内にある保留中のコマンドを含む、請求項1〜8のいずれか一項に記載のメモリ・ハブ装置。
- 前記APLUは、将来のアクセス・パターンを変更するために前記メモリ・コマンド・バッファ内にある前記保留中のコマンドを再配列する、請求項9に記載のメモリ・ハブ装置。
- プリフェッチ・モードを選択するための方法であって、
ハブ装置に接続された1つ以上のメモリ装置に向けられる、メモリ・コントローラからのコマンドを検出するステップと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを分析するステップと、
前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するステップであって、前記コマンドが前記メモリ・コントローラからの読み取りコマンドであることに応じて、前記プリフェッチ機能は、前記メモリ・コントローラからの前記読み取りコマンドよりも低い優先順位でプリフェッチ読み取りコマンドをディスパッチする、前記選択するステップと
を含み、
前記分析するステップは、前記アクセス・パターンに基づいて、前記メモリ・コントローラからの将来のコマンドの予想アドレスを予測することを含み、前記読み取りコマンドの現在のアドレスが前記予想アドレスと一致することに応じて、プリフェッチ可能化カウンタをインクリメントし、そして前記前記予測の正確性がプリフェッチ可能化しきい値以上である場合は、前記プリフェッチ機能を可能化し、一方、前記読み取りコマンドの現在のアドレスが前記予想アドレスと一致しないことに応じて、前記プリフェッチ可能化カウンタの値が0でないことを条件に当該プリフェッチ可能化カウンタをデクリメントし、そして前記予測の正確性がプリフェッチ不能化しきい値以下である場合は、前記プリフェッチ機能を不能化する、
前記方法。 - 前記アクセス・パターンは、読み取りアクセス・パターンである、請求項11に記載の方法。
- 前記予測は、ストライドされたアドレスを検出及び予測するためのアルゴリズムを使用して行われる、請求項11に記載の方法。
- 前記プリフェッチ機能は、プリフェッチされたデータ及びアドレスをプリフェッチ・バッファ内に格納する、請求項11〜13のいずれか一項に記載の方法。
- 書き込み動作中に、前記プリフェッチ・バッファ内でデータ・コヒーレンシが維持される、請求項14に記載の方法。
- 前記分析するステップ及び前記選択するステップは、前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される、請求項11〜15のいずれか一項に記載の方法。
- 前記メモリ装置のうちの1つのメモリ装置に適用される前記分析するステップ及び前記選択するステップは、前記メモリ装置のうちの他のメモリ装置に適用される前記分析するステップ及び前記選択するステップとは独立している、請求項11〜16のいずれか一項に記載の方法。
- 前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される前記分析するステップ及び前記選択するステップは、当該1つのメモリ装置内の他のバンクに適用される前記分析するステップ及び前記選択するステップとは独立している、請求項11〜17のいずれか一項に記載の方法。
- 前記分析するステップ及び前記選択するステップは、前記メモリ装置の全てに適用される、請求項11〜18のいずれか一項に記載の方法。
- 前記コマンドは、メモリ・コマンド・バッファ内にある保留中のコマンドを含む、請求項11〜19のいずれか一項に記載の方法。
- 前記保留中のコマンドは、将来のアクセス・パターンを変更するために再配列される、請求項20に記載の方法。
- メモリ・システムであって、
メモリ・コントローラと、
1つ以上のメモリ装置と、
請求項1〜10のいずれか一項に記載のメモリ・ハブ装置であって、前記メモリ・コントローラ及び前記メモリ装置と通信関係にある前記メモリ・ハブ装置と
を備えている、前記メモリ・システム。 - メモリ・サブシステムであって、
1つ以上のメモリ装置と、
請求項1〜10のいずれか一項に記載のメモリ・ハブ装置と
を備えている、前記メモリ・サブシステム。
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US11/668,088 US7603526B2 (en) | 2007-01-29 | 2007-01-29 | Systems and methods for providing dynamic memory pre-fetch |
US11/668088 | 2007-01-29 |
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JP2008186457A JP2008186457A (ja) | 2008-08-14 |
JP5571288B2 true JP5571288B2 (ja) | 2014-08-13 |
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US20230027611A1 (en) * | 2021-07-26 | 2023-01-26 | Realtek Semiconductor Corporation | Power supply device, power supply system and non-transitory computer-readable recording medium |
US11991011B2 (en) * | 2021-07-26 | 2024-05-21 | Realtek Semiconductor Corporation | Power supply device, power supply system and non-transitory computer-readable recording medium |
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CN101236540B (zh) | 2011-07-20 |
US20080183903A1 (en) | 2008-07-31 |
CN101236540A (zh) | 2008-08-06 |
US7603526B2 (en) | 2009-10-13 |
JP2008186457A (ja) | 2008-08-14 |
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