JP2008186457A - ハブ装置、プリフェッチ・モードを選択するための方法、メモリ・システム及びメモリ・サブシステム - Google Patents
ハブ装置、プリフェッチ・モードを選択するための方法、メモリ・システム及びメモリ・サブシステム Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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Abstract
【解決手段】
ハブ装置は、入力コマンド・ストリーム・インタフェース及び適応的プリフェッチ論理装置(APLU)を含む。前記入力コマンド・ストリーム・インタフェースは、前記ハブ装置に接続された1つ以上のメモリ装置に向けられる、メモリ・コントローラからのコマンドを検出する。前記APLUは、前記メモリ装置に対するアクセス・パターンを決定するためにこれらのコマンドを独立的に分析するとともに、かかる分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択する。
【選択図】図7
Description
次の行アドレス=現在の行アドレス+(現在の行アドレス−以前の行アドレス)
509 メモリ装置
510 メモリ・コントローラ
604 リンク・インタフェース
606 読み取りデータ・キュー
607 読み取りデータ・セレクタ
610 書き込みデータ・セレクタ
611 書き込みデータ・キュー
615 メモリ装置データ・インタフェース
702 適応的プリフェッチ論理装置(APLU)
704 プリフェッチ・バッファ
706 入力コマンド・ストリーム・インタフェース
708 メモリ・ハブ装置
713 メモリ・ハブ制御
Claims (27)
- ハブ装置であって、
前記ハブ装置に接続された1つ以上のメモリ装置に向けられる、メモリ・コントローラからのコマンドを検出するための入力コマンド・ストリーム・インタフェースと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを独立的に分析するとともに、前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するための適応的プリフェッチ論理装置(APLU)とを備える、ハブ装置。 - 前記アクセス・パターンは、読み取りアクセス・パターンである、請求項1に記載のハブ装置。
- 前記分析は、前記アクセス・パターンに基づいて、前記メモリ・コントローラからの将来のコマンドの予想アドレスを予測することを含み、前記予測の正確性がプリフェッチ可能化しきい値以上である場合は、前記プリフェッチ機能が可能化され、前記予測の正確性がプリフェッチ不能化しきい値以下である場合は、前記プリフェッチ機能が不能化される、請求項1に記載のハブ装置。
- 前記プリフェッチ機能は、前記メモリ・コントローラからの読み取りコマンドよりも低い優先順位を有する、プリフェッチ読み取りコマンドをディスパッチする、請求項1に記載のハブ装置。
- プリフェッチされたデータ及びアドレスを格納するために前記プリフェッチ機能によって利用されるプリフェッチ・バッファをさらに備える、請求項1に記載のハブ装置。
- 書き込み動作中に、前記プリフェッチ・バッファ内でデータ・コヒーレンシが維持される、請求項5に記載のハブ装置。
- 前記分析及び前記選択は、前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される、請求項1に記載のハブ装置。
- 前記メモリ装置のうちの1つのメモリ装置に適用される前記分析及び前記選択は、前記メモリ装置のうちの他のメモリ装置に適用される前記分析及び前記選択とは独立している、請求項1に記載のハブ装置。
- 前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される前記分析及び前記選択は、当該1つのメモリ装置内の他のバンクに適用される前記分析及び前記選択とは独立している、請求項1に記載のハブ装置。
- 前記分析及び前記選択は、前記メモリ装置の全てに適用される、請求項1に記載のハブ装置。
- 前記コマンドは、メモリ・コマンド・バッファ内にある保留中のコマンドを含む、請求項1に記載のハブ装置。
- 前記APLUは、将来のアクセス・パターンを変更するために前記メモリ・コマンド・バッファ内にある前記保留中のコマンドを再配列する、請求項11に記載のハブ装置。
- プリフェッチ・モードを選択するための方法であって、
ハブ装置に接続された1つ以上のメモリ装置に向けられる、メモリ・コントローラからのコマンドを検出するステップと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを分析するステップと、
前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するステップとを含む、方法。 - 前記アクセス・パターンは、読み取りアクセス・パターンである、請求項13に記載の方法。
- 前記分析するステップは、前記アクセス・パターンに基づいて、前記メモリ・コントローラからの将来のコマンドの予想アドレスを予測することを含み、前記予測の正確性がプリフェッチ可能化しきい値以上である場合は、前記プリフェッチ機能が可能化され、前記予測の正確性がプリフェッチ不能化しきい値以下である場合は、前記プリフェッチ機能が不能化される、請求項13に記載の方法。
- 前記予測は、ストライドされたアドレスを検出及び予測するためのアルゴリズムを使用して行われる、請求項15に記載の方法。
- 前記プリフェッチ機能は、前記メモリ・コントローラからの読み取りコマンドよりも低い優先順位を有する、プリフェッチ読み取りコマンドをディスパッチする、請求項13に記載の方法。
- 前記プリフェッチ機能は、プリフェッチされたデータ及びアドレスをプリフェッチ・バッファ内に格納する、請求項13に記載の方法。
- 書き込み動作中に、前記プリフェッチ・バッファ内でデータ・コヒーレンシが維持される、請求項18に記載の方法。
- 前記分析するステップ及び前記選択するステップは、前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される、請求項13に記載の方法。
- 前記メモリ装置のうちの1つのメモリ装置に適用される前記分析するステップ及び前記選択するステップは、前記メモリ装置のうちの他のメモリ装置に適用される前記分析するステップ及び前記選択するステップとは独立している、請求項13に記載の方法。
- 前記メモリ装置のうちの1つのメモリ装置内の1つのバンクに適用される前記分析するステップ及び前記選択するステップは、当該1つのメモリ装置内の他のバンクに適用される前記分析するステップ及び前記選択するステップとは独立している、請求項13に記載の方法。
- 前記分析するステップ及び前記選択するステップは、前記メモリ装置の全てに適用される、請求項13に記載の方法。
- 前記コマンドは、メモリ・コマンド・バッファ内にある保留中のコマンドを含む、請求項13に記載の方法。
- 前記保留中のコマンドは、将来のアクセス・パターンを変更するために再配列される、請求項24に記載の方法。
- メモリ・システムであって、
メモリ・コントローラと、
1つ以上のメモリ装置と、
前記メモリ・コントローラ及び前記メモリ装置と通信関係にあるメモリ・ハブ装置とを備え、
前記メモリ・ハブ装置が、
前記メモリ装置に向けられる、前記メモリ・コントローラからのコマンドを検出するための入力コマンド・ストリーム・インタフェースと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを独立的に分析するとともに、前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するための適応的プリフェッチ論理装置(APLU)とを有する、メモリ・システム。 - メモリ・サブシステムであって、
1つ以上のメモリ装置と、
メモリ・ハブ装置とを備え、
前記メモリ・ハブ装置が、
前記メモリ装置に向けられる、メモリ・コントローラからのコマンドを検出するための入力コマンド・ストリーム・インタフェースと、
前記メモリ装置に対するアクセス・パターンを決定するために前記コマンドを独立的に分析するとともに、前記分析の結果に基づいて、前記メモリ装置用のプリフェッチ機能の可能化及び不能化のうち何れか一方を動的に選択するための適応的プリフェッチ論理装置(APLU)とを有する、メモリ・サブシステム。
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US11/668,088 US7603526B2 (en) | 2007-01-29 | 2007-01-29 | Systems and methods for providing dynamic memory pre-fetch |
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Also Published As
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US7603526B2 (en) | 2009-10-13 |
CN101236540A (zh) | 2008-08-06 |
CN101236540B (zh) | 2011-07-20 |
US20080183903A1 (en) | 2008-07-31 |
JP5571288B2 (ja) | 2014-08-13 |
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