JP5527958B2 - 電圧吸収エッジを有するpn接合を含むSiC半導体装置 - Google Patents
電圧吸収エッジを有するpn接合を含むSiC半導体装置 Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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Description
上に説明し、請求項で定義するJTEは、電荷密度2・1012cm−2までの両極性の表面電荷を扱うことができる。正の表面電荷の更に高い密度さえ(n形表面層に対して)許容できるが、JTE領域の電荷密度の再設計を要するだろう。そこで基本的にJTE領域のドーピングレベルを増さねばならないだろうが、それが、最高濃度にドープしたJTE領域の有効シート電荷密度である、固有シート電荷密度Q0を増加させ、ここで上記電荷密度Q0は、この接合を設計した電圧に依って選定しなければならない。
図1は、この発明によるJTEを有するSiC半導体装置の例を示す。この半導体は、SiCに作ったダイオードで例示する。図1の素子は、このダイオードのカソードをなす、高濃度にドープした(n+)、n導体の層1から成るSiCの基板上に作る。このn+導体層1の上部に、第1の低濃度にドープした(n−)、n導体の、層2を設ける。これら二つのn導体層1、2がSiC半導体材料の第1導体形式のウェーハを構成する。この低濃度にドープしたn導体層2の上部に、第2の高濃度にドープした、(p+)p導体層3が作るアノードをこのウェーハの表面に向けて配置し、それによってこのウェーハ表面の平面を確立する。接点6および7が、それぞれ、このダイオードのカソードおよびアノードに接触する。この第1層(n導体)と第2層(p導体)がpn接合を構成し、この第1のn導体の層2と第2のp導体の層3の間の界面を、ここで主接合と呼ぶ、このpn接合の作動範囲を形成し、それは、今まで説明した限りでは、接合終端延長部(JTE)を何も含まない。図1に、横方向に主接合の延長部を形成する、四領域JTEを備え、各領域4a〜4dが第2導体層3を囲み、この第2導体層3と同じ導体形式である、pn接合を示す。最外領域4dは、その端がこの接合の外側で終り、それでJTEの最外エッジ5を形成する。それぞれの領域4a〜4dの電荷量および/または有効シート電荷密度は、JTEエッジ5の方へ階段状に減少する。
SiCの基板上に形成する。これら二つのn導体層1、2が第1導体形式、この例によれば、n導体の平面ウェーハを構成し、その上にこの発明による一つ以上のpn接合を作ることができる。第2段階で、p導体の高濃度にドープした第2層3をイオン注入技術によってこのウェーハ上に作る。ここで、例えば、アルミニウム、硼素またはガリウムを注入剤として使用しうる。次の段階で、層3の延長部をマスキングおよびイオン注入によって形成する。図4dは、JTEを作る第1工程を示し、ここで予定するJTEを含むこの接合の全範囲に、最外領域の電荷量および/または有効シート電荷密度、この例では、領域4dの上記電荷を確立するために必要な量まで提案の形式のイオンを注入する。この注入工程中、ウェーハの表面の終端エッジ5の外側をマスク10によってマスクする。次の段階で、マスク10を延ばしてJTEの最外領域4dも覆い、そこでアノードおよび全ての被覆のないJTE領域を含む、露出した範囲の注入を、最外JTE領域に隣接する領域、この場合領域4cが上記領域の電荷量および/または有効シート電荷密度に達するために必要な量で実施する。この工程を図4cに示す。注入手順をこの様にして全てのJTE領域4a〜4dを注入するまで繰返し、この手順の工程を図4a〜図4dに示す。
Q1:Q2:Q3:Q4=100:75:50:25〜30
但し、Q1は、このJTEの最内領域の有効シート電荷密度を示し、Q2は、最内領域の次の領域の有効シート電荷密度を示す、以下同様とする。値100は、四領域実施例のJTEで最高のドーピング領域の電荷密度を示す。この値100は、この電荷密度を有する領域が全設計電圧で完全に消耗するようなドーピングにも対応する。この電荷密度は、固有電荷密度Q0と称し、C/cm2で表す。
三領域:Q1:Q2:Q3=100:(50〜85):(25〜60)
二領域:Q1:Q2=100:(40〜60)
一領域:Q1=(40〜70)
SiC半導体のpn接合を通り、上記接合のJTEの輪郭を示す放射状断面を図示する。このpn接合の構造は、図1に関して上に議論したのと同じ形式である。しかし、この場合は、JTEが異なる構造を有する。低濃度にドープしたn導体層2の上部に、第2の、高濃度にドープした、(p+)p導体層3によって作ったアノードを、このウェーハの表面に向けて配置し、それによってこのウェーハの平らな表面を作る。第1のn導体層2と第2の、p導体の、層3がpn接合を構成し、ここでこの第1のn導体の層2と第2のp導体の層3との間の界面がこのpn接合の作動範囲を形成する。このpn接合を囲むのが、このpn接合の層3と同じ導体形式である多数のスポット11を含むJTEである。これらのスポット11がもたらす、cm2当りの電荷で表す有効表面電荷密度は、pn接合からJTEのエッジ5まで外方に減少する。これは、異なる方法で達成することができる。これらのスポットの面積は、エッジの方へ次第に小さくなっていてもよく、またはもう一つの例のように、スポット間の距離がエッジ5の方へ次第に大きくなってもよく、スポット間の距離がエッジ5の方へ次第に大きくなってもよく、これらスポットの電荷量を変えることができ、またはこれらの異なる対策の組合せを適用することもできる。延ばした終端に沿って所望の平坦な電界分布を生ずる有効表面電荷プロフィールを近似する目的でとられた全ての対策が包含される。図6bは、このJTEプロフィール全体にわたる電界分布の例を示す。
Claims (3)
- 低濃度でドープした第1導体形式の第1層および該第1層の一部にある、高濃度にドープした第2導体形式の第2層を含み、該第1と第2導体形式層がpn接合を形成し、前記第2層のエッジが第2導体形式のエッジ終端部分を備える、平面構造の半導体素子において、該エッジ終端部分が、前記低濃度でドープした第1層内で互いに分離した複数の別々の区域を有する接合終端延長(JTE)領域を画成し、
前記複数の別々の区域は、前記接合終端延長領域が、該接合終端領域全体の横方向にわたって平坦な電界分布を示すように、該接合終端領域の外方エッジに向かって減少する総電荷またはcm 2 当たりの電荷に関する有効シート電荷密度を有することを特徴とする半導体素子。 - 前記別々の区域が前記接合終端延長領域の前記外方エッジに向かって減少する面積を有することを特徴とする、請求項1に記載の半導体素子。
- 前記別々の区域の隣接するもの間の距離が前記接合終端延長領域の前記外方エッジに向かって増加することを特徴とする、請求項2に記載の半導体素子。
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US08/683,059 US6002159A (en) | 1996-07-16 | 1996-07-16 | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
US08/683,059 | 1996-07-16 |
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JP10505911A Division JP2000516767A (ja) | 1996-07-16 | 1997-06-27 | 電圧吸収エッジを有するpn接合を含むSiC半導体装置 |
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JP2008263877A Expired - Lifetime JP5527958B2 (ja) | 1996-07-16 | 2008-10-10 | 電圧吸収エッジを有するpn接合を含むSiC半導体装置 |
JP2013000103A Pending JP2013062545A (ja) | 1996-07-16 | 2013-01-04 | 電圧吸収エッジを有するpn接合を含むSiC半導体コンポーネント |
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US (2) | US6002159A (ja) |
EP (1) | EP0912999B1 (ja) |
JP (3) | JP2000516767A (ja) |
DE (1) | DE69739522D1 (ja) |
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US6096663A (en) * | 1998-07-20 | 2000-08-01 | Philips Electronics North America Corporation | Method of forming a laterally-varying charge profile in silicon carbide substrate |
US6972436B2 (en) | 1998-08-28 | 2005-12-06 | Cree, Inc. | High voltage, high temperature capacitor and interconnection structures |
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US6002159A (en) | 1999-12-14 |
JP2013062545A (ja) | 2013-04-04 |
EP0912999A2 (en) | 1999-05-06 |
JP2009044177A (ja) | 2009-02-26 |
EP0912999B1 (en) | 2009-08-05 |
WO1998002924A2 (en) | 1998-01-22 |
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JP2000516767A (ja) | 2000-12-12 |
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