JP4186919B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4186919B2 JP4186919B2 JP2004353757A JP2004353757A JP4186919B2 JP 4186919 B2 JP4186919 B2 JP 4186919B2 JP 2004353757 A JP2004353757 A JP 2004353757A JP 2004353757 A JP2004353757 A JP 2004353757A JP 4186919 B2 JP4186919 B2 JP 4186919B2
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 239000012535 impurity Substances 0.000 claims description 74
- 239000000758 substrate Substances 0.000 claims description 17
- 230000005684 electric field Effects 0.000 description 29
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 17
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S388/00—Electricity: motor control systems
- Y10S388/907—Specific control circuit element or device
- Y10S388/917—Thyristor or scr
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
図1は本発明の実施の形態1に係る半導体装置の構造を示す断面図である。当該半導体装置は、SiC基板1に形成されたショットキ障壁ダイオードを備えている。即ち、n型のSiC基板1に同じくn型のSiCドリフト層2が形成され、その上面には、当該ドリフト層2とショットキ接続するアノード電極3(ショットキ電極)が形成される。ドリフト層2は、当該ダイオードが1000V程度の耐圧を実現できるよう、不純物濃度(ドーピング濃度)は2×1015〜12×1015cm-3に、厚さは5〜15μmに設定されている。ドリフト層2の上面の、アノード電極3が接しない領域には絶縁膜4が形成される。また、SiC基板の底面には当該ダイオードのカソード電極5が設けられる。
実施の形態1では、図1に示したように第1のp型領域6aと第2のp型領域6bとを、同じ厚さに形成した。そしてそれら各々の不純物濃度を調整することにより、第1のp型領域6aの不純物面濃度を1.8×1013〜4×1013cm-2に、第2のp型領域6bの不純物面濃度を1×1013〜2.5×1013cm-2に設定した。
先に述べたように、従来のJTE構造では、JTE領域を構成する複数のp型領域の境界、即ち、JTE領域内でチャージレベルが急激に変化する部分で電界集中が生じていた。本実施の形態では、JTE領域内部での電界集中の発生を抑制できるJTE構造を示す。
図7は、実施の形態4に係る半導体装置の構造を示す断面図である。同図においても、図1に示したものと同様の要素には、同一符号を付してある。
Claims (3)
- 半導体基板と、
前記半導体基板に形成されたn型SiCドリフト層と、
前記半導体基板上に形成され、前記n型SiCドリフト層にショットキ接続する電極と、
前記n型SiCドリフト層上部に形成され、前記電極の前記半導体基板に接する部分のエッジの下を含む領域に配設されたp型のJTE(Junction Termination Extension)領域とを備える半導体装置であって、
前記JTE領域は、
前記エッジに接続する第1のp型領域と、
前記第1のp型領域の外側に形成され、当該第1のp型領域よりも不純物面濃度が低い第2のp型領域のみから成り、
前記第2のp型領域は、前記エッジから15μm以上外側に配設されており、
前記第1のp型領域の不純物面濃度は、1.8×1013〜4×1013cm-2であり、
前記第2のp型領域の不純物面濃度は、1×1013〜2.5×1013cm-2である
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1のp型領域と前記第2のp型領域とは、厚さは互いに等しく、単位体積あたりの不純物濃度は第2のp型領域の方が低い
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1のp型領域と前記第2のp型領域とは、単位体積あたりの不純物濃度は互いに等しく、厚さは前記第2のp型領域の方が小さい
ことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004353757A JP4186919B2 (ja) | 2004-12-07 | 2004-12-07 | 半導体装置 |
US11/142,322 US7564072B2 (en) | 2004-12-07 | 2005-06-02 | Semiconductor device having junction termination extension |
CN200510082033A CN100590884C (zh) | 2004-12-07 | 2005-07-05 | 半导体器件 |
DE102005034871A DE102005034871A1 (de) | 2004-12-07 | 2005-07-26 | Halbleitervorrichtung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004353757A JP4186919B2 (ja) | 2004-12-07 | 2004-12-07 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008185860A Division JP2008252143A (ja) | 2008-07-17 | 2008-07-17 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2006165225A JP2006165225A (ja) | 2006-06-22 |
JP4186919B2 true JP4186919B2 (ja) | 2008-11-26 |
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ID=36441830
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JP2004353757A Active JP4186919B2 (ja) | 2004-12-07 | 2004-12-07 | 半導体装置 |
Country Status (4)
Country | Link |
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US (1) | US7564072B2 (ja) |
JP (1) | JP4186919B2 (ja) |
CN (1) | CN100590884C (ja) |
DE (1) | DE102005034871A1 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8026160B2 (en) * | 2005-09-08 | 2011-09-27 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor device manufacturing method |
JP4921880B2 (ja) * | 2006-07-28 | 2012-04-25 | 株式会社東芝 | 高耐圧半導体装置 |
JP5223773B2 (ja) | 2009-05-14 | 2013-06-26 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
JP5601849B2 (ja) * | 2010-02-09 | 2014-10-08 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
WO2012131878A1 (ja) * | 2011-03-28 | 2012-10-04 | トヨタ自動車株式会社 | 縦型半導体装置 |
JP5928101B2 (ja) | 2012-03-30 | 2016-06-01 | 富士電機株式会社 | SiC半導体デバイスの製造方法 |
JP6206862B2 (ja) * | 2012-05-31 | 2017-10-04 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP6384944B2 (ja) * | 2012-05-31 | 2018-09-05 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
CN105493293B (zh) * | 2013-09-09 | 2018-08-24 | 株式会社日立制作所 | 半导体装置及其制造方法 |
CN104134703A (zh) * | 2014-08-08 | 2014-11-05 | 上海安微电子有限公司 | 一种低漏电低正向压降肖特基二极管结构及其制备方法 |
WO2016059871A1 (ja) | 2014-10-15 | 2016-04-21 | 富士電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP6705155B2 (ja) | 2015-11-13 | 2020-06-03 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6672764B2 (ja) | 2015-12-16 | 2020-03-25 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6862782B2 (ja) | 2016-11-16 | 2021-04-21 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2018156987A (ja) | 2017-03-15 | 2018-10-04 | 住友電気工業株式会社 | 半導体装置 |
JP7087280B2 (ja) | 2017-05-31 | 2022-06-21 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
CN114023805A (zh) * | 2021-10-18 | 2022-02-08 | 西安电子科技大学 | 具有P型掺杂区和凹陷缓冲层的4H-SiC金属半导体场效应管 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US4927772A (en) | 1989-05-30 | 1990-05-22 | General Electric Company | Method of making high breakdown voltage semiconductor device |
US6002159A (en) * | 1996-07-16 | 1999-12-14 | Abb Research Ltd. | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
SE9700156D0 (sv) * | 1997-01-21 | 1997-01-21 | Abb Research Ltd | Junction termination for Si C Schottky diode |
SE512259C2 (sv) * | 1998-03-23 | 2000-02-21 | Abb Research Ltd | Halvledaranordning bestående av dopad kiselkarbid vilken innefattar en pn-övergång som uppvisar åtminstone en ihålig defekt och förfarande för dess framställning |
US6215168B1 (en) | 1999-07-21 | 2001-04-10 | Intersil Corporation | Doubly graded junction termination extension for edge passivation of semiconductor devices |
US6573128B1 (en) * | 2000-11-28 | 2003-06-03 | Cree, Inc. | Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same |
JP3873798B2 (ja) * | 2002-04-11 | 2007-01-24 | 富士電機デバイステクノロジー株式会社 | 炭化けい素半導体素子およびその製造方法 |
-
2004
- 2004-12-07 JP JP2004353757A patent/JP4186919B2/ja active Active
-
2005
- 2005-06-02 US US11/142,322 patent/US7564072B2/en active Active
- 2005-07-05 CN CN200510082033A patent/CN100590884C/zh active Active
- 2005-07-26 DE DE102005034871A patent/DE102005034871A1/de not_active Ceased
Also Published As
Publication number | Publication date |
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US7564072B2 (en) | 2009-07-21 |
DE102005034871A1 (de) | 2006-06-08 |
JP2006165225A (ja) | 2006-06-22 |
CN100590884C (zh) | 2010-02-17 |
CN1787228A (zh) | 2006-06-14 |
US20060118812A1 (en) | 2006-06-08 |
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