JP5470602B2 - 磁気記憶装置 - Google Patents
磁気記憶装置 Download PDFInfo
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- JP5470602B2 JP5470602B2 JP2009089207A JP2009089207A JP5470602B2 JP 5470602 B2 JP5470602 B2 JP 5470602B2 JP 2009089207 A JP2009089207 A JP 2009089207A JP 2009089207 A JP2009089207 A JP 2009089207A JP 5470602 B2 JP5470602 B2 JP 5470602B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/30—Technical effects
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- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Description
本発明の磁気記憶装置は、ダイと、第2および第3の磁気シールド構造と、リードフレーム部材とを有する。ダイは、基板と、第1および第2配線と、磁気記憶素子と、第1の磁気シールド構造とを有する。第1配線は、基板上に設けられ、一の方向に延びる部分を有する。第2配線は、基板上に設けられ、平面視において第1配線と交差し、かつ基板の厚み方向において第1配線と間隔を空けて配置されている。磁気記憶素子は、第1および第2配線が間隔を空けて互いに交差する領域において第1および第2配線に少なくとも一部が挟まれている。第1の磁気シールド構造は、平面視において磁気記憶素子を覆うように形成されている。第2および第3の磁気シールド構造は、厚み方向においてダイを挟んでいる。リードフレーム部材は、ダイが実装され、かつ強磁性体を含有する。リードフレーム部材は平面視においてダイの一部のみと重複している。
(メモリセルの回路と構造)
まず、本発明の実施の形態における磁気記憶装置に関し、磁気記憶装置のメモリセルの回路について説明する。
図2を参照して、半導体基板11におけるメモリセル領域MRでは、素子分離絶縁膜12によって区切られた素子形成領域の表面(半導体基板11の表面)に素子選択用トランジスタTRが形成されている。素子選択用トランジスタTRは、ドレイン領域Dと、ソース領域Sと、ゲート電極本体Gとを主に有している。ドレイン領域Dおよびソース領域Sは、互いに所定の距離を開け半導体基板11の表面に形成されている。ドレイン領域Dおよびソース領域Sは、互いに所定導電型の不純物領域から形成されている。ゲート電極本体Gは、ドレイン領域Dおよびソース領域Sに挟まれる領域上にゲート絶縁膜GIを介在して形成されている。ゲート電極本体Gの側壁は、サイドウォール状の側壁絶縁膜SIによって覆われている。
次に、メモリセルの動作について、図2に示す構造を例として説明する。
図4(A)および(B)を参照して、本実施の形態の磁気記憶装置100は、モールドパッケージ115(モールド構造)と、ダイパッド112と、リード111と、ワイヤ116と、上述のメモリセル構造を有するMRAMダイ110と、磁気シールド板113、114(第2および第3の磁気シールド構造)とで主に構成される。ダイパッド112とは、図5に示すリードフレーム部材において、MRAMダイ110が実装される部分である。
図7を参照して、半導体基板11の主表面における所定の領域に素子分離絶縁膜12を形成することによって、メモリセル領域MRおよび周辺回路領域RRが形成される。そのメモリセル領域MRおよび周辺回路領域RRに位置する半導体基板11の表面にゲート絶縁膜GIを介してゲート電極本体Gが形成される。そのゲート電極本体Gなどをマスクとして半導体基板11の表面に所定導電型の不純物を導入することにより、不純物領域からなるドレイン領域Dおよびソース領域Sと、1対のソース/ドレイン領域S/Dが形成される。こうして、メモリセル領域MRでは、ゲート電極G、ドレイン領域Dおよびソース領域Sを含む素子選択用トランジスタTRが形成され、周辺回路領域RRでは、論理回路を構成するトランジスタTRAが形成される。
図14を参照して、リードフレーム部材200が準備される。リードフレーム部材200は、図中V部(図5に対応)に示すダイパッド112およびダイパッド・サポート119と、リード111と、ダム・バー202と、外枠203とを有する。
上述した磁気記憶装置100(図4(B))では、ダイパッド112と磁気シールド板113を、それぞれ高飽和磁束密度、高透磁率特性を有する材料系で構成するとともに、ダイパッド112の大きさをMRAMダイ110よりも小さくした。そして、少なくともMRAMダイ110のメモリ領域部よりも大きいサイズの磁気シールド板114を、その平面形状において、長辺/短辺比を3以下とする形状に加工するとともに、モールドパッケージ115の材料との密着性を高めるテクスチャー加工を施してMRAMダイ110を挟むように配置した。さらに、MRAMダイの製造プロセスの中でも、磁気シールド層101を形成した。これらを適用することで、既存のモールドパッケージとの整合性が高く、8kA/m(100エルステッド)以上の強い擾乱磁界下であってもメモリセル領域MR(図2)に影響する磁界強度を地磁気レベルに低減できたため(図16)、情報の記録動作時における安定動作と、記録情報の安定保持が可能となる磁気記憶装置100を提供することができた。
Claims (15)
- ダイを備え、
前記ダイは、
基板と、
前記基板上に設けられ、一の方向に延びる部分を有する第1配線と、
前記基板上に設けられ、平面視において前記第1配線と交差し、かつ前記基板の厚み方向において前記第1配線と間隔を空けて配置された第2配線と、
前記第1および第2配線が前記間隔を空けて互いに交差する領域において前記第1および第2配線に少なくとも一部が挟まれた磁気記憶素子と、
平面視において前記磁気記憶素子を覆うように形成された第1の磁気シールド構造とを含み、さらに
厚み方向において前記ダイを挟む第2および第3の磁気シールド構造と、
前記ダイが実装され、かつ強磁性体を含有するリードフレーム部材とを備え、
前記リードフレーム部材は平面視において前記ダイの一部のみと重複しており、
前記第2および第3の磁気シールド構造のうち、一方の大きさは前記ダイの大きさより大きく、他方の大きさは前記ダイの大きさより小さいことを特徴とする、磁気記憶装置。 - 前記第2および第3の磁気シールド構造のうちの前記他方は、前記ダイのメモリセル領域部分のすべてを平面視において覆っている、請求項1に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の各々は前記ダイのメモリセル領域部分を全て覆い、かつ前記第2および第3の磁気シールド構造の各々の端部が前記メモリセル領域部分の端部と少なくとも0.3mmの距離をなす、請求項1に記載の磁気記憶装置。
- 前記リードフレーム部材のうち平面視において前記ダイと重複する部分は1.2テスラ以上の高飽和磁束密度材料からなり、前記第2および第3の磁気シールド構造との各々は、比透磁率5000以上の高透磁率材料からなる、請求項1に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の少なくともいずれかは、長辺および短辺を有する平面形状を有し、かつ前記長辺および前記短辺の比は3以下である、請求項1に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の少なくともいずれかは、モールド構造と接触し、かつ前記モールド構造との接触面において周期的な凸凹構造を有する、請求項1に記載の磁気記憶装置。
- 前記凸凹構造は、ドット状、矩形状および溝状のいずれかの形状を有する、請求項6に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の各々と、前記ダイとは、接着層を介して接続されている、請求項1に記載の磁気記憶装置。
- 前記接着層は強磁性材料を含んでいる、請求項8に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の少なくともいずれかは、平面視における端部において、前記ダイに対して遠ざかる方向に突出した凸部を有する、請求項1に記載の磁気記憶装置。
- 前記第2および第3の磁気シールド構造の間隔は、0.15mm以上0.5mm以下である、請求項1に記載の磁気記憶装置。
- 前記第1および第2配線の少なくともいずれかと、前記第1の磁気シールド構造との間隔は、100nm以下である、請求項1に記載の磁気記憶装置。
- 前記第1の磁気シールド構造は複数の部分に分割されており、前記複数の部分の各々は前記第1および第2配線のいずれかが延びる方向に延びている、請求項1に記載の磁気記憶装置。
- 前記磁気記憶素子は、磁化の方向が固定された固着層と、磁化容易軸を持つ記録層とを含み、
前記第1および第2配線に所定の電流を流すことで生じる磁界によって前記記録層の磁化方向を制御することによって情報が記録され、かつ前記情報は磁気抵抗効果によって読み出されるように構成された、請求項1に記載の磁気記憶装置。 - 前記磁気記憶素子は、磁化の方向が固定された固着層と、磁化容易軸を持つ記録層とを含み、
前記記録層にスピン偏極した電流を流すことによって生じるトルクをもって前記記録層の磁化方向を制御することによって情報が記録され、かつ前記情報は磁気抵抗効果によって読み出されるように構成された、請求項1に記載の磁気記憶装置。
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