JP5858335B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5858335B2 JP5858335B2 JP2012006347A JP2012006347A JP5858335B2 JP 5858335 B2 JP5858335 B2 JP 5858335B2 JP 2012006347 A JP2012006347 A JP 2012006347A JP 2012006347 A JP2012006347 A JP 2012006347A JP 5858335 B2 JP5858335 B2 JP 5858335B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- metal shield
- shield plate
- outer dimension
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Description
まず、図1を用いて、メタルシールド板の構成及び製造方法について説明する。メタルシールド板は、後述するように、半導体チップを外部の磁気から保護するために使用されるものである。
50 半導体装置
51 半導体チップ
51A 回路面
52 ダイパッド
54 リード
55 ボンディングワイヤ
56 封止樹脂
Claims (3)
- ダイパッド及びリードを有するリードフレームと、
前記ダイパッド上に設けられたメタルシールド板と、
前記メタルシールド板上に設けられ、ボンディングワイヤを介して前記リードに接続された半導体チップと、
前記リードフレーム、前記メタルシールド板、前記半導体チップ、及び前記ボンディングワイヤを封止する樹脂封止部と、
を備え、
前記メタルシールド板の外形寸法は前記半導体チップの外形寸法より大きく、前記メタルシールド板の周縁部が前記半導体チップ外方へ突出し、前記半導体チップの上面全域が前記樹脂封止部に直接接着することを特徴とする半導体装置。 - 前記メタルシールド板は、Fe−Ni合金を含む材料からなることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは磁気メモリを有することを特徴とする請求項1又は2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012006347A JP5858335B2 (ja) | 2012-01-16 | 2012-01-16 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012006347A JP5858335B2 (ja) | 2012-01-16 | 2012-01-16 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013145844A JP2013145844A (ja) | 2013-07-25 |
JP5858335B2 true JP5858335B2 (ja) | 2016-02-10 |
Family
ID=49041485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012006347A Active JP5858335B2 (ja) | 2012-01-16 | 2012-01-16 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5858335B2 (ja) |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3961914B2 (ja) * | 2002-09-05 | 2007-08-22 | 株式会社東芝 | 磁気メモリ装置 |
JP4096302B2 (ja) * | 2002-12-16 | 2008-06-04 | ソニー株式会社 | 磁気メモリ装置 |
JP2004221463A (ja) * | 2003-01-17 | 2004-08-05 | Sony Corp | 磁気メモリ装置 |
JP2005158985A (ja) * | 2003-11-26 | 2005-06-16 | Sony Corp | 磁気メモリ装置の実装構造及び実装基板 |
JP2005340237A (ja) * | 2004-05-24 | 2005-12-08 | Renesas Technology Corp | 磁気記憶装置 |
JP4941264B2 (ja) * | 2007-12-07 | 2012-05-30 | 大日本印刷株式会社 | 半導体装置用のメタルシールド板、メタルシールド用シート、半導体装置、メタルシールド用シートの製造方法、およびメタルシールド板の製造方法 |
JP5425461B2 (ja) * | 2008-12-26 | 2014-02-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5470602B2 (ja) * | 2009-04-01 | 2014-04-16 | ルネサスエレクトロニクス株式会社 | 磁気記憶装置 |
JPWO2011046091A1 (ja) * | 2009-10-13 | 2013-03-07 | 日本電気株式会社 | 磁性体装置 |
JP5354376B2 (ja) * | 2009-11-27 | 2013-11-27 | 大日本印刷株式会社 | 半導体装置および半導体装置の製造方法 |
JP5483281B2 (ja) * | 2010-03-31 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置アセンブリ |
JP2012109307A (ja) * | 2010-11-15 | 2012-06-07 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP2012182274A (ja) * | 2011-03-01 | 2012-09-20 | Nec Casio Mobile Communications Ltd | モジュール部品、その製造方法、及びそれが実装された半導体パッケージ、電子モジュール、または電子機器 |
-
2012
- 2012-01-16 JP JP2012006347A patent/JP5858335B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2013145844A (ja) | 2013-07-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7808089B2 (en) | Leadframe having die attach pad with delamination and crack-arresting features | |
JP5829562B2 (ja) | 半導体装置 | |
US9466784B2 (en) | Semiconductor device having multiple magnetic shield members | |
JP5227501B2 (ja) | スタックダイパッケージ及びそれを製造する方法 | |
TWI464851B (zh) | 包含嵌入式倒裝晶片之半導體晶粒封裝體 | |
JP5924110B2 (ja) | 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 | |
KR101563911B1 (ko) | 반도체 패키지 | |
JP4146290B2 (ja) | 半導体装置 | |
US7851902B2 (en) | Resin-sealed semiconductor device, manufacturing method thereof, base material for the semiconductor device, and layered and resin-sealed semiconductor device | |
JP2008532277A (ja) | 改良したボンディングパッド接続部を備える集積回路パッケージ装置、リードフレームおよび電子装置 | |
JP2002134685A (ja) | 集積回路装置 | |
TW201347135A (zh) | 線路板 | |
JP6411249B2 (ja) | 半導体装置 | |
JP5858335B2 (ja) | 半導体装置 | |
CN104916599A (zh) | 芯片封装方法和芯片封装结构 | |
JP5154275B2 (ja) | 磁気センサパッケージ | |
KR20110123505A (ko) | 반도체 패키지 | |
JP6220282B2 (ja) | 半導体装置 | |
JP2005327967A (ja) | 半導体装置 | |
JP2013030568A (ja) | 半導体装置 | |
JP4466341B2 (ja) | 半導体装置及びその製造方法、並びにリードフレーム | |
JP5553960B2 (ja) | 半導体装置及びその製造方法 | |
KR20010073946A (ko) | 딤플 방식의 측면 패드가 구비된 반도체 소자 및 그제조방법 | |
CN205752156U (zh) | 一种ic黑陶瓷低熔玻璃外壳覆铝引线框架 | |
JP4275109B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141120 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150722 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150728 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150918 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151120 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151203 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5858335 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D02 |