JP5430338B2 - ディッシング効果を低減する接合パッドの設計 - Google Patents
ディッシング効果を低減する接合パッドの設計 Download PDFInfo
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- JP5430338B2 JP5430338B2 JP2009238342A JP2009238342A JP5430338B2 JP 5430338 B2 JP5430338 B2 JP 5430338B2 JP 2009238342 A JP2009238342 A JP 2009238342A JP 2009238342 A JP2009238342 A JP 2009238342A JP 5430338 B2 JP5430338 B2 JP 5430338B2
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- patterned
- bond pad
- portions
- pad
- integrated circuit
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- 239000010703 silicon Substances 0.000 claims description 35
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
第2面と、第2面を介して露出且つ突出され、直接接合によって前記第1パターン化接合パッドに接合される第2接合パッドを含み、第2面を介して露出すると共に、前記中実の接合パッドに接続された付加の中実の接合パッドと、第1パターン化接合パッドが、複数の部分に電気的に相互接続された複数の配線を含み、複数の配線は複数の部分と同じ層にある、第2半導体チップ、を含んでいる。
一般的に、本発明の実施例は、改善された半導体チップの接合パッド構造を提供する。本発明の実施例は、局部のパターン密度を減少するために、好ましくは、接合パッドの中にスロット/開口を有するように設計されている。これは、ディッシング効果を最小限に抑えるのに有利である。例えば、直接的な金属−金属接合(しばしば銅直接接合として知られる)の技術背景において用いられることができる、本発明のいくつかの実施例がここに記述されるが、本発明の実施例は、その他の技術背景においても用いられることができる。
4、8 大型接合パッド
10、110 半導体チップ
20 半導体基板
24 相互接続構造
26 誘電体層
30、30’ 金属線
32、32’ ビア
40、50、501、502、503 シリコン貫通ビア
42、52、62、72、152 接合パッド
521 部分
522 配線部分
53 開口
64、74 再分配線
Claims (9)
- 集積回路構造であって、
第1面、
前記第1面を介して露出且つ突出される第1パターン化接合パッドであって、この第1パターン化接合パッドは、互いに電気的接続された複数の部分を含み、且つ第1パターン化接合パッドは、その中に少なくとも1つの開口を含むこと、及び
前記少なくとも1つの開口の少なくとも1つの部分の中に充填された誘電材料を含み、
前記第1パターン化接合パッドと同じレベルにあると共に、電気的に切断さえれており、前記第1パターン化接合パッドより小さい中実の(solid)接合パッドを有し、
前記第1パターン化接合パッドは、複数の部分に電気的に相互接続された複数の配線を含み、前記複数の配線は、前記複数の部分と同じ層にある第1半導体チップを含む集積回路構造。 - 前記複数の部分は、分離しており、前記集積回路構造は、前記複数の部分に電気的に相互接続された配線を更に含み、前記配線は、前記複数の部分と異なる層にある請求項1に記載の集積回路構造。
- 前記第1半導体チップにあるシリコン貫通ビアであって、このシリコン貫通ビアが前記第1パターン化接合パッドに接続されること、及び
前記第1パターン化接合パッドでなく、前記第1半導体チップの反対側にある付加的パターン化接合パッドであって、この付加的パターン化接合パッドは、前記シリコン貫通ビアに電気的接続することを更に含む請求項1に記載の集積回路構造。 - 前記付加的パターン化接合パッドは、互いに電気的接続された複数の付加の部分を含み、前記集積回路構造は、前記シリコン貫通ビアに隣接する付加のシリコン貫通ビアを更に含み、各前記シリコン貫通ビアと前記付加のシリコン貫通ビアは、前記第1パターン化接合パッドの前記複数の部分の1つを前記付加的パターン化接合パッドの前記複数の付加部分の1つに接続する請求項3に記載の集積回路構造。
- 集積回路構造であって、
第2面、及び
前記第2面を介して露出された第2パターン化接合パッドであって、この第2パターン化接合パッドは、互いに電気的接続された複数の付加部分を含み、且つ第2パターン化接合パッドは、その中に少なくとも1つの開口を含み、前記第1パターン化接合パッドが直接接合によってそれに接合されることを含む第2半導体チップを含む請求項1に記載の集積回路構造。 - 集積回路構造であって、
第1面、
前記第1面を介して露出且つ突出される第1パターン化接合パッドであって、この第1パターン化接合パッドは、複数の部分と、前記複数の部分間の複数の開口を含むこと、
前記第1パターン化接合パッドの前記複数の部分に接続した接続構造、
前記第1パターン化接合パッドの下方の半導体基板、
前記半導体基板にあり、前記第1パターン化接合パッドに電気的接続されたシリコン貫通ビア、及び
前記第1面を介して露出且つ突出される中実の接合パッドであって、この中実の接合パッドは、前記第1パターン化接合パッドより小さいことを含み、前記第1パターン化接合パッドは、複数の部分に電気的に相互接続された複数の配線を含み、前記複数の配線は、前記複数の部分と同じ層にある半導体チップを、備えた集積回路構造。 - 前記第1面に相対する第2面、及び
前記第2面を介して露出される第2パターン化接合パッドであって、この第2パターン化接合パッドは、互いに電気的接続された複数の付加部分を含むこと、及び
前記半導体基板にあり、前記シリコン貫通ビアに隣接する付加のシリコン貫通ビアを含み、各前記シリコン貫通ビアと前記付加のシリコン貫通ビアは、前記第1パターン化接合パッドの前記複数の部分の1つを前記第2パターン化接合パッドの前記複数の付加部分の1つに接続する請求項6に記載の集積回路構造。 - 集積回路構造であって、
第1面と、前記第1面を介して露出且つ突出される第1パターン化接合パッドであって、この第1パターン化接合パッドは、複数の部分と、前記複数の部分間の複数の開口を含む第1パターン化接合パッドと、前記第1面を介して露出すると共に、前記第1パターン化接合パッドから電気的に切断されており、前記第1パターン化接合パッドより小さい中実の接合パッドとを含む第1半導体チップ、及び
第2面と、前記第2面を介して露出且つ突出され、直接接合によって前記第1パターン化接合パッドに接合される第2接合パッドと、前記第2面を介して露出すると共に、前記
中実の接合パッドに接続された付加の中実の接合パッドと、前記第1パターン化接合パッドが、前記複数の部分に電気的に相互接続された複数の配線と、前記複数の配線は複数の部分と同じ層にある、第2半導体チップ、を含む集積回路構造。 - 前記第1半導体チップにあり、前記第1パターン化接合パッドでなく、前記第1半導体チップの反対側にある第2パターン化接合パッド、及び
前記半導体チップにある複数のシリコン貫通ビアであって、これら複数のシリコン貫通ビアのそれぞれが前記第1パターン化接合パッドの前記複数の部分の1つを前記第2パターン化接合パッドの複数の付加部分の1つに接続することを更に含む請求項8に記載の集積回路構造。
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US12/255,060 US8053900B2 (en) | 2008-10-21 | 2008-10-21 | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
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US8053900B2 (en) | 2011-11-08 |
KR101107806B1 (ko) | 2012-01-25 |
CN101728371A (zh) | 2010-06-09 |
JP2010103533A (ja) | 2010-05-06 |
CN101728371B (zh) | 2014-03-12 |
KR20100044100A (ko) | 2010-04-29 |
TW201017847A (en) | 2010-05-01 |
US20100096760A1 (en) | 2010-04-22 |
TWI399842B (zh) | 2013-06-21 |
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