JP5271985B2 - 集積回路構造 - Google Patents

集積回路構造 Download PDF

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Publication number
JP5271985B2
JP5271985B2 JP2010211576A JP2010211576A JP5271985B2 JP 5271985 B2 JP5271985 B2 JP 5271985B2 JP 2010211576 A JP2010211576 A JP 2010211576A JP 2010211576 A JP2010211576 A JP 2010211576A JP 5271985 B2 JP5271985 B2 JP 5271985B2
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metal
integrated circuit
circuit structure
semiconductor substrate
tsv
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JP2011071516A (ja
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明發 陳
文智 邱
曉林 ▲すい▼
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Description

本発明は、集積回路構造に関するものであって、特に、ウェハ背面に形成され、導電ビアであるスルーサブストレートビア（through-substrate via（ＴＳＶ））に接続される相互接続に関するものである。
各種電子素子（例えば、トランジスタ、ダイオード、レジスタ、キャパシタ等）の集積密度の不断の改善により、集積回路の製造、及び、半導体工業は、急速に成長を続けている。集積密度の改善は、多くが、最小形状寸法の縮小化を重ねてきたことによるもので、与えられたチップ領域内に、より多くの素子を集積することを可能にした。
これらの集積化の改善は、二次元（two-dimensional、２D）上の進歩であり、集積素子が占める体積は、実質上、半導体ウェハの表面上である。リソグラフィの劇的な改善は、既に、二次元の集積回路形成において、大幅な改善をもたらしているが、二次元で達成できる集積密度は、物理的限界がある。これらの限界の一つは、これらの素子の製造に必要な最小寸法があること、並びに、更に多くのデバイスを一チップ内に配置する時に、更に複雑な設計が必要なことである。
もう一つの限界は、デバイス数量の増加に伴い、デバイス間の相互接続（interconnection）の長さや数量も大幅に増加することである。相互接続の長さや数量が増加する場合、回路のＲＣ遅延、及び、電力消耗も増加する。
現在、上述の限界を解決する方法として、通常、３次元の集積回路（three-dimensional integrated circuit 、3D IC)、及び、スタックダイを用いる。３次元の集積回路とスタックダイ中に、スルーサブストレートビア（through-substrate via、ＴＳＶ)を使用して、ダイを接続する。この例では、ＴＳＶを使用して、ダイ上の集積回路を、このダイの背面に接続する。また、ＴＳＶは、短い接地経路を提供して、集積回路をこのダイの背面から接地し、接地金属膜により被覆される。
ＴＳＶを備えるチップの接合は、ＴＳＶ間で大きいピッチを必要とするので、ＴＳＶの位置は制限される。また、ＴＳＶ間の距離は、例えば、ソルダーボールを収容するのに十分な空間を必要とする。更に、現行のウェハ背面構造の形成方法において、ＴＳＶの電気的接続を、それぞれのＴＳＶから離すのは不可能である。
本発明は、ＴＳＶに接続されるウェハ背部の相互接続構造を提供し、上述の問題を改善することを目的とする。
本発明の第１の態様は、集積回路構造であって、正面と背面を有する半導体基板と、半導体基板を貫通する導電ビアと、半導体基板の背面上の金属構造と、を備える。金属構造は、導電ビアを被覆し、接触する金属パッド、及び、導電ビア上の金属線を含む。金属線はデュアルダマシン構造を含む。集積回路構造は、更に、金属線上のバンプを備える。
本発明の第２の態様は、集積回路構造であって、正面と背面を有する半導体基板と、半導体基板中の導電ビアとを備える。また、半導体基板の背面から半導体基板中に延伸し、導電ビアと接触する第一金属構造と、第一金属構造上で、且つ、第一金属構造に電気的に接続するバンプとを備える。
デュアルダマシンプロセスを用いて、背面相互接続構造を形成することにより、マルチ相互接続層がスタックされて、好ましいルーティング能力を有する。基板を凹陥することにより、金属パッドを形成して、ＴＳＶと接触し、金属パッドはサイズが大きく、金属パッドをＴＳＶに照準する精度要件が緩和される。更に、金属パッドと底部ＴＳＶは、大きい接触領域を有し、接触抵抗が減少する。
第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態に係る集積回路構造の製造工程断面図。 第１実施形態の変形例に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態に係る集積回路構造の製造工程断面図。 第２実施形態の変形例に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態に係る集積回路構造の製造工程断面図。 第３実施形態の変形例に係る集積回路構造の製造工程断面図。
ＴＳＶに接続される新規の背面相互接続構造を有する集積回路構造とその形成方法について説明する。以下、本発明の製造工程の一例、及びいくつかの実施態様について説明する。以降の図や説明において、同一要素には同一の符号を用いる。
[実施形態１]
図１を参照すると、基板１０と集積回路（図示しない）を含むチップ２が提供される。チップ２はウェハの一部である。基板１０は半導体基板、例えば、バルクシリコン基板（bulk silicon substrate）であるが、第III族、第IV族、及び/又は、第V族素子等の別の半導体材料を含んでいてもよい。トランジスタ（ブロック１５で示される）等のアクティブ半導体装置が、基板１０の前側１０ｆ上に形成される。本文中、 "背面" は、基板１０がアクティブ半導体装置を有する側と反対側である。金属線とバイアス（図示しない）を含む相互接続構造１２が、基板１０の前側１０ｆに形成されて、アクティブ半導体装置に接続される。金属線とバイアスは、銅、或いは、銅合金により構成され、公知のダマシンプロセス（damascene processes）により形成される。相互接続構造１２は、既知の層間絶縁膜（inter-layer dielectric 、ILD) と 金属間誘電体（inter-metal dielectric 、IMD)を備える。接着パッド１４が基板１０の前側１０ｆに形成される。
導電ビアであるＴＳＶ２０が基板１０中に形成され、前側１０ｆから基板１０中に延伸する。図１で示される第１実施形態においては、ＴＳＶ２０は、ビアファーストアプローチ（via-first approach）にて形成され、相互接続構造１２の形成前に形成される。従って、ＴＳＶ２０は、アクティブデバイスを被覆するのに用いられる層間絶縁膜だけに延伸するが、相互接続構造１２中の金属間誘電体層には延伸しない。なお、ＴＳＶ２０は、ビアラストアプローチ（via-last approach）にて形成し、相互接続構造１２の形成後に形成してもよい。この場合、ＴＳＶ２０は、基板１０と相互接続構造１２の両方を貫通する。絶縁層２２が、ＴＳＶ２０の側壁と端部上に形成され、ＴＳＶ２０と基板１０を電気的に絶縁する。絶縁層２２は、窒化ケイ素、酸化ケイ素（例えば、オルトけい酸テトラエチル（tetra-ethyl-ortho-silicate 、TEOS)酸化物等の一般の誘電体材料により形成される。チップ２と対応するウェハはキャリア２５に接着される。
図２を参照すると、背面研磨が実行されて、ＴＳＶ２０が、基板１０の背面１０ｂから露出する。ＴＳＶ２０を停止層として、背面研磨を実施する。その後、図３で示されるように、ＴＳＶ２０が凹陥し、その上表面が基板１０の背面１０ｂより低くなる。凹陥深さＤ１は、約０．５μｍより大きく、第１実施形態では、３μｍである。凹陥のプロセスにより、開口２４が形成される。
図４は、基板１０の凹陥プロセスを示し、そのプロセスは、フォトレジスト２６をマスクとして用いて実行される。凹陥のプロセスにより、開口２４の水平寸法が増加し、ＴＳＶ２０の水平寸法より大きくなる。図４の背面１０ｂの開口２４底部２８は、ＴＳＶ２０の露出端と同じ高さである。別の実施形態として、底部２８は、図４中の点線で示すように、ＴＳＶ２０の露出端より高くしたり、低くしたりしてもよい。開口２４の形成と同時に、（トレンチ）開口２７も形成される。
図５を参照すると、誘電絶縁層（dielectric isolation layer）３０が蒸着される。蒸着方法は、低温CVD（low-temperature chemical vapor deposition 、LTCVD)を含むが、他の常用の方法を使用してもよい。第１実施形態中、誘電絶縁層３０は窒化ケイ素(SiNx)で、 数百オングストロームの厚さを有する。次に、図６で示されるように、ＴＳＶ２０の端部を被覆する誘電絶縁層３０の一部が、フォトレジスト３１の使用とフォトリソグラフィプロセスの実行により、ビア開口３３で露出し、形成されたバンプは、ＴＳＶ２０に電気的に接続される。
図７〜図９は、再分配線とパッドの形成を示す図である。図７を参照すると、チタン、窒化チタン、タンタル、窒化タンタル等からなる導電バリア層（conductive barrier layer）３２が、例えば、スパッタリングにより形成される。次に、図８で示されるように、銅３４がめっきされる。銅３４の厚さは、深さＤ１(図３)に基づく。その後、化学機械研磨（chemical mechanical polish 、CMP)が実行され、第１金属構造である金属構造３６(３６−１と３６−２で示される)を形成する。得られた構造は図９で示される。金属構造３６は、金属線３６−１を含み、実際は、別のＴＳＶ（図示しない）に接続される。従って、金属線３６−１は、再分配線として使用される。金属構造３６−２は、金属パッドか金属線である。金属パッドは、ＴＳＶ２０より大きい寸法(頂部から見て) で、金属パッドは全水平方向で、ＴＳＶ２０の辺縁を越えて延在される。従って、金属パッド３６−２とＴＳＶ２０は大きい界面面積を有し、よって、接触抵抗が小さい。更に、金属パッド３６−２をＴＳＶ２０に照準する精度要件が緩和される。
図１０〜図１２Ａは、バンプ４２の形成プロセスを示す。図１０を参照すると、誘電層３８がブランケット蒸着（blanket deposited）される。第１実施形態中、誘電層３８は窒化ケイ素 (SiNx)で、厚さは、例えば、約０．２μｍである。次に、図１１で示されるように、フォトレジスト４０により、開口が誘電層３８中に形成されて、金属パッド３６−２が露出する。図１２Ａは、バンプ４２の形成を示し、水平寸法（長さ、或いは、幅）が約３０μｍ以下なので、マイクロバンプ（U-bump) とも称される。バンプ４２の形成方法は、電気化学めっき（electrical chemical plating 、ECP)、化学めっき、及び、浸漬（immersion）を含む。得られたバンプ４２は、電気ニッケル・無電解金（無電解ニッケル／浸漬金）（electroless nickel immersion gold 、ENIG)構造、無電解ニッケル／無電解パラジウム／無電解金(electroless nickel electroless palladium immersion gold ,ENEPIG)構造、或いは、 ニッケルパラジウム構造としてもよい。図１２Ａは、バンプ４２が、金属パッド３６−２の直上にあることを示しているが、バンプ４２は、金属パッド３６−２の直上になくてもよく、実際は、金属構造３６の形成と同時に形成される金属線３６−１と同様の再分配線により、金属パッド３６−２に接続されていてもよい。
図１２Ｂは、本発明の実施形態１の変形例を示す図である。金属パッド３６−２の直上にバンプ４２を形成する構成に代えて、追加の再分配線層が形成されている。例えば、付加層６０は、エッチ停止層４６、誘電層４８、第２金属構造であるビア５０と金属線５２を含み、付加層６０は、金属パッド３６−２とバンプ４２間に挿入される。必要であれば、付加層６０上に、更に多くの付加層６０と同様の層をスタックし、背面相互接続構造のルーティング可能性（routability）を増加させる。層６０の形成方法の詳細は、実質上、図１８〜図２１で示されるのと同じであり、後述する。
[第２実施形態]
図１３〜図２３Ｂを用いて、第２実施形態を説明する。第２実施形態の初期段階は、図１と図２で示したのと同様である。次に、図１３を参照すると、基板１０が背面からエッチバックされ、ＴＳＶ２０が、基板１０の背面を貫通する。第２実施形態においては、エッチバック深さＤ２は、約０．５μｍより大きく、約１μｍである。絶縁層２２も、ＴＳＶ２０の頂面からエッチバックされ、ＴＳＶ２０の頂面より低く、例えば、約０．５μｍである。従って、ＴＳＶ２０の側壁の一部が露出する。
図１４を参照すると、誘電層１２４が基板１０の背面に形成され、ＴＳＶ２０を被覆する。第２実施形態において、誘電層１２４はポリイミドからなり、厚さは約２μｍより大きく、例では、約３μｍである。他の誘電材料を用いてもよい。
図１５〜図１７は、金属線の形成プロセスを示す図である。図１５を参照すると、例えば、フォトレジスト（図示しない）を用いて、誘電層１２４をエッチングすることにより開口１２６が形成される。第２実施形態において、例えば、時間モードを用いて、開口形成プロセスが制御され、ＴＳＶ２０は、開口１２６の一つにより露出し、誘電層１２４の底部(層１２４'で示される)を残して、基板１０と開口１２６を分離する。
図１６を参照すると、まず洗浄を行い、導電バリア層１２８が、例えば、スパッタリングにより蒸着される。導電バリア層１２８は、チタン、タンタル等からなる。金属素材（metallic material）１３０がその後、誘電層１２４の頂面より高くなるまでめっきされる。金属素材１３０は銅を用いているが、アルミニウム、タングステン等のほかの材料を用いてもよい。その後、図１７で示されるように、ＣＭＰが実行され、金属線/パッド（金属構造）１３２(１３２−１と１３２−２)が形成される。金属線１３２−２は、チップ中のＴＳＶの一つに電気的に接続される。従って、金属線１３２−２は再分配線として用いられる。金属構造１３２−１は、金属パッド、或いは、金属線である。金属パッドは、ＴＳＶ２０より大きい寸法（上から見て）を有し、上視図で、金属パッド１３２−１は、全横方向で、ＴＳＶ２０の辺縁を越えて延在している。
図１８〜図２１は、相互接続の付加層の形成プロセスを示す図である。図１８を参照すると、誘電層１２５が形成される。第２実施形態では、誘電層１２５はポリイミドで形成され、約２．５μｍ等、数ミクロンの厚さを有する。その後、フォトレジスト１３４を用いて、パターン化される。パターン化されたフォトレジスト１３４により、誘電層１２５を、金属層１３２−２が露出するまでエッチングし、ビア開口１３６を形成する。
図１９を参照すると、フォトレジスト１３４が除去され、付加フォトレジスト１４０が形成、パターン化される。その後、図２０で示されるように、パターン化されたフォトレジスト１４０が誘電層１２５を更にエッチングすることにより、トレンチ開口１３８が形成される。エッチングは、時間モードを用いて実行され、エッチングは、誘電層１２５の中間で停止される。その後、フォトレジスト１４０が、例えば、アッシングにより除去される。図１８〜図２０で示されるステップは、ビアファーストアプローチであり、ビア開口１３６は、トレンチ開口１３８が形成される前に形成されることが理解できる。当業者なら、図２０で示される構造は、図１９と図２０に示すステップを図１８に示すステップより前に行うトレンチファーストアプローチにより形成してもよいことがわかるであろう。
図２１は、金属線１４４とビア１４６を含むダマシン構造の形成を示す図であり、導電バリア層１４８（例えば、Ｔｉ層）を蒸着するステップと、銅をめっきするステップと、ＣＭＰを実行し、余分な銅を除去するステップと、からなる。図２２〜図２３Ａは、誘電層３８とバンプ４２の形成を示す図である。形成プロセスは、本質的には、第１実施形態と同じであり、よって、ここで、詳述しない。図２３Ｂは、本発明の第２実施形態の変形例を示す図で、金属線１４４とビア１４６は、誘電層１２４中に形成される。
[第３実施形態]
図２４〜図２９Ｂは、第３実施形態を説明するための図である。第３実施形態の初期ステップは、図１と図２と同様である。次に、図２４で示されるように、エッチ停止層２２０が形成される。第３実施形態中、エッチ停止層２２０は窒化ケイ素で形成され、厚さは、例えば、約７５０Åである。誘電層２２２は、エッチ停止層２２０上に形成される。第３実施形態中、誘電層２２２は、様々な化学気相蒸着方法（ＣＶＤ）の一つを用いて形成され、誘電層２２２は、例えば、酸化物からなる。ＣＶＤ誘電層２２２の厚さは、例えば、約８０００Åである。別の第３実施形態中、誘電層２２２は、ポリイミドで形成され、厚さは、ＣＶＤを用いて形成するより誘電層の厚さよりも大幅に大きい。ポリイミドで形成される誘電層２２２の厚さは、約２μｍより大きく、第３実施形態では、約５μｍである。
図２５〜図２７は、ビア開口２２６とトレンチ開口２２８の形成を示す図である。形成の詳細は、本質的に図１８〜図２０と同じであり、ここで詳述しない。次に、図２８で示されるように、デュアルダマシン構造が形成される。デュアルダマシン構造は、ビア２３２とビア２３２を被覆する金属線２３４と、からなり、金属線２３４は銅から形成される。導電バリア層２３６も形成される。
図２９Ａは、誘電層３８とバンプ４２の形成プロセスを示す図である。誘電層３８とバンプ４２の材料と形成プロセスは、実質上、図１０〜図１２Ａと同じである。図２９Ｂは、相互接続の付加層（６０）を有する変形例を示す図で、追加のデュアルダマシン構造を含む。必要であれば、更に多くの相互接続が挿入される。
上述の実施形態は、幾つかの優れた特色を有する。デュアルダマシンプロセスを用いて、背面相互接続構造を形成することにより、マルチ相互接続層がスタックされて、好ましいルーティング能力を提供する。ＴＳＶを接触させる金属パッド(図１０の３６−２と図１７の１３２−１)を形成するために基板を凹陥させるので、金属パッドは大きなサイズとすることができる。その結果、ＴＳＶに対する金属パッドの配置の精度要求は緩和される。更に、金属パッドとその下のＴＳＶは、大きい接触領域を有し、接触抵抗が減少する。
以上、本発明の好ましい実施形態を例示したが、これらは本発明を限定するものではなく、本発明の趣旨と範囲を逸脱しない限りにおいては、当業者なら行い得る種々の変更や修飾を付加することができる。従って、本発明が請求する保護範囲は、特許請求の範囲を基準とする。
２ チップ
１０ 基板
１０ｂ 背面
１０ｆ 前側
１２ 相互接続構造
１４ 接着パッド
１５ トランジスタ
２０ ＴＳＶ
２２ 絶縁層
２４ 開口
２５ キャリア
２６、３１ フォトレジスト
２７ （トレンチ）開口
２８ 底部
３０ 誘電絶縁層
３２、１２８、１４８、２３６ 導電バリア層
３３、１３６、２２６ 開口
３４ 銅
３６（３６−１と３６−２） 金属構造
３８、４８、２２２ 誘電層
４０ フォトレジスト
４２ バンプ
４６ ２２０ エッチ停止層
５０ １４６ ビア
５２ 金属線
６０ 付加層
１２４ １２４'誘電層
１２５ 誘電層
１２６ 開口
１３０ 金属素材
１３２（１３２−１と１３２−２） 金属線／パッド
２３４ 金属線
１３４ フォトレジスト
１３８ ２２８ トレンチ開口
１４０ フォトレジスト
１４４ 金属線
２３２ ビア
Ｄ１、Ｄ２ 深さ

Claims (9)

  1. 集積回路構造であって、
    正面と背面を有する半導体基板と、
    前記半導体基板を貫通する導電ビアと、
    前記半導体基板の背面上にあり、前記導電ビアを被覆し、接触する金属パッド、及び、前記導電ビア上に位置し、デュアルダマシン構造を含む金属線を具備する金属構造と、
    前記金属線上のバンプと、を備えることを特徴とする集積回路構造。
  2. 前記金属パッドは、更に、
    前記導電ビアの頂面と接触する第一底面と、
    前記半導体基板の前記背面より高く、且つ、前記第一底面より低い第二底面と、
    を備えることを特徴とする請求項１に記載の集積回路構造。
  3. 前記デュアルダマシン構造は、前記金属パッドと同じ誘電層中にあることを特徴とする請求項１又は２に記載の集積回路構造。
  4. 前記デュアルダマシン構造は、前記金属パッド上の誘電層中にあることを特徴とする請求項１又は２に記載の集積回路構造。
  5. 前記金属パッドの全水平寸法は、それぞれ、前記導電ビアの水平寸法より大きいことを特徴とする請求項１〜４のいずれか１項に記載の集積回路構造。
  6. 集積回路構造であって、
    正面と背面を有する半導体基板と、
    前記半導体基板中の導電ビアと、
    前記半導体基板の背面から前記半導体基板中に延伸し、前記導電ビアと接触する第一金属構造と、
    前記第一金属構造上で、且つ、前記第一金属構造に電気的に接続するバンプと、
    前記第一金属構造と前記バンプ間に形成され、デュアルダマシン構造を含む第二金属構造と、
    を備えることを特徴とする集積回路構造。
  7. 前記第一金属構造の全水平寸法は、それぞれ、前記導電ビアの水平寸法より大きいことを特徴とする請求項６に記載の集積回路構造。
  8. 前記第一金属構造は、前記半導体基板の前記背面と同じ高さの頂面を有することを特徴とする請求項６又は７に記載の集積回路構造。
  9. 前記第一金属構造は、
    前記導電ビアに接触する導電バリア層と、
    前記導電バリア層上の銅含有金属材料と、
    からなることを特徴とする請求項６〜８のいずれか１項に記載の集積回路構造。
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Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8716867B2 (en) 2010-05-12 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interconnect structures using pre-ink-printed sheets
US9190325B2 (en) * 2010-09-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. TSV formation
KR101697573B1 (ko) 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20120090417A (ko) * 2011-02-08 2012-08-17 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP2012256679A (ja) 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置及びその製造方法
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
CN103000571B (zh) * 2011-09-19 2015-07-08 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法
CN103890940B (zh) 2011-10-28 2017-03-01 英特尔公司 包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构
CN103890939B (zh) * 2011-10-28 2017-03-01 英特尔公司 包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构
US20130313710A1 (en) * 2012-05-22 2013-11-28 Micron Technology, Inc. Semiconductor Constructions and Methods of Forming Semiconductor Constructions
KR101931115B1 (ko) 2012-07-05 2018-12-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140023055A (ko) * 2012-08-16 2014-02-26 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
KR102021884B1 (ko) * 2012-09-25 2019-09-18 삼성전자주식회사 후면 본딩 구조체를 갖는 반도체 소자
US8859425B2 (en) * 2012-10-15 2014-10-14 Micron Technology, Inc. Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
KR102018885B1 (ko) * 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US10483132B2 (en) * 2012-12-28 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US9466578B2 (en) * 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
US20150179580A1 (en) * 2013-12-24 2015-06-25 United Microelectronics Corp. Hybrid interconnect structure and method for fabricating the same
US9093503B1 (en) * 2014-01-03 2015-07-28 International Business Machines Corporation Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
KR102222485B1 (ko) * 2014-09-18 2021-03-04 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
TWI582918B (zh) * 2014-11-12 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
KR102279729B1 (ko) * 2014-12-01 2021-07-21 삼성전자주식회사 Ｔｓｖ, 전면 범핑 패드 및 후면 범핑 패드를 갖는 반도체 소자
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
US9666523B2 (en) 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US9472490B1 (en) 2015-08-12 2016-10-18 GlobalFoundries, Inc. IC structure with recessed solder bump area and methods of forming same
KR20170023643A (ko) 2015-08-24 2017-03-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10121812B2 (en) * 2015-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked substrate structure with inter-tier interconnection
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
JP6955864B2 (ja) * 2016-12-26 2021-10-27 ラピスセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
WO2018136712A1 (en) * 2017-01-20 2018-07-26 Tokyo Electon Limited Interconnect structure and method of forming the same
KR102406573B1 (ko) * 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10515921B2 (en) 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US11843020B2 (en) 2017-10-30 2023-12-12 Samsung Electronics Co., Ltd. Image sensor
KR102542614B1 (ko) 2017-10-30 2023-06-15 삼성전자주식회사 이미지 센서
US11521923B2 (en) * 2018-05-24 2022-12-06 Intel Corporation Integrated circuit package supports
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
KR102635832B1 (ko) 2018-09-28 2024-02-15 삼성전자주식회사 반도체 소자 및 그 제조방법
US10727124B2 (en) 2018-10-29 2020-07-28 International Business Machines Corporation Structure and method for forming fully-aligned trench with an up-via integration scheme
JP7353748B2 (ja) * 2018-11-29 2023-10-02 キヤノン株式会社 半導体装置の製造方法および半導体装置
US11195810B2 (en) 2019-08-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure and method of forming same
US11398408B2 (en) * 2019-09-24 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate with trace connected to via at a level within a dielectric layer
US11094580B2 (en) * 2019-10-01 2021-08-17 International Business Machines Corporation Structure and method to fabricate fully aligned via with reduced contact resistance
US11217481B2 (en) * 2019-11-08 2022-01-04 International Business Machines Corporation Fully aligned top vias
US11295978B2 (en) * 2020-04-29 2022-04-05 International Business Machines Corporation Interconnects having spacers for improved top via critical dimension and overlay tolerance
KR20210133524A (ko) 2020-04-29 2021-11-08 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
KR20220129924A (ko) * 2021-03-17 2022-09-26 삼성전자주식회사 인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지
CN113078119B (zh) * 2021-03-26 2022-03-18 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
KR20220167423A (ko) 2021-06-11 2022-12-21 삼성전자주식회사 관통 전극들을 포함하는 반도체 소자
US12002758B2 (en) 2021-11-04 2024-06-04 International Business Machines Corporation Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer
KR20240019456A (ko) * 2022-08-04 2024-02-14 삼성전자주식회사 반도체 장치

Family Cites Families (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2034900B (en) * 1978-11-17 1982-10-20 Marconi Instruments Ltd Spectrum analyser
US4872750A (en) * 1982-07-14 1989-10-10 Nec Home Electronics Ltd. Image projection apparatus
US4799050A (en) * 1986-10-23 1989-01-17 Litton Systems Canada Limited Full color liquid crystal display
JP2554724B2 (ja) * 1987-12-11 1996-11-13 株式会社リコー レーザーダイオードアレイを用いる光走査光学系
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US5646067A (en) 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
EP1798592A3 (en) * 1996-01-17 2007-09-19 Nippon Telegraph And Telephone Corporation Optical device and three-dimensional display device
EP2270846A3 (en) 1996-10-29 2011-12-21 ALLVIA, Inc. Integrated circuits and methods for their fabrication
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
JPH10163315A (ja) * 1996-11-28 1998-06-19 Nec Ic Microcomput Syst Ltd 半導体回路装置
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3600470B2 (ja) * 1998-06-22 2004-12-15 パイオニア株式会社 プラズマディスプレイパネル
KR100281897B1 (ko) 1998-07-21 2001-03-02 윤종용 도전층을 갖는 반도체 장치의 제조방법
US6706189B2 (en) 1998-10-09 2004-03-16 Zenon Environmental Inc. Cyclic aeration system for submerged membrane modules
WO2000025176A1 (fr) * 1998-10-28 2000-05-04 Dai Nippon Printing Co., Ltd. Afficheur a cristaux liquides
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP3998373B2 (ja) 1999-07-01 2007-10-24 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6785028B1 (en) * 1999-11-24 2004-08-31 Ricoh Company, Ltd. Optical scanning device having a temperature compensation unit
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6417087B1 (en) * 1999-12-16 2002-07-09 Agere Systems Guardian Corp. Process for forming a dual damascene bond pad structure over active circuitry
US6292285B1 (en) * 1999-12-20 2001-09-18 Xerox Corporation Single rotating polygon mirror with v-shaped facets for a multiple beam ROS
JP3626058B2 (ja) 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2001291720A (ja) 2000-04-05 2001-10-19 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US7053465B2 (en) 2000-11-28 2006-05-30 Texas Instruments Incorporated Semiconductor varactor with reduced parasitic resistance
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6696360B2 (en) * 2001-03-15 2004-02-24 Micron Technology, Inc. Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
JP2002296714A (ja) * 2001-03-30 2002-10-09 Fuji Photo Film Co Ltd 放射線画像情報読取方法
US7224063B2 (en) * 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
KR100404479B1 (ko) * 2001-06-21 2003-11-05 주식회사 하이닉스반도체 듀얼 다마신 배선 형성방법
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
CN1215551C (zh) * 2002-04-12 2005-08-17 台湾积体电路制造股份有限公司 阻绝气体释放及凸出结构产生的双镶嵌方法
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP3774715B2 (ja) * 2002-10-21 2006-05-17 キヤノン株式会社 投射型表示装置
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US7354798B2 (en) * 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
JP4072677B2 (ja) 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2004297019A (ja) 2003-03-28 2004-10-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
JP4248928B2 (ja) * 2003-05-13 2009-04-02 ローム株式会社 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US6897125B2 (en) 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US6878616B1 (en) * 2003-11-21 2005-04-12 International Business Machines Corporation Low-k dielectric material system for IC application
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4339152B2 (ja) * 2004-03-08 2009-10-07 富士通マイクロエレクトロニクス株式会社 配線構造の形成方法
JP4074862B2 (ja) 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4439976B2 (ja) * 2004-03-31 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
JP4327644B2 (ja) * 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
TWI427700B (zh) 2004-08-20 2014-02-21 Kamiyacho Ip Holdings 三維積層構造之半導體裝置之製造方法
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
KR20060054689A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR20060054690A (ko) 2004-11-16 2006-05-23 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
KR101052366B1 (ko) 2004-11-16 2011-07-28 강준모 후면 입출력 단자를 갖는 반도체 장치 및 그 제조방법
JP2006339584A (ja) * 2005-06-06 2006-12-14 Sharp Corp 半導体装置およびその製造方法
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7429529B2 (en) 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20070081239A1 (en) * 2005-10-06 2007-04-12 May Gregory J Optical characteristics of a screen
US7609442B2 (en) * 2005-10-13 2009-10-27 Hewlett-Packard Development Company, L.P. Synchronizing screen
TW200733270A (en) * 2005-10-19 2007-09-01 Koninkl Philips Electronics Nv Redistribution layer for wafer-level chip scale package and method therefor
JP5073946B2 (ja) 2005-12-27 2012-11-14 新光電気工業株式会社 半導体装置および半導体装置の製造方法
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7514775B2 (en) 2006-10-09 2009-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US7544605B2 (en) 2006-11-21 2009-06-09 Freescale Semiconductor, Inc. Method of making a contact on a backside of a die
JP4415984B2 (ja) * 2006-12-06 2010-02-17 ソニー株式会社 半導体装置の製造方法
US8247322B2 (en) * 2007-03-01 2012-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Via/contact and damascene structures and manufacturing methods thereof
US7697183B2 (en) * 2007-04-06 2010-04-13 Prysm, Inc. Post-objective scanning beam systems
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
KR20080101635A (ko) 2007-05-18 2008-11-21 삼성전자주식회사 반도체 패키지, 그 제조 방법, 및 반도체 패키지를 이용한패키지 모듈 및 전자 제품
JP4937842B2 (ja) 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20090057909A1 (en) 2007-06-20 2009-03-05 Flipchip International, Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TW200910557A (en) 2007-06-20 2009-03-01 Flipchip Int Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TWI351751B (en) 2007-06-22 2011-11-01 Ind Tech Res Inst Self-aligned wafer or chip structure, self-aligned
US8556430B2 (en) * 2007-06-27 2013-10-15 Prysm, Inc. Servo feedback control based on designated scanning servo beam in scanning beam display systems with light-emitting screens
US8193092B2 (en) 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
KR101387701B1 (ko) * 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2009055004A (ja) * 2007-08-24 2009-03-12 Honda Motor Co Ltd 貫通配線構造
US20090102052A1 (en) * 2007-10-22 2009-04-23 Sang Wook Ryu Semiconductor Device and Fabricating Method Thereof
JP2009147218A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置とその製造方法
JP5358089B2 (ja) 2007-12-21 2013-12-04 スパンション エルエルシー 半導体装置
US7804119B2 (en) 2008-04-08 2010-09-28 International Business Machines Corporation Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP5324822B2 (ja) * 2008-05-26 2013-10-23 ラピスセミコンダクタ株式会社 半導体装置
US7939449B2 (en) * 2008-06-03 2011-05-10 Micron Technology, Inc. Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension back side ends
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20100013060A1 (en) 2008-06-22 2010-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a conductive trench in a silicon wafer and silicon wafer comprising such trench
US7800238B2 (en) 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US7869112B2 (en) * 2008-07-25 2011-01-11 Prysm, Inc. Beam scanning based on two-dimensional polygon scanner for display and other applications
US8384224B2 (en) * 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
KR20100021856A (ko) 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
KR20100045857A (ko) * 2008-10-24 2010-05-04 삼성전자주식회사 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법
US7935571B2 (en) * 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) * 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US7999320B2 (en) 2008-12-23 2011-08-16 International Business Machines Corporation SOI radio frequency switch with enhanced signal fidelity and electrical isolation
US8264077B2 (en) * 2008-12-29 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips
US8097964B2 (en) * 2008-12-29 2012-01-17 Texas Instruments Incorporated IC having TSV arrays with reduced TSV induced stress
US7910473B2 (en) 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8399354B2 (en) 2009-01-13 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with low-K dielectric liner
US8531015B2 (en) * 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8294261B2 (en) * 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
JP5019303B2 (ja) * 2010-03-03 2012-09-05 Ｓｍｃ株式会社 電磁弁駆動回路、電磁弁及び電磁弁の駆動方法
US8587121B2 (en) * 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8174124B2 (en) * 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing

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US8791549B2 (en) 2014-07-29
US9449875B2 (en) 2016-09-20
KR101319701B1 (ko) 2013-10-17
US9978708B2 (en) 2018-05-22
TW201112371A (en) 2011-04-01
CN102024781B (zh) 2013-04-17
US20110068466A1 (en) 2011-03-24
US20140312494A1 (en) 2014-10-23
US20170005069A1 (en) 2017-01-05
US9716074B2 (en) 2017-07-25
KR20110033022A (ko) 2011-03-30
TWI453879B (zh) 2014-09-21
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US20140322909A1 (en) 2014-10-30
CN102024781A (zh) 2011-04-20

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