JP4433298B2 - 多段構成半導体モジュール - Google Patents
多段構成半導体モジュール Download PDFInfo
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Description
本発明の第1の実施形態に係る多段構成の半導体モジュールについて、図1〜図3を参照して説明する。
本発明の第2の実施形態に係る多段構成の半導体モジュールについて、図1、図2、図4を参照して説明する。図4(a)、(c)は、それぞれ本実施形態の半導体モジュール1に用いられる第1の樹脂基板3およびシート部材5を示す平面図である。また、図4(b)は、第1の樹脂基板3をIVb−IVb線に沿って切断したときの断面図であり、(d)は、シート部材5をIVd−IVd線に沿って切断したときの断面図である。
本発明の第3の実施形態に係る多段構成の半導体モジュールについて、図1、図2、図5を参照して説明する。図5(a)、(c)は、それぞれ本実施形態の半導体モジュール1に用いられる第1の樹脂基板3およびシート部材5を示す平面図である。また、図5(b)は、第1の樹脂基板3をVb−Vb線に沿って切断したときの断面図であり、(d)は、シート部材5をVd−Vd線に沿って切断したときの断面図である。
本発明の第4の実施形態に係る多段構成の半導体モジュールについて、図1、図2、図6を参照して説明する。図6(a)、(c)は、それぞれ本実施形態の半導体モジュール1に用いられる第1の樹脂基板3およびシート部材5を示す平面図である。また、図6(b)は、第1の樹脂基板3をVIb−VIb線に沿って切断したときの断面図であり、(d)は、シート部材5をVId−VId線に沿って切断したときの断面図である。
本発明の第5の実施形態に係る多段構成の半導体モジュールについて、図1、図2、図6を参照して説明する。本実施形態の半導体モジュール1の構成は、第4の実施形態の半導体モジュールと同一であるが、樹脂基板またはシート部材の対角線上に配置された埋め込み導体の接続先のみが異なっている。
本発明の第6の実施形態に係る多段構成の半導体モジュールについて、図7を参照して説明する。図7(a)、(b)は、本実施形態の半導体モジュールのうち半導体チップが搭載された第1の樹脂基板を示す平面図および断面図である。
図8は、本発明の各実施形態に係る半導体モジュールを分解して示す断面図である。ここでは、第1〜6の各実施形態の半導体モジュールの構成を分かりやすく示している。ただし、第1〜6の実施形態の半導体モジュールにおいては、半導体チップ2a、2b、2c、2dは共に同一の半導体チップである。
本発明の第8実施形態に係る多段構成の半導体モジュールについて、図8を参照して説明する。
2、2a、2b、2c、2d 半導体チップ
3 第1の樹脂基板
4 第2の樹脂基板
5 シート部材
6 第2の樹脂基材
7 第1の埋め込み導体
8 第1の樹脂基材
9 第2の埋め込み導体
10 開口部
11 半導体素子接続端子
12 配線
13 接続用ランド
15 接着層
16 半田ボール
17 電極バンプ
18 封止樹脂
19 最下層基板ビア
Claims (6)
- 複数の第1の埋め込み導体を有し、上面上に半導体チップが実装された樹脂基板と、前記半導体チップを収納するための開口部が形成され、前記複数の第1の埋め込み導体と電気的に接続された複数の第2の埋め込み導体を有するシート部材とが交互に積層されてなる多段構成半導体モジュールであって、
前記複数の第1の埋め込み導体は、前記半導体チップを実装するための実装領域を囲む領域に配置され、
前記複数の第1の埋め込み導体の各々の径は、前記実装領域との距離が近いほど大きくなっていることを特徴とする多段構成半導体モジュール。 - 前記複数の第2の埋め込み導体は、前記開口部を囲む領域に配置され、
前記複数の第2の埋め込み導体の各々の径は、前記開口部との距離が近いほど大きくなっていることを特徴とする請求項1に記載の多段構成半導体モジュール。 - 前記複数の第1の埋め込み導体は、前記半導体チップを実装するための実装領域を囲む領域に、内外に位置する複数の列に分けて配置され、
前記複数の第2の埋め込み導体は、前記開口部を囲む領域に、内外に位置する複数の列に分けて配置され、
前記複数の第1の埋め込み導体で構成された複数の列のうち内側の列を構成する第1の埋め込み導体の径は、外側の列を構成する第1の埋め込み導体の径より大きくなっており、
前記複数の第2の埋め込み導体で構成された複数の列のうち内側の列を構成する第2の埋め込み導体の径は、外側の列を構成する第2の埋め込み導体の径より大きくなっていることを特徴とする請求項2に記載の多段構成半導体モジュール。 - 複数の第1の埋め込み導体を有し、上面上に半導体チップが実装された樹脂基板と、前記半導体チップを収納するための開口部が形成され、前記複数の第1の埋め込み導体と電気的に接続された複数の第2の埋め込み導体を有するシート部材とが交互に積層されてなる多段構成半導体モジュールであって、
前記複数の第1の埋め込み導体は、前記半導体チップを実装するための実装領域を囲む領域に、内外に位置する複数の列に分けて配置され、
前記複数の第1の埋め込み導体のうち、前記樹脂基板の対角線上に配置された第1の埋め込み導体の径は他の第1の埋め込み導体の径以上であり、且つ前記実装領域に近づくにつれて大きくなっていることを特徴とする多段構成半導体モジュール。 - 前記複数の第2の埋め込み導体は、前記開口部を囲む領域に、内外に位置する複数の列に分けて配置され、
前記複数の第2の埋め込み導体のうち、前記シート部材の対角線上に配置された第2の埋め込み導体の径は他の第2の埋め込み導体の径以上であり、且つ前記開口部に近づくにつれて大きくなっていることを特徴とする請求項4に記載の多段構成半導体モジュール。 - 前記半導体チップは電源供給用端子と接地用端子とを有しており、
前記樹脂基板の対角線上に配置された第1の埋め込み導体および前記シート部材の対角線上に配置された第2の埋め込み導体のうち、内周列に配置された第1の埋め込み導体および第2の埋め込み導体は前記接地用端子に接続され、外周列に配置された第1の埋め込み導体および第2の埋め込み導体は前記電源供給用端子に接続されていることを特徴とする請求項5に記載の多段構成半導体モジュール。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004364570A JP4433298B2 (ja) | 2004-12-16 | 2004-12-16 | 多段構成半導体モジュール |
KR1020050056232A KR20060069229A (ko) | 2004-12-16 | 2005-06-28 | 다단구성 반도체모듈 |
US11/274,414 US20060131715A1 (en) | 2004-12-16 | 2005-11-16 | Multi-level semiconductor module |
CNB2005101271800A CN100505242C (zh) | 2004-12-16 | 2005-11-30 | 多层构成半导体微型组件 |
TW094144285A TW200623354A (en) | 2004-12-16 | 2005-12-14 | Multi-level semiconductor module |
US11/594,760 US7327021B2 (en) | 2004-12-16 | 2006-11-09 | Multi-level semiconductor module |
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JP2004364570A JP4433298B2 (ja) | 2004-12-16 | 2004-12-16 | 多段構成半導体モジュール |
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JP4433298B2 true JP4433298B2 (ja) | 2010-03-17 |
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JP2004364570A Expired - Fee Related JP4433298B2 (ja) | 2004-12-16 | 2004-12-16 | 多段構成半導体モジュール |
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US (2) | US20060131715A1 (ja) |
JP (1) | JP4433298B2 (ja) |
KR (1) | KR20060069229A (ja) |
CN (1) | CN100505242C (ja) |
TW (1) | TW200623354A (ja) |
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JP2006041438A (ja) * | 2004-07-30 | 2006-02-09 | Shinko Electric Ind Co Ltd | 半導体チップ内蔵基板及びその製造方法 |
JP4504798B2 (ja) * | 2004-12-16 | 2010-07-14 | パナソニック株式会社 | 多段構成半導体モジュール |
JP4880218B2 (ja) * | 2004-12-22 | 2012-02-22 | 三洋電機株式会社 | 回路装置 |
JP4520355B2 (ja) * | 2005-04-19 | 2010-08-04 | パナソニック株式会社 | 半導体モジュール |
US7528474B2 (en) * | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
TW200743035A (en) * | 2006-05-09 | 2007-11-16 | Siliconware Precision Industries Co Ltd | Circuit card module and method for fabricating the same |
US8581380B2 (en) * | 2006-07-10 | 2013-11-12 | Stats Chippac Ltd. | Integrated circuit packaging system with ultra-thin die |
JP4843515B2 (ja) * | 2007-02-01 | 2011-12-21 | パナソニック株式会社 | 半導体チップの積層構造 |
US8134235B2 (en) | 2007-04-23 | 2012-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional semiconductor device |
JP2008306105A (ja) * | 2007-06-11 | 2008-12-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US8053900B2 (en) * | 2008-10-21 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
EP2405727A1 (en) * | 2009-04-02 | 2012-01-11 | Panasonic Corporation | Manufacturing method for circuit board, and circuit board |
JP5340789B2 (ja) * | 2009-04-06 | 2013-11-13 | 新光電気工業株式会社 | 電子装置及びその製造方法 |
KR101665556B1 (ko) | 2009-11-19 | 2016-10-13 | 삼성전자 주식회사 | 멀티 피치 볼 랜드를 갖는 반도체 패키지 |
KR102161173B1 (ko) * | 2013-08-29 | 2020-09-29 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
US9589936B2 (en) * | 2014-11-20 | 2017-03-07 | Apple Inc. | 3D integration of fanout wafer level packages |
JP6517629B2 (ja) * | 2015-08-20 | 2019-05-22 | 株式会社東芝 | 平面型アンテナ装置 |
CN109285825B (zh) * | 2017-07-21 | 2021-02-05 | 联华电子股份有限公司 | 芯片堆叠结构及管芯堆叠结构的制造方法 |
US10686105B2 (en) * | 2018-06-18 | 2020-06-16 | Advanced Semiconductor Engineering, Inc. | Optical package device |
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WO1998047331A1 (fr) * | 1997-04-16 | 1998-10-22 | Kabushiki Kaisha Toshiba | Tableau de connexions, son procede de fabrication et boitier de semi-conducteur |
JP2001068617A (ja) * | 1999-08-27 | 2001-03-16 | Toshiba Corp | 半導体装置 |
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JP2001177051A (ja) * | 1999-12-20 | 2001-06-29 | Toshiba Corp | 半導体装置及びシステム装置 |
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JP4365515B2 (ja) | 2000-08-21 | 2009-11-18 | イビデン株式会社 | 半導体モジュールの製造方法 |
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US20030042587A1 (en) * | 2001-08-31 | 2003-03-06 | Tsung-Jen Lee | IC packaging and manufacturing methods |
JP3655242B2 (ja) * | 2002-01-04 | 2005-06-02 | 株式会社東芝 | 半導体パッケージ及び半導体実装装置 |
JP4022405B2 (ja) | 2002-01-23 | 2007-12-19 | イビデン株式会社 | 半導体チップ実装用回路基板 |
JP2003234431A (ja) * | 2002-02-08 | 2003-08-22 | Ibiden Co Ltd | 半導体チップ実装回路基板とその製造方法および多層化回路基板 |
JP2004186494A (ja) * | 2002-12-04 | 2004-07-02 | Toshiba Corp | 積層型半導体装置の製造方法 |
-
2004
- 2004-12-16 JP JP2004364570A patent/JP4433298B2/ja not_active Expired - Fee Related
-
2005
- 2005-06-28 KR KR1020050056232A patent/KR20060069229A/ko not_active Application Discontinuation
- 2005-11-16 US US11/274,414 patent/US20060131715A1/en not_active Abandoned
- 2005-11-30 CN CNB2005101271800A patent/CN100505242C/zh not_active Expired - Fee Related
- 2005-12-14 TW TW094144285A patent/TW200623354A/zh unknown
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2006
- 2006-11-09 US US11/594,760 patent/US7327021B2/en active Active
Also Published As
Publication number | Publication date |
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US7327021B2 (en) | 2008-02-05 |
CN1790706A (zh) | 2006-06-21 |
US20070057358A1 (en) | 2007-03-15 |
JP2006173387A (ja) | 2006-06-29 |
TW200623354A (en) | 2006-07-01 |
CN100505242C (zh) | 2009-06-24 |
US20060131715A1 (en) | 2006-06-22 |
KR20060069229A (ko) | 2006-06-21 |
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