JP5257096B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5257096B2 JP5257096B2 JP2009013529A JP2009013529A JP5257096B2 JP 5257096 B2 JP5257096 B2 JP 5257096B2 JP 2009013529 A JP2009013529 A JP 2009013529A JP 2009013529 A JP2009013529 A JP 2009013529A JP 5257096 B2 JP5257096 B2 JP 5257096B2
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- semiconductor element
- die pad
- notch
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- 230000000903 blocking effect Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- WABPQHHGFIMREM-RNFDNDRNSA-N lead-211 Chemical compound [211Pb] WABPQHHGFIMREM-RNFDNDRNSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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Description
この場合、第1のダイパッドの厚さは第2のダイパッドの厚さに比べて厚いことが好ましい。
図1乃至図3に示すように、本実施例に係る半導体装置1は、第1の方向Xに離間して順次配列された第1の半導体素子31、第2の半導体素子32、第3の半導体素子33及び第4の半導体素子34と、第1の方向Xに延伸し、第1の表面21A上に第1の半導体素子31乃至第4の半導体素子34を搭載し、第1の方向Xと交差する第2の方向Yにおいて、第1の側面21C1から第1の半導体素子31と第2の半導体素子32との間に達する第1の切欠部211、第1の側面21C1から第3の半導体素子33と第4の半導体素子34との間に達する第2の切欠部212、及び第1の側面21C1から第2の半導体素子32と第3の半導体素子33との間に達し第1の切欠部211及び第2の切欠部212の長さに比べて長い第3の切欠部213を有する第1のダイパッド21と、第1のダイパッド21の第1の側面21C1に対向する第2の側面21C2に連接され、第1の半導体素子31乃至第4の半導体素子34に共通の第1のリード23(D1)、23(D2)、23(D3)とを備えている。
図1及び図2に示す本実施例に係る半導体装置1において、第1の半導体素子31乃至第4の半導体素子34は、例えば、同一の半導体素子であり、シリコン(Si)、シリコンカーバイト(SiC)、窒化物半導体のいずれかからなる。ここでは、第1の半導体素子31乃至第4の半導体素子34は、例えば縦型構造を有するスイッチング素子又はダイオードを有する。また、本実施例において、第1の半導体素子31乃至第4の半導体素子34は、横型構造、又は縦型構造と横型構造とを混在させたスイッチング素子又はダイオードを備えてよい。例えば、横型構造を有するスイッチング素子を有する半導体素子が使用される場合、第1のダイパッド21とこの半導体素子との間には絶縁物を介在させることができる。スイッチング素子には、少なくともMOSFET(metal oxide semiconductor field effect transistor)、MISFET(metal insulated semiconductor field effect transistor)のいずれかが含まれる。
電子部品としての制御回路35は、本実施例において、第1の半導体素子31乃至第4の半導体素子34のそれぞれの駆動制御を行う制御用モノリシックIC(MIC)である。制御回路35は、第1の半導体素子31乃至第4の半導体素子34のそれぞれと同様にSi、SiC又は窒化物半導体からなり、この半導体チップにトランジスタ、容量、抵抗等の素子を集積化して回路を構築している。制御回路35は、必ずしもこの数値に限定されるものではないが、例えば第1の方向Xの長さを6.4mm−6.8mm、第2の方向Yの長さを4.0mm−4.4mmとした平面形状を有する。また、第3の方向Zの厚さは0.3mm−0.5mmに設定されている。
配線基板36は、第2のダイパッド22の第1の表面22A上において、図1中、制御回路35の左側、右側のそれぞれに配設されている。配線基板36は、本実施例において、絶縁基板361と、その表面上に配設された配線362とを備えている。配線基板36の配線362は、第1の方向Xに延伸し、第2の方向Yに一定間隔において複数本配列されている。
図1に示すように、第1のダイパッド21の平面形状は、第1の方向Xに細長く延伸し、第1の半導体素子31乃至第4の半導体素子34のそれぞれを搭載した部分が第1の側面21C1として第2の方向Yに突出し、逆に第1の切欠部211、第2の切欠部212及び第3の切欠部213の部分が第1の側面21C1から第2の側面21C2に向かって途中まで後退し、第2の側面21C2部分が第1の方向Xに連なる櫛形形状により構成されている。
第1のダイパッド21に配設された第1の切欠部211は、第1の半導体素子31と第2の半導体素子32とが対向する側面に対して、50%以上100%以下掛かる長さL1に設定されている。更に、第1の切欠部211は、第1のダイパッド21の厚さに対して、50%以上100%以下の幅W1に設定されている。ここで、第1の切欠部211の長さL1とは第1の切欠部211の第2の方向Yの長さであり、第1の切欠部211の幅W1とは第1の切欠部211の第1の方向Xの長さである。
図10は第1のダイパッド21の第1の表面21Aから第2の表面(裏面)2Bを経て樹脂封止体5の裏面に至る放熱経路の熱抵抗と第1の切欠部211の幅W1との関係を示す。図10中、横軸は第1のダイパッド21に配設した第1の切欠部211の幅W1(mm)である。縦軸は第1の半導体素子31を発熱させ1秒後に樹脂封止体5の裏面において測定した放熱経路(第1のダイパッド21の第1の表面21A−樹脂封止体5の裏面)の熱抵抗(℃/W)である。
図1乃至図3に示すように、第1のリード23は、第1のダイパッド21の第2の側面21C2に対向し、この第2の側面21C2に沿って複数本配列されている。図1中、最も左端に配列された第1のリード23(N1)、それから第1の方向Xに順次配列された第1のリード23(S1)、第1のリード23(S2)、第1のリード23(S3)、第1のリード23(S4)、最も右端に配列された第1のリード23(N2)のそれぞれのインナー部は、第1のダイパッド21の第2の側面21C2から一定間隔において離間され、第1のダイパッド21とは電気的に絶縁されている。
図1及び図2に示すように、第2のダイパッド22は、第1のダイパッド21の第1の側面21C1に第1の側面22C1を対向させ、離間させて配設されている。第1のダイパッド21の第1の側面21C1と第2のダイパッドの第1の側面22C1との離間寸法は、本実施例において、例えば0.3mm−0.5mmに設定されている。第2のダイパッド22の第1の方向Xの長さは例えば26.0mm−30.0mmに設定され、第2の方向Yの幅すなわち第1の側面22C1からそれに対向する第2の側面22C2までの寸法は例えば4.2mm−4.4mmに設定されている。第2のダイパッド22の第3の方向Zの厚さは第1のリード23の厚さと同一である。
図1乃至図3に示すように、第2のリード24は、第2のダイパッド22の第2の側面22C2に対向し、この第2の側面21C2に沿って複数本配列されている。図1中、最も左端に配列された第2のリード24、左側中央部に配列された第2のリード24、右側中央部に配列された第2のリード24、最も右側に配列された第2のリード24のそれぞれは第2のダイパッド22に一体に形成され、連接されかつ電気的に接続されている。これらの第2のリード24は吊りリードとして機能する。それ以外の第2のリード24は信号端子、電源端子、又は空き端子として使用される。
ここで、本実施例に係る半導体装置1の製造過程(組立過程)において、図12に示すリードフレーム2が使用される。リードフレーム2は、外枠25及び26に、前述の第1のダイパッド21、第2のダイパッド22、第1のリード23及び第2のリード24を連接し、それらを一体に構成したものである。ここでは、本実施例においては、第1の方向Xに複数個分の半導体装置1を同時に製作できる多連リードフレーム2が使用されている。
図1乃至図3に示すように、樹脂封止体5は、第1のダイパッド21、それに搭載された第1の半導体素子31乃至第4の半導体素子34、第2のダイパッド22、それに搭載された制御回路35及び配線基板36、第1のリード23のインナー部、第2のリード24のインナー部を被覆する。樹脂封止体5の製作にはトランスファーモールド法が使用される。樹脂封止体5には例えば熱硬化型エポキシ系樹脂が使用される。
以上説明したように、本実施例に係る半導体装置1においては、1つの共通の第1のダイパッド21に複数の第1の半導体素子31乃至第4の半導体素子34を搭載したので、半導体素子毎にダイパッドを分割した場合に比べて、全体の小型化を実現することができる。更に、本実施例に係る半導体装置1においては、小型化の実現により、第1のワイヤ41、第2のワイヤ42のそれぞれのワイヤ長を短くすることができ、信号伝搬速度を速くすることができるので、動作速度の高速化を実現することができる。
上記のように、本発明を一実施例によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施の形態、実施例及び運用技術に適用することができる。例えば、前述の実施例において、半導体装置1の最終的なリード形状を説明していないが、第1のリード23、第2のリード24のそれぞれのアウター部の形状は、ピン挿入型、面実装型のいずれであってもよい。
2…リードフレーム
21…第1のダイパッド
22…第2のダイパッド
23…第1のリード
24…第2のリード
211…第1の切欠部
212…第2の切欠部
213…第3の切欠部
31…第1の半導体素子
32…第2の半導体素子
33…第3の半導体素子
34…第4の半導体素子
35…制御回路
36…配線基板
41…第1のワイヤ
42…第2のワイヤ
5…樹脂封止体
Claims (2)
- 第1の方向に離間して配列された第1の半導体素子及び第2の半導体素子と、
前記第1の方向に延伸し、第1の表面上に前記第1の半導体素子及び前記第2の半導体素子を搭載し、前記第1の方向と交差する第2の方向において第1の側面から前記第1の半導体素子と前記第2の半導体素子との間に達する切欠部を有する第1のダイパッドと、
前記第1のダイパッドの前記第1の側面と異なる第2の側面に連接されたリードと、
を備え、
前記第1のダイパッドの前記第1の表面からそれと対向する第2の表面までの厚さは前記リードの厚さに比べて厚いことを特徴とする半導体装置。 - 前記第1の半導体素子、前記第2の半導体素子、前記第1のダイパッドの前記第1の表面、この第1の表面に対向する第2の表面を覆い、前記切欠部に埋設された樹脂封止体を更に備え、
前記樹脂封止体の前記第1のダイパッドの前記第2の表面上の厚さは、前記第1のダイパッドの前記第1の表面から前記第2の表面までの厚さに比べて薄く、かつ前記樹脂封止体の前記第1のダイパッドの前記第1の表面上の厚さに比べて薄いことを特徴とする請求項1に記載の半導体装置。
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