JP5225091B2 - 電界効果トランジスタにおいて非対称のオーバーラップ容量を形成するための構造及び方法 - Google Patents
電界効果トランジスタにおいて非対称のオーバーラップ容量を形成するための構造及び方法 Download PDFInfo
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
電界効果トランジスタ(FET)におけるオーバーラップ容量を低減するための方法及び構造が、本明細書に開示される。従来のFET製造プロセスにおいて、ゲート導電体の対向する側部に形成されたスペーサ構造体は、一般に対称性であり、そのためその後に形成されたソース及びドレインのエクステンションは、ゲートに対して同じ量のオーバーラップを有する。しかしながら、トランジスタの駆動電流は、主としてソース側のオーバーラップ(すなわち、ゲートからソースへの抵抗)の量によって制御されるため、ドレイン側のオーバーラップの量は、駆動電流に悪影響を及ぼすことなくもっと低減することができる。その一方で、ゲートからドレインへのオーバーラップの低減は、例えば、短チャネル効果、パンチスルー、ホット・キャリア効果及び寄生キャパシタンスの点で有益である。
102:ゲート構造体
104:基板
106:ゲート酸化物層
108:STI構造
110、130、132、122:スペーサ層
112:傾斜イオン注入
114、124:スペーサ
116、118、120:エクステンション
Claims (5)
- 半導体デバイスのための電界効果トランジスタ(FET)構造体を形成する方法であって、
半導体基板(104)の上に少なくとも1対の隣接して離間配置されるゲート構造体(102)を形成するステップと、
前記1対の隣接して離間配置されたゲート構造体(102)の側壁に隣接してオフセット・スペーサ(114、114a、114b)を形成するステップと、
前記オフセット・スペーサの形成後の前記ゲート構造体(102)の両側の前記基板(104)内にエクステンション領域を形成するステップと、
前記オフセット・スペーサ、前記ゲート構造体(102)及び前記エクステンション領域の形成後の前記基板(104)の上に第2のスペーサ層(122)を形成するステップと、
前記第2のスペーサ層(122)に中性種の単一傾斜イオン注入(112)を受けさせるステップであって、前記傾斜イオン注入(112)は単一方向から発するステップと、
前記第2のスペーサ層(122)をエッチングするステップであって、前記傾斜イオン注入を受けた前記第2のスペーサ層の部分は、その非暴露部分より速い速度でエッチングされ、そのため前記オフセット・スペーサに隣接する非対称の第2のスペーサ(124a、124b)が形成されるステップと、
前記第2のスペーサの形成後の前記基板(104)にドーパントを注入してソース及びドレイン領域を形成するステップと、を含む方法。 - 前記ソース領域は、前記ドレイン領域よりも短いエクステンションを有する、請求項11記載の方法。
- 前記中性種は、ゲルマニウムとキセノンのうちの少なくとも1つを含む、請求項1または2に記載の方法。
- 前記オフセット・スペーサ(114a、114b)もまた、前記ゲート構造体(102)及び前記基板(104)の上に形成された第1のスペーサ層(110)における中性種の傾斜イオン注入によって、非対称に形成される、請求項1に記載の方法。
- 薄い方のオフセット・スペーサ(114b)に対応する前記エクステンション領域は、厚い方のオフセット・スペーサ(114a)に対応する前記エクステンション領域よりも長いゲート・オーバーラップを有する、請求項4に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US11/163,165 US7396713B2 (en) | 2005-10-07 | 2005-10-07 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
US11/163,165 | 2005-10-07 | ||
PCT/US2006/038593 WO2007044324A2 (en) | 2005-10-07 | 2006-10-02 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2012169233A Division JP5602799B2 (ja) | 2005-10-07 | 2012-07-31 | 半導体デバイスのための非対称スペーサ構造体を形成する方法 |
Publications (2)
Publication Number | Publication Date |
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JP2009512192A JP2009512192A (ja) | 2009-03-19 |
JP5225091B2 true JP5225091B2 (ja) | 2013-07-03 |
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JP2008534619A Expired - Fee Related JP5225091B2 (ja) | 2005-10-07 | 2006-10-02 | 電界効果トランジスタにおいて非対称のオーバーラップ容量を形成するための構造及び方法 |
JP2012169233A Expired - Fee Related JP5602799B2 (ja) | 2005-10-07 | 2012-07-31 | 半導体デバイスのための非対称スペーサ構造体を形成する方法 |
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JP2012169233A Expired - Fee Related JP5602799B2 (ja) | 2005-10-07 | 2012-07-31 | 半導体デバイスのための非対称スペーサ構造体を形成する方法 |
Country Status (7)
Country | Link |
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US (2) | US7396713B2 (ja) |
EP (1) | EP1946360A4 (ja) |
JP (2) | JP5225091B2 (ja) |
KR (1) | KR101054703B1 (ja) |
CN (1) | CN101647108B (ja) |
TW (1) | TW200731417A (ja) |
WO (1) | WO2007044324A2 (ja) |
Families Citing this family (31)
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2005
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2006
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EP1946360A2 (en) | 2008-07-23 |
WO2007044324A3 (en) | 2009-06-11 |
US20080185662A1 (en) | 2008-08-07 |
JP2012253371A (ja) | 2012-12-20 |
JP2009512192A (ja) | 2009-03-19 |
US20070080401A1 (en) | 2007-04-12 |
CN101647108B (zh) | 2011-09-14 |
US7396713B2 (en) | 2008-07-08 |
KR101054703B1 (ko) | 2011-08-08 |
CN101647108A (zh) | 2010-02-10 |
KR20080061378A (ko) | 2008-07-02 |
JP5602799B2 (ja) | 2014-10-08 |
TW200731417A (en) | 2007-08-16 |
EP1946360A4 (en) | 2009-11-11 |
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