JP5149631B2 - 半導体メモリ装置 - Google Patents
半導体メモリ装置 Download PDFInfo
- Publication number
- JP5149631B2 JP5149631B2 JP2008007104A JP2008007104A JP5149631B2 JP 5149631 B2 JP5149631 B2 JP 5149631B2 JP 2008007104 A JP2008007104 A JP 2008007104A JP 2008007104 A JP2008007104 A JP 2008007104A JP 5149631 B2 JP5149631 B2 JP 5149631B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- data
- semiconductor memory
- pulse signal
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Description
200 DLL回路
300 パルス発生器
400 プリドライバ
500 メインドライバ
600 遅延チューニング部
700 位相検出器
3A 読出回路
3B データアイ制御回路
Claims (7)
- 半導体メモリ装置において、
外部クロックを内部クロックとしてバッファリングするクロックバッファと、
前記内部クロックを入力してDLLクロックをクロックとして出力するDLL回路と、
データを前記クロックの入力に同期して出力する出力回路と、
該出力回路の出力のデータアイを制御するデータアイ制御回路と
を備え、
前記出力回路が、前記DLLクロックを入力してパルス信号を出力するパルス発生器を備え、
前記データアイ制御回路が、前記内部クロック及び前記パルス信号を受信し、前記パルス信号のパルス幅が前記内部クロックのパルス幅を超えたことを検出する位相検出器を備え、
前記位相検出器によって検出された値に基づき、前記パルス発生器が前記パルス信号のパルス幅を制御することを特徴とする半導体メモリ装置。 - 前記データを供給するパイプレジスタを更に備えることを特徴とする請求項1に記載の半導体メモリ装置。
- 前記出力回路が、
前記データを入力し、この入力を前記パルス信号の入力に同期して出力するプリドライバと、
該プリドライバの出力に該当する出力データを外部に出力するメインドライバと
を更に備えることを特徴とする請求項1に記載の半導体メモリ装置。 - 前記DLLクロックが、立ち上がりクロック及び立ち下がりクロックを含んでなることを特徴とする請求項1に記載の半導体メモリ装置。
- 前記位相検出器に入力される前記内部クロックとパルス信号とを同期化して供給する遅延チューニング部を更に備えることを特徴とする請求項1に記載の半導体メモリ装置。
- 内部クロックが遅延ロックされたDLLクロックを出力するステップと、
データのデータアイを制御するステップと、
前記データを前記DLLクロックの入力に同期して出力するステップと
を含み、
前記DLLクロックの入力に同期して出力するステップが、
前記DLLクロックを入力してパルス信号を出力するステップと、
前記データを前記パルス信号の入力に同期して出力するステップとを含み、
前記データのデータアイを制御するステップが、
前記パルス信号のパルス幅が前記内部クロックのパルス幅を超えたことを検出するステップと、
前記検出された値に基づき、前記パルス信号のパルス幅を制御するステップと
を含むことを特徴とする半導体メモリ装置の駆動方法。 - 前記データのデータアイを制御するステップが、
前記パルス信号のパルス幅が前記内部クロックのパルス幅を超えたことを検出するステップの前に、前記内部クロックとパルス信号とを同期化して供給するステップを更に含むことを特徴とする請求項6に記載の半導体メモリ装置の駆動方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2007-0057727 | 2007-06-13 | ||
KR1020070057727A KR100907928B1 (ko) | 2007-06-13 | 2007-06-13 | 반도체 메모리 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008310943A JP2008310943A (ja) | 2008-12-25 |
JP5149631B2 true JP5149631B2 (ja) | 2013-02-20 |
Family
ID=40132324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008007104A Expired - Fee Related JP5149631B2 (ja) | 2007-06-13 | 2008-01-16 | 半導体メモリ装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8379784B2 (ja) |
JP (1) | JP5149631B2 (ja) |
KR (1) | KR100907928B1 (ja) |
TW (1) | TWI407437B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2010137076A1 (ja) * | 2009-05-28 | 2012-11-12 | 株式会社アドバンテスト | パルス測定装置およびパルス測定方法ならびにそれらを用いた試験装置 |
JP2012129851A (ja) * | 2010-12-16 | 2012-07-05 | Elpida Memory Inc | 半導体装置 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5371684A (en) | 1992-03-31 | 1994-12-06 | Seiko Epson Corporation | Semiconductor floor plan for a register renaming circuit |
JPH06209243A (ja) | 1992-08-25 | 1994-07-26 | Fujitsu Ltd | デューティファクタ補償回路 |
US5706292A (en) | 1996-04-25 | 1998-01-06 | Micron Technology, Inc. | Layout for a semiconductor memory device having redundant elements |
JP4070255B2 (ja) * | 1996-08-13 | 2008-04-02 | 富士通株式会社 | 半導体集積回路 |
JP3720934B2 (ja) * | 1996-12-17 | 2005-11-30 | 富士通株式会社 | 半導体記憶装置とデータ読み出し及び書き込み方法 |
US6020776A (en) | 1998-06-22 | 2000-02-01 | Xilinx, Inc. | Efficient multiplexer structure for use in FPGA logic blocks |
US6430696B1 (en) * | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
JP3873532B2 (ja) | 1999-07-14 | 2007-01-24 | 富士通株式会社 | 半導体装置 |
JP2002082830A (ja) * | 2000-02-14 | 2002-03-22 | Mitsubishi Electric Corp | インターフェイス回路 |
JP4592179B2 (ja) | 2000-12-19 | 2010-12-01 | ルネサスエレクトロニクス株式会社 | ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法 |
US6889336B2 (en) * | 2001-01-05 | 2005-05-03 | Micron Technology, Inc. | Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal |
KR100437539B1 (ko) * | 2001-06-29 | 2004-06-26 | 주식회사 하이닉스반도체 | 클럭 동기 회로 |
US6930524B2 (en) * | 2001-10-09 | 2005-08-16 | Micron Technology, Inc. | Dual-phase delay-locked loop circuit and method |
KR100413774B1 (ko) | 2002-02-22 | 2004-01-03 | 삼성전자주식회사 | 래이 아웃 면적을 감소시키는 반도체 메모리 장치 |
US7130367B1 (en) * | 2002-04-09 | 2006-10-31 | Applied Micro Circuits Corporation | Digital delay lock loop for setup and hold time enhancement |
JP4138521B2 (ja) | 2003-02-13 | 2008-08-27 | 富士通株式会社 | 半導体装置 |
JP2005038526A (ja) | 2003-07-16 | 2005-02-10 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
KR100540472B1 (ko) | 2003-10-31 | 2006-01-11 | 주식회사 하이닉스반도체 | 데이터 출력에 관한 동작마진이 향상된 메모리 장치 |
KR100673885B1 (ko) | 2004-04-27 | 2007-01-26 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 듀티 싸이클 교정 장치 및 그 방법 |
US7116143B2 (en) * | 2004-12-30 | 2006-10-03 | Micron Technology, Inc. | Synchronous clock generator including duty cycle correction |
KR100640629B1 (ko) * | 2005-01-12 | 2006-10-31 | 삼성전자주식회사 | 동기식 반도체 메모리 장치의 지연 동기 루프 회로 및동기식 반도체 메모리 장치의 데이터 핀에 연결된 부하의정보를 생성하는 방법 |
KR100562655B1 (ko) * | 2005-02-28 | 2006-03-20 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 동작 제한 필터 및 그 방법 |
JP4928097B2 (ja) * | 2005-07-29 | 2012-05-09 | 株式会社アドバンテスト | タイミング発生器及び半導体試験装置 |
US7400181B2 (en) * | 2005-09-30 | 2008-07-15 | Agere Systems Inc. | Method and apparatus for delay line control using receive data |
JP2007141383A (ja) * | 2005-11-18 | 2007-06-07 | Elpida Memory Inc | 半導体記憶装置 |
KR100800150B1 (ko) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | 지연 고정 루프 장치 |
-
2007
- 2007-06-13 KR KR1020070057727A patent/KR100907928B1/ko not_active IP Right Cessation
- 2007-12-28 US US12/005,841 patent/US8379784B2/en active Active
-
2008
- 2008-01-10 TW TW097101012A patent/TWI407437B/zh not_active IP Right Cessation
- 2008-01-16 JP JP2008007104A patent/JP5149631B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008310943A (ja) | 2008-12-25 |
TW200849249A (en) | 2008-12-16 |
TWI407437B (zh) | 2013-09-01 |
US20080310574A1 (en) | 2008-12-18 |
KR20080109423A (ko) | 2008-12-17 |
US8379784B2 (en) | 2013-02-19 |
KR100907928B1 (ko) | 2009-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100399941B1 (ko) | 디디알 에스디램의 레지스터 제어 지연고정루프 | |
KR100733471B1 (ko) | 반도체 기억 소자의 지연 고정 루프 회로 및 그 제어 방법 | |
JP5047736B2 (ja) | Dll回路及びその制御方法 | |
US7489172B2 (en) | DLL driver control circuit | |
US7348819B2 (en) | Delay locked loop circuit | |
KR100732760B1 (ko) | 지연고정루프회로 | |
US7944260B2 (en) | Clock control circuit and a semiconductor memory apparatus having the same | |
US20070069782A1 (en) | Delay locked loop for high speed semiconductor memory device | |
KR20050076202A (ko) | 지연 신호 발생 회로 및 이를 포함한 메모리 시스템 | |
KR100733465B1 (ko) | 지연고정루프회로 | |
KR100910852B1 (ko) | 반도체 메모리 소자 | |
US8773189B2 (en) | Domain crossing circuit of semiconductor apparatus | |
JP6104586B2 (ja) | 半導体装置及び半導体装置の動作方法 | |
JP5149631B2 (ja) | 半導体メモリ装置 | |
KR100550633B1 (ko) | 반도체 기억 소자의 지연 고정 루프 및 그의 제어 방법 | |
US8638137B2 (en) | Delay locked loop | |
KR100735548B1 (ko) | 지연동기회로 및 방법 | |
KR100631952B1 (ko) | Dll 회로의 출력신호 구동장치 | |
US8331190B2 (en) | Semiconductor memory device and operation method thereof | |
US20100283519A1 (en) | Clock signal generating circuit and semiconductor memory apparatus including the same | |
US7902889B2 (en) | Delay locked loop | |
KR20060113305A (ko) | 지연고정루프의 클럭 버퍼 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110106 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20120323 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20120402 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120619 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120919 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121106 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121130 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151207 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |