JP5011329B2 - メタルポストを備えた基板及びその製造方法 - Google Patents
メタルポストを備えた基板及びその製造方法 Download PDFInfo
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
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- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H05K2203/04—Soldering or other types of metallurgic bonding
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
図4は本発明の好適な実施例によるメタルポストを備えた基板の断面図である。以下、この図に基づいて本実施例によるメタルポストを備えた基板100について説明する。
また、酸化防止用ソルダバンプ膜122bは、メタルポスト116の側面に形成されてメタルポスト116を外部から遮断することで、空気による酸化、及び工程の進行中に使用される化学薬品による腐食を防止する機能をする。
この際、表面処理層118は、すず(Sn)系丸形ソルダバンプ122と結合して、その界面にNix−Sny系の金属間化合物層(Intermetallic compound layer;IMC layer)が形成される。この金属間化合物層は、例えば約1μm以下の厚さを持つことが好ましい。
図5〜図14は本発明の好適な実施例によるメタルポストを備えた基板の製造方法を順に示す工程断面図(1)〜(10)である。以下、これら図に基づいて、本実施例によるメタルポストを備えた基板100の製造方法を説明する。
104 接続パッド
106 ソルダレジスト層
110 シード層
112 感光性レジスト
114 開口部
116 メタルポスト
118 表面処理層
120 ソルダペースト
122 ソルダバンプ
122a 丸形ソルダバンプ
122b 酸化防止用ソルダバンプ膜
Claims (19)
- 接続パッドが形成されたベース基板;
前記ベース基板に形成され、前記接続パッドを露出させる開放部を持つソルダレジスト層;
前記接続パッドに連結され、前記ソルダレジスト層の上部に突出したメタルポスト;及び
前記突出したメタルポストの上部を含む外面に形成されるとともに、前記メタルポスト上に形成された丸形ソルダバンプ、及び前記メタルポストの側面に一定の側面厚さにて形成された酸化防止用ソルダバンプ膜を含むソルダバンプ;
を含むことを特徴とする、メタルポストを備えた基板。 - 前記丸形ソルダバンプの高さは、前記ソルダレジスト層の上部に突出したメタルポストの高さの50〜70%であることを特徴とする、請求項1に記載のメタルポストを備えた基板。
- 前記酸化防止用ソルダバンプ膜は、前記メタルポストの側面と同じ形状に前記メタルポストの側面に形成されることを特徴とする、請求項1に記載のメタルポストを備えた基板。
- 前記酸化防止用ソルダバンプ膜の側面厚さは、前記丸形ソルダバンプの直径の5%以下であることを特徴とする、請求項1に記載のメタルポストを備えた基板。
- 前記メタルポスト上には、表面処理層が形成されていることを特徴とする、請求項1に記載のメタルポストを備えた基板。
- 前記表面処理層は、ニッケルメッキ層またはニッケル合金メッキ層に形成されるか、さらに前記ニッケルメッキ層または前記ニッケル合金メッキ層上にパラジウムメッキ層、金メッキ層、または前記パラジウムメッキ層及び前記金メッキ層が順に形成された複合層が形成されたものであることを特徴とする、請求項5に記載のメタルポストを備えた基板。
- 前記表面処理層と前記丸形ソルダバンプの界面には、Nix−Sny系の金属間化合物層が形成されていることを特徴とする、請求項6に記載のメタルポストを備えた基板。
- 前記金属間化合物層は、1μm以下の厚さに形成されることを特徴とする、請求項7に記載のメタルポストを備えた基板。
- (A)接続パッドが形成されたベース基板に、前記接続パッドを露出させる開放部を持つソルダレジスト層を形成し、前記開放部を含む前記ソルダレジスト層上にシード層を形成する段階;
(B)前記開放部を含む前記ソルダレジスト層に感光性レジストを塗布し、前記感光性レジストに、前記接続パッドを露出させる開口部を形成する段階;
(C)前記開口部の一部に、前記接続パッドに連結されるメタルポストを形成する段階;
(D)前記開口部内の前記メタルポスト上にソルダペーストを形成し、前記ソルダペーストに1次リフローを行って丸形ソルダバンプを形成し、前記感光性レジスト及び前記シード層を除去する段階;及び
(E)前記丸形ソルダバンプに2次リフローを行って、前記丸形ソルダバンプを構成するソルダが前記メタルポストの側面に流れるようにし、前記メタルポストの側面に酸化防止用ソルダバンプ膜を形成し、前記丸形ソルダバンプ及び前記酸化防止用ソルダバンプ膜を含むソルダバンプを形成する段階;
を含み、
前記酸化防止用ソルダバンプ膜は、前記メタルポストの側面に一定の側面厚さにて形成されることを特徴とする、メタルポストを備えた基板の製造方法。 - 前記メタルポストは、前記感光性レジストの高さの半分まで形成されることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記(C)段階と前記(D)段階の間に、(C1)前記メタルポスト上に表面処理層を形成する段階をさらに含むことを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記表面処理層は、ニッケルメッキ層またはニッケル合金メッキ層に形成されるか、さらに前記ニッケルメッキ層または前記ニッケル合金メッキ層上にパラジウムメッキ層、金メッキ層、または前記パラジウムメッキ層及び前記金メッキ層が順に形成された複合層が形成されてなることを特徴とする、請求項11に記載のメタルポストを備えた基板の製造方法。
- 前記表面処理層と前記丸形ソルダバンプの界面には、Nix−Sny系の金属間化合物層が形成されることを特徴とする、請求項12に記載のメタルポストを備えた基板の製造方法。
- 前記金属間化合物層は、1μm以下の厚さに形成されることを特徴とする、請求項13に記載のメタルポストを備えた基板の製造方法。
- 前記(D)段階において、前記ソルダペーストは、前記感光性レジストの表面と同じ高さを持つように、前記開口部の前記メタルポストに充填されることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記2次リフローは、前記1次リフローに比べ、20%程度速い速度で行われることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記(E)段階において、前記丸形ソルダバンプの高さは、前記ソルダレジスト層の上部に突出したメタルポストの高さの50〜70%であることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記酸化防止用ソルダバンプ膜は、前記メタルポストの側面と同じ形状に前記メタルポストの側面に形成されることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
- 前記酸化防止用ソルダバンプ膜の側面厚さは、前記丸形ソルダバンプの直径の5%以下に形成されることを特徴とする、請求項9に記載のメタルポストを備えた基板の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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KR10-2008-0119805 | 2008-11-28 | ||
KR1020080119805A KR20100060968A (ko) | 2008-11-28 | 2008-11-28 | 메탈 포스트를 구비한 기판 및 그 제조방법 |
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JP2010129996A JP2010129996A (ja) | 2010-06-10 |
JP5011329B2 true JP5011329B2 (ja) | 2012-08-29 |
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JP2009049565A Expired - Fee Related JP5011329B2 (ja) | 2008-11-28 | 2009-03-03 | メタルポストを備えた基板及びその製造方法 |
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US (1) | US20100132998A1 (ja) |
JP (1) | JP5011329B2 (ja) |
KR (1) | KR20100060968A (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
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KR101019642B1 (ko) * | 2009-04-27 | 2011-03-07 | 삼성전기주식회사 | 인쇄회로기판 제조 방법 |
US8637392B2 (en) | 2010-02-05 | 2014-01-28 | International Business Machines Corporation | Solder interconnect with non-wettable sidewall pillars and methods of manufacture |
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-
2008
- 2008-11-28 KR KR1020080119805A patent/KR20100060968A/ko not_active Application Discontinuation
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2009
- 2009-02-27 US US12/379,760 patent/US20100132998A1/en not_active Abandoned
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US20100132998A1 (en) | 2010-06-03 |
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