JP6530298B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents
配線基板、半導体装置及び配線基板の製造方法 Download PDFInfo
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- JP6530298B2 JP6530298B2 JP2015201143A JP2015201143A JP6530298B2 JP 6530298 B2 JP6530298 B2 JP 6530298B2 JP 2015201143 A JP2015201143 A JP 2015201143A JP 2015201143 A JP2015201143 A JP 2015201143A JP 6530298 B2 JP6530298 B2 JP 6530298B2
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- layer
- connection terminal
- insulating layer
- wiring
- protective insulating
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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Description
なお、添付図面は、便宜上、特徴を分かりやすくするために特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、断面図では、各部材の断面構造を分かりやすくするために、一部の部材のハッチングを梨地模様に代えて示し、一部の部材のハッチングを省略している。
図1(a)に示すように、配線基板10は、配線基板10の厚さ方向の中心付近に設けられた基板本体20を有している。基板本体20は、コア基板21と、コア基板21を厚さ方向に貫通する貫通孔21Xに形成された貫通電極22と、コア基板21の上面及び下面にそれぞれ積層され、貫通電極22を介して互いに電気的に接続された配線23,24とを有している。また、基板本体20は、コア基板21の上面に配線23を被覆するように形成された絶縁層25と、コア基板21の下面に配線24を被覆するように形成された絶縁層26とを有している。
絶縁層42の上面42Aには、接続端子52の側面を被覆する保護絶縁層70が積層されている。保護絶縁層70は、例えば、接続端子52の側面の一部に接し、その接続端子52の側面の一部を被覆するように形成されている。また、保護絶縁層70は、例えば、接続端子52から露出する絶縁層42の上面42A全面を被覆するように形成されている。本例の保護絶縁層70の厚さは、接続端子52の厚さよりも薄く設定されている。このため、各接続端子52の上面及び各接続端子52の上面側の側面は、保護絶縁層70から露出されている。
配線層50は、貫通孔42Xの内面(つまり、貫通孔42Xの内側面及び貫通孔42Xの底部に露出する配線層40の上面)と、絶縁層42の上面42Aとを連続的に被覆するシード層60を有している。本例のシード層60は、貫通孔42Xの内面と絶縁層42の上面42Aとを連続的に被覆する金属膜61と、その金属膜61の上面を被覆する金属膜62とが順に積層された2層構造のシード層である。金属膜61は、例えば、その側面が接続端子52及び金属膜62の側面よりも外側に突出するように形成されている。すなわち、本例では、金属膜61の外形が、接続端子52や金属膜62の外形よりも大きく形成されている。
図2(a)に示すように、半導体装置80は、配線基板10と、1つ又は複数(ここでは、1つ)の半導体チップ90と、アンダーフィル材95と、外部接続端子96とを有している。
接続端子52には、はんだ層92が直接接合されている。すなわち、配線基板10では、保護絶縁層70から露出する接続端子52の表面(上面及び側面)に表面処理層が形成されていない。換言すると、配線基板10では、保護絶縁層70から露出する接続端子52の上部54の表面(上面及び側面)が、配線基板10の最表面になっている。そして、はんだ層92は、接続端子52の上部54、つまり結晶粒径が比較的大きい上部54の平滑面54S及び平滑面54Tに直接接合されている。
次に、配線基板10及び半導体装置80の作用について説明する。
図3(a)に示すように、まず、配線層50及び保護絶縁層70が形成される前段階の配線基板10を準備する。この配線基板10は、公知の製造方法により製造することが可能であるため、その概略について図3(a)を参照しながら説明する。
次に、図8及び図9に従って、半導体装置80の製造方法について説明する。
図8(a)に示す工程では、保護絶縁層70の上面に、保護絶縁層70から露出する接続端子52を被覆するようにB−ステージ状態(半硬化状態)のアンダーフィル材95を形成する。アンダーフィル材95の材料としてフィルム状の絶縁樹脂を用いた場合には、保護絶縁層70の上面にフィルム状の絶縁樹脂をラミネートする。但し、この工程では、フィルム状の絶縁樹脂の熱硬化は行わず、B−ステージ状態にしておく。なお、アンダーフィル材95を真空雰囲気中でラミネートすることにより、アンダーフィル材95中へのボイドの巻き込みを抑制することができる。一方、アンダーフィル材95の材料として液状又はペースト状の絶縁樹脂を用いる場合には、保護絶縁層70の上面に液状又はペースト状の絶縁樹脂を例えば印刷法やディスペンサ法により塗布する。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(1)柱状の接続端子52の側面に接してその側面を被覆する保護絶縁層70を形成した。これにより、接続端子52と絶縁層42及び保護絶縁層70との界面を増加させることができ、接続端子52と絶縁層42及び保護絶縁層70との界面に生じる応力を分散させることができる。この結果、接続端子52と絶縁層42及び保護絶縁層70との界面にクラックが発生することを好適に抑制できる。
なお、上記実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・図10に示すように、保護絶縁層70の上面に、上方に盛り上がる***部71を形成するようにしてもよい。***部71は、例えば、その頂部72(上端部)が断面視において針のように尖った形状に形成されている。具体的には、***部71は、頂部72から接続端子52に向かって下方に傾斜する傾斜部73と、頂部72から、接続端子52から離間する方向に向かって下方に傾斜する傾斜部74とから構成されている。本変形例では、傾斜部73は、頂部72から接続端子52に向かって湾曲状に凹むように形成されている。また、傾斜部74は、頂部72から、接続端子52から離間する方向に向かって断面視円弧状に凹むように形成されている。このような***部71(とくに、傾斜部73)によって、はんだ層92(図2参照)が接続端子52の外側に広がることを好適に抑制することができる。
・上記実施形態における保護絶縁層70の凹部70Xを省略してもよい。すなわち、保護絶縁層70の上面を平坦面に形成してもよい。
・上記実施形態において、接続端子52の上部54の側面全面を保護絶縁層70から露出させるようにしてもよい。この場合の保護絶縁層70は、シード層60の側面全面と接続端子52の下部53の側面全面又は下部53の側面の一部とを被覆するように形成される。
・上記実施形態では、金属膜61の側面を、接続端子52及び金属膜62の側面よりも外側に突出するように形成した。これに限らず、例えば、金属膜61の側面を、接続端子52及び金属膜62の側面と面一になるように形成してもよい。また、金属膜61の側面を、接続端子52及び金属膜62の側面よりも内側に後退するように形成してもよい。
・上記実施形態の図7(a)や図7(b)に示した工程において、保護絶縁層70から露出された接続端子52の上面及び側面に、表面処理層を形成するようにしてもよい。表面処理層の例としては、Au層、Ni層/Au層、Ni層/Pd層/Au層などを挙げることができる。また、OSP処理などの酸化防止処理を施して表面処理層を形成するようにしてもよい。
40 配線層
42 絶縁層
42X 貫通孔
50 配線層
51 ビア配線
52 接続端子(第1接続端子)
53 下部
54 上部
60 シード層
61,62 金属膜(スパッタ膜)
70 保護絶縁層
70X 凹部
74 傾斜部(凹部)
80 半導体装置
90 半導体チップ(電子部品)
91 接続端子(第2接続端子)
92 はんだ層
93 合金層
101 感光性樹脂層
Claims (8)
- 配線層と、
前記配線層を被覆する絶縁層と、
前記絶縁層を厚さ方向に貫通して前記配線層の上面を露出する貫通孔と、
前記貫通孔内に形成されたビア配線と、
前記ビア配線を介して前記配線層と電気的に接続され、前記絶縁層の上面から上方に突出して形成され、電子部品と接続される柱状の第1接続端子と、
前記第1接続端子の側面に接し前記第1接続端子の側面の一部を被覆するように前記絶縁層の上面に形成された保護絶縁層と、を有し、
前記第1接続端子は、下部と上部とからなり、
前記保護絶縁層は、前記第1接続端子よりも薄く、前記下部の側面全面と前記上部の側面の一部とを被覆し、
前記下部における結晶粒径は、前記上部における結晶粒径よりも小さく設定され、
前記下部と前記上部とは、同一の金属材料からなり、
前記下部の側面の表面粗度は、前記上部の側面の表面粗度よりも大きく設定されており、
前記保護絶縁層から露出された前記上部の側面部分の表面粗度は、前記保護絶縁層により被覆された前記上部の側面部分の表面粗度よりも小さく設定されていることを特徴とする配線基板。 - 前記保護絶縁層から露出された前記上部の表面は、前記配線基板の最表面であることを特徴とする請求項1に記載の配線基板。
- 前記貫通孔に露出する前記配線層の上面と前記貫通孔の内側面と前記絶縁層の上面とを連続して被覆するスパッタ膜を有し、
前記ビア配線は、前記スパッタ膜よりも内側の前記貫通孔を充填し、
前記第1接続端子は、前記ビア配線の上面及び前記スパッタ膜の上面に形成されていることを特徴とする請求項1又は2に記載の配線基板。 - 前記保護絶縁層の上面には、隣接する前記第1接続端子の間において、前記絶縁層側に向かって円弧状に凹む凹部が形成されていることを特徴とする請求項1〜3のいずれか一項に記載の配線基板。
- 請求項1〜4のいずれか一項に記載の配線基板と、
回路形成面に形成された第2接続端子がはんだ層を介して前記第1接続端子に電気的に接続された前記電子部品と、を有し、
前記第1接続端子の前記上部の上面は、前記はんだ層と直接接合されていることを特徴とする半導体装置。 - 前記はんだ層は、錫を含むはんだからなり、
前記第1接続端子と前記はんだ層との界面には、銅と錫の合金からなる合金層が形成されていることを特徴とする請求項5に記載の半導体装置。 - 配線層を形成する工程と、
前記配線層を被覆する絶縁層を形成する工程と、
前記絶縁層を厚さ方向に貫通して前記配線層の上面を露出する貫通孔を形成する工程と、
前記貫通孔内にビア配線を形成するとともに、前記ビア配線を介して前記配線層と電気的に接続され、前記絶縁層の上面から上方に突出する柱状の第1接続端子を形成する工程と、
前記第1接続端子の上面及び側面を粗化する工程と、
前記絶縁層の上面に、前記第1接続端子の側面を被覆する保護絶縁層を形成する工程と、を有し、
前記第1接続端子を形成する工程では、電流密度を第1の値に設定した電解めっき法により前記第1接続端子の下部を形成した後に、前記電流密度を前記第1の値よりも小さい第2の値に設定した電解めっき法により前記第1接続端子の上部を形成することにより、前記上部における結晶粒径が前記下部における結晶粒径よりも大きくなるように前記第1接続端子を形成し、
前記第1接続端子の上面及び側面を粗化する工程では、前記下部の表面粗度が前記上部の表面粗度よりも大きくなるように粗化し、
前記保護絶縁層を形成する工程では、前記下部の側面全面と前記上部の側面の一部とを被覆するように前記保護絶縁層を形成し、
前記保護絶縁層を形成する工程の後に、前記保護絶縁層から露出する前記上部の上面及び側面を平滑化する工程を有することを特徴とする配線基板の製造方法。 - 前記保護絶縁層を形成する工程は、
前記絶縁層の上面にポジ型の感光性樹脂を塗布し、前記第1接続端子の側面全面及び上面全面を被覆する感光性樹脂層を形成する工程と、
前記感光性樹脂層を未露光の状態で現像液によって溶解させて薄化することにより、前記保護絶縁層を形成する工程と、を有することを特徴とする請求項7に記載の配線基板の製造方法。
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