JP4969113B2 - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
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- JP4969113B2 JP4969113B2 JP2006044882A JP2006044882A JP4969113B2 JP 4969113 B2 JP4969113 B2 JP 4969113B2 JP 2006044882 A JP2006044882 A JP 2006044882A JP 2006044882 A JP2006044882 A JP 2006044882A JP 4969113 B2 JP4969113 B2 JP 4969113B2
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- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
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- 229910000679 solder Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
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- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- H01L23/495—Lead-frames or other flat leads
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- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
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- H05K3/0011—Working of insulating substrates or insulating layers
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- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
本形態では、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図2から図4を参照して、混成集積回路装置の製造方法を説明する。
11 回路基板
12 絶縁層
13 導電パターン
14 封止樹脂
15A、15B 半導体素子
15C チップ素子
17 金属細線
13A パッド
22A 上金型
22B 下金型
23 キャビティ
25 リード
40 リードフレーム
41 外枠
42 第1アライメント孔
46 ユニット
50 基板
51 外枠
52 連結部
53 第2アライメント孔
54 アライメントピン
Claims (6)
- 導電パターンに接続された回路素子が上面に配置された複数個の前記回路基板が一体に連結された基板と、前記回路基板の上面に設けたパッドに接続される複数個のリードから成るユニットを前記回路基板毎に有するリードフレームとを、重畳した状態で用意する工程と、
前記基板と前記リードフレームとが重畳された状態で、前記回路素子および前記回路基板を封止樹脂で被覆する工程と、
前記封止樹脂で被覆後、各々の前記回路基板を前記基板から分離し、前記リードフレームから前記リードを分離する工程と、
を有することを特徴とする回路装置の製造方法。 - 前記リードフレームを貫通して設けた第1アライメント孔と、前記基板を貫通して設けた第2アライメント孔に、アライメントピンを嵌合することにより、前記基板と前記リードフレームとを位置合わせすると共に連結することを特徴とする請求項1に記載の回路装置の製造方法。
- 前記基板と前記リードフレームとは、略同一の平面的な大きさを有することを特徴とする請求項1または請求項2記載の回路装置の製造方法。
- 前記分離する工程では、打ち抜き加工により、前記回路基板および前記リードが分離されることを特徴とする請求項1から請求項3の何れかに記載の回路装置の製造方法。
- 前記基板の表面を被覆するBステージ状態の絶縁層を介して、前記リードフレームが前記基板に貼着されることを特徴とする請求項1から請求項4の何れかに記載の回路装置の製造方法。
- 前記基板は、額縁形状の外枠と、前記外枠と前記回路基板とを連結する連結部とを有し、
前記分離する工程では、前記連結部分を切断することにより、前記回路基板が前記外枠から分離することを特徴とする請求項1から請求項5の何れかに記載の回路装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006044882A JP4969113B2 (ja) | 2006-02-22 | 2006-02-22 | 回路装置の製造方法 |
CN2006101531751A CN101026110B (zh) | 2006-02-22 | 2006-12-05 | 电路装置的制造方法 |
US11/622,198 US7521290B2 (en) | 2006-02-22 | 2007-01-11 | Method of manufacturing circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006044882A JP4969113B2 (ja) | 2006-02-22 | 2006-02-22 | 回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007227502A JP2007227502A (ja) | 2007-09-06 |
JP4969113B2 true JP4969113B2 (ja) | 2012-07-04 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006044882A Active JP4969113B2 (ja) | 2006-02-22 | 2006-02-22 | 回路装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7521290B2 (ja) |
JP (1) | JP4969113B2 (ja) |
CN (1) | CN101026110B (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102437061A (zh) * | 2011-11-30 | 2012-05-02 | 深圳市威怡电气有限公司 | 电子元件及其封装方法 |
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