JP4845090B2 - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
- Publication number
- JP4845090B2 JP4845090B2 JP2005218722A JP2005218722A JP4845090B2 JP 4845090 B2 JP4845090 B2 JP 4845090B2 JP 2005218722 A JP2005218722 A JP 2005218722A JP 2005218722 A JP2005218722 A JP 2005218722A JP 4845090 B2 JP4845090 B2 JP 4845090B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- metal substrate
- groove
- insulating layer
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
本形態では、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図3から図6を参照して、混成集積回路装置10の製造方法を説明する。本形態の製造方法では、溝部18を設けた金属基板21を打ち抜き加工により分割して、個別の回路基板11を形成している。更に本形態では、多数個のリード25が設けられたリードフレーム40を用いて、混成集積回路装置10を製造する。
11 回路基板
12 絶縁層
13 導電パターン
13A パッド
14 封止樹脂
15A 半導体素子
15B チップ素子
17 金属細線
18 溝部
20 接合材
21 金属基板
22A 上金型
22B 下金型
23 キャビティ
25 リード
26 エッチングマスク
27 上金型
28 下金型
32 バリ
40 リードフレーム
41 外枠
42 接続部
43 吊りリード
44 タイバー
45 ランド
46 ユニット
Claims (3)
- 形成予定の多数の回路基板が形成できる大型の金属基板の主面に於いて、前記形成予定の回路基板の外周に渡って前記主面を窪ませて溝部を形成する工程と、
前記溝部も含めた前記金属基板の主面にフィラーが充填された絶縁層を被覆する事で、前記溝部の前記絶縁層を前記金属基板の主面の絶縁層よりも低くする工程と、
前記金属基板の表面に金属箔を貼着し、前記金属箔をパターニングして導電パターンを形成する工程と、
前記金属基板を打ち抜き加工用の金型で打ち抜くに際し、前記溝部が設けられた箇所で前記金属基板を個別の回路基板に分割する工程と、
前記回路基板表面の導電パターンに半導体素子を実装する工程と、を具備し、
前記分割する工程では、前記金属基板の下面を下金型で支えつつ、前記溝部で囲まれる領域の前記金属基板を上金型で上方から打ち抜くことにより、上面の端部に前記溝部が設けられた前記回路基板を前記金属基板から分離することを特徴とする回路装置の製造方法。 - 前記溝部には、前記金属基板の上方へ突出するバリを有し、前記バリの突出量を抑止する請求項1記載の回路装置の製造方法。
- 前記打ち抜き加工により、前記溝部の内部にクラックを発生させ、前記金属基板の他の領域に発生するクラックが抑制される請求項1に記載の回路装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005218722A JP4845090B2 (ja) | 2005-07-28 | 2005-07-28 | 回路装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005218722A JP4845090B2 (ja) | 2005-07-28 | 2005-07-28 | 回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007036013A JP2007036013A (ja) | 2007-02-08 |
JP4845090B2 true JP4845090B2 (ja) | 2011-12-28 |
Family
ID=37794888
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005218722A Expired - Fee Related JP4845090B2 (ja) | 2005-07-28 | 2005-07-28 | 回路装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4845090B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104952856A (zh) * | 2015-06-27 | 2015-09-30 | 华东光电集成器件研究所 | 一种双面组装集成电路 |
WO2018043876A1 (ko) * | 2016-08-31 | 2018-03-08 | 삼성전자 주식회사 | 전자 부품 및 그를 포함하는 전자 장치 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6005997B2 (ja) * | 2012-05-24 | 2016-10-12 | 日本発條株式会社 | 金属ベース回路基板のエッジ形成方法及び金属ベース回路基板 |
US9397017B2 (en) | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
JP6501638B2 (ja) | 2015-06-11 | 2019-04-17 | オムロンオートモーティブエレクトロニクス株式会社 | 電子装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6150350A (ja) * | 1984-08-18 | 1986-03-12 | Nichicon Capacitor Ltd | 混成集積回路基板 |
JPH08307053A (ja) * | 1995-04-28 | 1996-11-22 | Matsushita Electric Works Ltd | 金属コアプリント配線板の製造方法 |
JPH09289263A (ja) * | 1996-04-19 | 1997-11-04 | Mitsubishi Plastics Ind Ltd | Icパッケージ用メタルコア基板の製造方法 |
JP2000133913A (ja) * | 1998-10-28 | 2000-05-12 | Ngk Spark Plug Co Ltd | プリント配線板の製造方法及び金属板 |
JP3806550B2 (ja) * | 1999-08-06 | 2006-08-09 | 三洋電機株式会社 | 混成集積回路装置 |
JP2005123606A (ja) * | 2003-09-25 | 2005-05-12 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
JP2005005730A (ja) * | 2004-08-13 | 2005-01-06 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
-
2005
- 2005-07-28 JP JP2005218722A patent/JP4845090B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104952856A (zh) * | 2015-06-27 | 2015-09-30 | 华东光电集成器件研究所 | 一种双面组装集成电路 |
WO2018043876A1 (ko) * | 2016-08-31 | 2018-03-08 | 삼성전자 주식회사 | 전자 부품 및 그를 포함하는 전자 장치 |
KR20180024678A (ko) * | 2016-08-31 | 2018-03-08 | 삼성전자주식회사 | 전자 부품 및 그를 포함하는 전자 장치 |
US10922513B2 (en) | 2016-08-31 | 2021-02-16 | Samsung Electronics Co., Ltd. | Electronic component and electronic device comprising same |
KR102528424B1 (ko) | 2016-08-31 | 2023-05-04 | 삼성전자주식회사 | 전자 부품 및 그를 포함하는 전자 장치 |
Also Published As
Publication number | Publication date |
---|---|
JP2007036013A (ja) | 2007-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8203848B2 (en) | Circuit device and method of manufacturing the same | |
US7529093B2 (en) | Circuit device | |
JP4785139B2 (ja) | 回路装置およびその製造方法 | |
JP5802695B2 (ja) | 半導体装置、半導体装置の製造方法 | |
US8133759B2 (en) | Leadframe | |
US7957158B2 (en) | Circuit device | |
JP4845090B2 (ja) | 回路装置の製造方法 | |
US8592962B2 (en) | Semiconductor device packages with protective layer and related methods | |
US7439614B2 (en) | Circuit device with dummy elements | |
CN107039387B (zh) | 引线框架、半导体装置及引线框架的制造方法 | |
US9331041B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
US20080099922A1 (en) | Circuit device and manufacturing method thereof | |
JP2006100759A (ja) | 回路装置およびその製造方法 | |
JP5341339B2 (ja) | 回路装置 | |
JP4918391B2 (ja) | 半導体装置 | |
JP2010109255A (ja) | 半導体装置 | |
JP2008166621A (ja) | 半導体装置およびその製造方法 | |
JP4942452B2 (ja) | 回路装置 | |
JP4610426B2 (ja) | 回路装置の製造方法 | |
JP2008034728A (ja) | 回路装置およびその製造方法 | |
JP5104020B2 (ja) | モールドパッケージ | |
JP4676252B2 (ja) | 回路装置の製造方法 | |
JP2010010569A (ja) | 回路装置およびその製造方法 | |
US20170018487A1 (en) | Thermal enhancement for quad flat no lead (qfn) packages | |
KR101107756B1 (ko) | 리드 프레임 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080718 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100811 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100816 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101012 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20110531 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110704 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110829 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111005 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111006 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141021 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |