JP4927356B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4927356B2 JP4927356B2 JP2005201157A JP2005201157A JP4927356B2 JP 4927356 B2 JP4927356 B2 JP 4927356B2 JP 2005201157 A JP2005201157 A JP 2005201157A JP 2005201157 A JP2005201157 A JP 2005201157A JP 4927356 B2 JP4927356 B2 JP 4927356B2
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- Prior art keywords
- voltage
- transistor
- circuit
- bit line
- threshold voltage
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 27
- 230000010355 oscillation Effects 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 230000004044 response Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 18
- 230000007547 defect Effects 0.000 description 17
- 230000007423 decrease Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000005086 pumping Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- VLQGDKKHHCKIOJ-UHFFFAOYSA-N NNOS Chemical compound NNOS VLQGDKKHHCKIOJ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
I1=(VREF1−V(N2))/R1 (1)
となる。ここで、コンパレータ30のプラス側入力端子とマイナス側入力端子が同レベルになるようにフィードバックがかかり、電圧V(N2)はビット線プリチャージ電圧VHBと同レベルになるように制御されるので、(1)式の電流I1は、
I1=(VREF1−VHB)/R1 (2)
と表すことができる。この電流I1は、PMOSトランジスタTP2を流れるドレイン電流に概ね一致する。なお、例えば、基準電圧VREFは1.6V、ビット線プリチャージ電圧VHBは0.6Vに設定される。
VGS=V1−V(N2)=V1−VHB (3)
と表すことができる。既に述べたように、|IDS|=1μAのときのVGSが、しきい値電圧Vtpとして定義され、|IDS|=I1であることから、(2)式に基づき、
(VREF1−VHB)/R1=1μA (4)
を満たすように抵抗R1を設定すればよい。この状態では、PMOSトランジスタTP2におけるゲートソース間電圧VGSがしきい値電圧Vtpに一致するため(3)式から、
V1=VHB+Vtp (5)
を導くことができる。
VGS=V(N4)−VHB (6)
と表すことができる。上述したように、コンパレータ30へのフィードバックにより、電圧V(N4)が電圧V1と同レベルになるように制御されるので、(6)式は、
VGS=V1−VHB (7)
と表すことができる。さらに、|IDS|=1μAであるとすると、このときのVGSがしきい値電圧Vtpに一致するので、(7)式は、
V1=VHB+Vtp (8)
を導くことでき、第1の実施例と同様の結果が得られることがわかる。
I3=(V1−VBB)/R3 (9)
となり、しきい値電圧Vtpに連動する電圧V1の変動により変化する。よって、電流I3に対応する制限電流についても、(9)式による若干の変動を考慮する必要がある。
11…電流制限回路
12…スイッチ回路
13…センスアンプ
14…ショート欠陥
15…ゲート電圧発生回路
16…電流制限素子
20、24、25…レベル検知部
21…基準電圧源
22…リングオシレータ
23…チャージポンプ
30…コンパレータ
101、102、103…NMOSトランジスタ
201…NAND回路
202、203…インバータ
204…容量
BLT、BLN…ビット線
WL…ワード線
MC…メモリセル
R1、R3…抵抗
R2…可変抵抗
TP1…PMOSトランジスタ(本発明の第1のPMOSトランジスタ)
TP2、TP3…PMOSトランジスタ(本発明の第2のPMOSトランジスタ)
Claims (7)
- 複数のメモリセルと、
前記複数のメモリセルのうちの関連する複数個のメモリセルに接続された第1のビット線対と、
前記第1のビット線対に接続された第1のイコライズ回路と、
ビット線プリチャージ電圧が供給されたノードと、
前記第1のイコライズ回路と前記ノードとの間に接続された第1のトランジスタと、
前記第1のトランジスタの制御電極に接続され、前記第1のトランジスタの前記制御電極に制御電圧を供給する電圧発生回路であって、当該電圧発生回路は、前記第1のトランジスタが前記第1のトランジスタのしきい値電圧の変動にかかわらず実質的に一定の電流供給能力を備えるように、前記制御電圧を前記第1のトランジスタの前記しきい値電圧の変動に追随して変化させる前記電圧発生回路と、
を備え、
前記電圧発生回路は、前記ノードに電気的に接続された第1の入力端子と、前記第1のトランジスタの前記しきい値電圧に関連した電圧を生成する回路素子を介して前記第1のトランジスタの前記制御電極に接続された第2の入力端子と、を有するコンパレータを備えることを特徴とする半導体装置。 - 夫々が、前記複数のメモリセルのうちの関連する複数個のメモリセルに接続された複数の第2のビット線対と、
夫々が、前記複数の第2のビット線対のうちの関連する1つの第2のビット線対と接続された複数の第2のイコライズ回路と、
夫々が、前記複数の第2のイコライズ回路のうちの関連する1つのイコライズ回路と前記ノードとの間に接続された複数の第2のトランジスタと、を含み、
前記電圧発生回路は、前記複数の第2のトランジスタの各々の制御電極に前記制御電圧を供給することを特徴とする請求項1に記載の半導体装置。 - 前記回路素子は、前記第1のトランジスタの前記しきい値電圧と実質的に同一に変化するしきい値電圧を備える第3のトランジスタを含むことを特徴とする請求項1又は2に記載の半導体装置。
- 前記電圧発生回路は、前記コンパレータの出力信号に応じて、前記制御電圧を出力する制御部を備えることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記制御部は、前記コンパレータの前記出力信号によって発振が制御されるオシレータと、前記オシレータの発振出力に応答して前記制御電圧を発生するチャージポンプとを備えることを特徴とする請求項4に記載の半導体装置。
- 前記電圧発生回路は、前記第1のトランジスタの前記しきい値電圧と実質的に同一に変化するしきい値電圧を備える第2のトランジスタを含み、前記電圧発生回路は、前記第2のトランジスタの前記しきい値電圧の変動を前記第1のトランジスタの前記しきい値電圧の変動として検出することを特徴とする請求項1に記載の半導体装置。
- 半導体基板中に形成されたウェルであって、実質的に一定のバックバイアス用電圧が供給される前記ウェルを備え、
前記第1のトランジスタが前記ウェルに形成されることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201157A JP4927356B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
TW095124299A TW200710847A (en) | 2005-07-11 | 2006-07-04 | Current limit circuit and semiconductor memory device |
DE102006031862A DE102006031862B4 (de) | 2005-07-11 | 2006-07-10 | Strombegrenzungsschaltung und Halbleiterspeichervorrichtung |
KR1020060065009A KR100842696B1 (ko) | 2005-07-11 | 2006-07-11 | 전류 제한 회로 및 반도체 기억 장치 |
US11/483,662 US7633820B2 (en) | 2005-07-11 | 2006-07-11 | Current limit circuit and semiconductor memory device |
CNB2006101019091A CN100533591C (zh) | 2005-07-11 | 2006-07-11 | 电流限制电路及半导体存储装置 |
US12/606,756 US8354877B2 (en) | 2005-07-11 | 2009-10-27 | Current limit circuit and semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201157A JP4927356B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007018636A JP2007018636A (ja) | 2007-01-25 |
JP4927356B2 true JP4927356B2 (ja) | 2012-05-09 |
Family
ID=37609635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005201157A Active JP4927356B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7633820B2 (ja) |
JP (1) | JP4927356B2 (ja) |
KR (1) | KR100842696B1 (ja) |
CN (1) | CN100533591C (ja) |
DE (1) | DE102006031862B4 (ja) |
TW (1) | TW200710847A (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4927356B2 (ja) * | 2005-07-11 | 2012-05-09 | エルピーダメモリ株式会社 | 半導体装置 |
US7672107B2 (en) * | 2006-10-13 | 2010-03-02 | Advanced Analogic Technologies, Inc. | Current limit control with current limit detector |
US7957116B2 (en) | 2006-10-13 | 2011-06-07 | Advanced Analogic Technologies, Inc. | System and method for detection of multiple current limits |
US7532448B2 (en) * | 2006-10-13 | 2009-05-12 | Advanced Analogic Technologies, Inc. | Current limit detector |
US7576525B2 (en) * | 2006-10-21 | 2009-08-18 | Advanced Analogic Technologies, Inc. | Supply power control with soft start |
US7697354B2 (en) * | 2007-05-30 | 2010-04-13 | Qimonda Ag | Integrated circuit memory device responsive to word line/bit line short-circuit |
TW200943293A (en) * | 2008-04-08 | 2009-10-16 | Nanya Technology Corp | Method for suppressing current leakage in memory |
US7869258B2 (en) * | 2008-06-27 | 2011-01-11 | Sandisk 3D, Llc | Reverse set with current limit for non-volatile storage |
KR100968468B1 (ko) | 2008-12-30 | 2010-07-07 | 주식회사 하이닉스반도체 | 비트라인 프리차지 회로 및 이를 이용하는 반도체 메모리 장치 |
CN102119424B (zh) * | 2009-04-15 | 2014-03-26 | 松下电器产业株式会社 | 电阻变化型非易失性存储装置 |
KR20120063136A (ko) * | 2010-12-07 | 2012-06-15 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 구동방법 |
JP2014126947A (ja) * | 2012-12-25 | 2014-07-07 | Toshiba Corp | 半導体装置 |
KR101351906B1 (ko) * | 2013-09-10 | 2014-01-20 | (주)비엔씨넷 | 실리콘 콘덴서 마이크로폰 |
DE102016104987B4 (de) * | 2016-03-17 | 2024-05-23 | Infineon Technologies Ag | Speicheranordnung und Verfahren zum Lesen einer Speicherzelle eines Speichers |
JP2019146300A (ja) * | 2018-02-16 | 2019-08-29 | 株式会社東芝 | ドライバ回路 |
JP6535784B1 (ja) * | 2018-04-25 | 2019-06-26 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
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JP4927356B2 (ja) * | 2005-07-11 | 2012-05-09 | エルピーダメモリ株式会社 | 半導体装置 |
KR100604947B1 (ko) * | 2005-08-17 | 2006-07-31 | 삼성전자주식회사 | 고속 메모리 장치에 채용되는 이퀄라이저 및 데이터 라인센스앰프의 배치 방법 |
-
2005
- 2005-07-11 JP JP2005201157A patent/JP4927356B2/ja active Active
-
2006
- 2006-07-04 TW TW095124299A patent/TW200710847A/zh unknown
- 2006-07-10 DE DE102006031862A patent/DE102006031862B4/de active Active
- 2006-07-11 CN CNB2006101019091A patent/CN100533591C/zh active Active
- 2006-07-11 US US11/483,662 patent/US7633820B2/en active Active
- 2006-07-11 KR KR1020060065009A patent/KR100842696B1/ko active IP Right Grant
-
2009
- 2009-10-27 US US12/606,756 patent/US8354877B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2007018636A (ja) | 2007-01-25 |
US8354877B2 (en) | 2013-01-15 |
DE102006031862A1 (de) | 2007-03-01 |
CN100533591C (zh) | 2009-08-26 |
CN1897155A (zh) | 2007-01-17 |
US7633820B2 (en) | 2009-12-15 |
TWI343576B (ja) | 2011-06-11 |
KR20070007739A (ko) | 2007-01-16 |
DE102006031862B4 (de) | 2011-07-07 |
KR100842696B1 (ko) | 2008-07-01 |
TW200710847A (en) | 2007-03-16 |
US20100039171A1 (en) | 2010-02-18 |
US20070008795A1 (en) | 2007-01-11 |
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